116 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 12, NO.

1, JANUARY 1997

A New Mathematical Model and Control of a

Three-Phase AC–DC Voltage Source Converter
Vladimir Blasko, Member, IEEE, and Vikram Kaura, Member, IEEE

Abstract—A new mathematical model of the power circuit of a model are drawn to facilitate the analysis on an intuitive
three-phase voltage source converter (VSC) was developed in the basis. This model is then used to synthesize the voltage and
stationary and synchronous reference frames. The mathematical current control loops for the VSC and study the dynamics
model was then used to analyze and synthesize the voltage and
current control loops for the VSC. Analytical expressions were of these control loops. Analytical expressions are presented
derived for calculating the gains and time constants of the current for the gains and time constants of the voltage and current
and voltage regulators. The mathematical model was used to regulators. The model allows for a straightforward algorithm
control a 140-kW regenerative VSC. The synchronous reference- for decoupling control of the active and reactive current
frame model was used to define feedforward signals in the current components. Complete control of the VSC based on this model
regulators to eliminate the cross coupling between the d and q
phases. It allowed the reduction of the current control loops to is implemented in a digital signal processor (DSP) running at
first-order plants and improved their tracking capability. The a clock speed of 40 MHz with a sampling rate of 10 kHz.
bandwidths of the current and voltage-control loops were found
to be approximately 20 and 60 times (respectively) smaller than
the sampling frequency. All control algorithms were implemented II. THE MATHEMATICAL MODEL
in a digital-signal processor. All results of the analysis were A three-phase mathematical model for the VSC was derived
experimentally verified.
in [4]–[5]. The power unit used was similar to the one shown
Index Terms— Control, converter, low harmonic distortion, in Fig. 1. Assuming a balanced three-phase system without the
mathematical model, unity power neutral connection and neglecting the resistance of the power
switches, the VSC can be modeled as
I. INTRODUCTION
(1)
T HREE-PHASE voltage source converters (VSC’s) can
provide constant dc bus voltage, low harmonic distor-
tion of the utility currents, bidirectional power flow, and
controllable power factor. Because of these features, they (2)
are becoming increasingly popular in high-power or high-
performance drive applications requiring frequent acceleration
(3)
and deceleration. In these applications, the cost of the energy
wasted during braking becomes too high and can justify the
additional cost of a VSC as an integral part of the drive or where
as a stand-alone unit. index for the three-phases ;
The three-phase regenerative VSC is a relatively new ap- switching functions;
paratus and has attracted much development effort in recent line currents;
times. References [1]–[4] present the control principles of phase voltages;
a VSC with three-phase stationary reference-frame current bus voltage;
regulators and analyze the associated voltage, current, and bus current;
power conditions. An exhaustive analysis of the VSC is given resistance of the line reactor;
in [5] for a steady-state dc model, a low-frequency small-signal inductance of the line reactor.
ac model, and a high-frequency model. These models, while This three-phase model is represented as a block diagram
complete in their analysis, are difficult to apply for control in Fig. 2. A two-phase coordinate system ( – ) is defined
purposes because of their complexity. in Fig. 3 along with a three-phase system (1, 2, 3). The
In this paper a new mathematical model of a VSC is transformation of variables between these two coordinate
presented from the control point of view. The new model, systems is given by the following:
based on the – representation, is derived in the stationary
and synchronous frames of reference. Block diagrams of the
(4)
Manuscript received June 5, 1995; revised June 5, 1996.
The authors are with the Rockwell Automation–Allen Bradley Company, (5)
Standard Drives Division, Mequon, WI 53092 USA.
Publisher Item Identifier S 0885-8993(97)00620-0. (6)
0885–8993/97$10.00  1997 IEEE

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BLASKO AND KAURA: AC–DC VOLTAGE SOURCE CONVERTER 117

Fig. 1. Circuit diagram of a three-phase VSC.

Fig. 4. Stationary reference-frame d–q model of a three-phase VSC.

A two-phase stationary reference-frame – model of the

VSC is obtained by applying (4) and (5) to (1)–(3)

(7)

(8)

(9)

A block diagram of this two-phase model in the stationary

reference-frame is shown in Fig. 4. Using the complex vector
notation of (6), (7)–(9) can be written in a more compact form
as
(10)

(11)
Fig. 2. Block diagram for the power circuit of a three-phase VSC.
where denotes the complex conjugate vector.
The complex vector representation of the two-phase model
in a stationary reference frame [(10) and (11)] can be trans-
formed to a complex vector representation of the two-phase
model in the synchronous reference frame using the following
transformation
(12)

where
superscript for synchronous reference-frame;
utility frequency (constant).
Fig. 3. Orientation of three-phase and d–q systems in a complex plane. Applying (12) to (10) and (11), the following two-phase
synchronous reference-frame model in the complex vector
where notation is obtained
(13)

the two-phase system variables (14)

Separating (13) and (14) into and components results in

the three-phase system variables
the following:

(15)
is a complex vector rotating counterclockwise.

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118 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 12, NO. 1, JANUARY 1997

Fig. 5. Synchronous reference-frame d–q model of a three-phase VSC.

(16)

(17) Fig. 6. Control diagram of the VSC.

A block diagram of this two-phase model (15)–(17) in

the synchronous reference frame is shown in Fig. 5. Note
that the synchronous reference-frame model in Fig. 5 can be
transformed into the stationary reference-frame model in Fig. 4
by inserting . This new model in Fig. 5 forms the basis
for the analysis which follows.
only work which is performed by the regulators during normal
operation is to correct for the errors in the parameters used
for the above compensations. The current regulators become
more active during operation of the VSC at an increased utility
voltage when the PWM transitions toward a six-step mode of
operation [8].

III. CONTROL OF THE VSC

IV. DIGITAL CURRENT REGULATORS
A functional control diagram of the VSC is presented in
Fig. 6. Complete control with the current and voltage-feedback A. Synthesis and Analysis
loops was implemented in a DSP. The reference angle gen-
erator synchronizes reference angle with the line volt- Decoupling the and axes reduces the synchronous
ages. Transformation block 3 /2 transforms the three-phase reference-frame current control plant to a first-order delay and
currents ( ) from the stationary frame of reference improves the tracking capability of the current regulators. It
to the synchronous frame of reference ( ). Synchronous simplifies the analysis and enables the derivation of analytical
reference-frame proportional integral (PI) current regulators expressions for the parameters of current regulators. A block
( reg, reg) regulate the and current components. diagram for such a simplified current control loop in the
The command for reg is generated by PI voltage synchronous reference-frame is shown in Fig. 7. Because the
regulator which regulates dc bus voltage . For unity same diagram applies to both the and axis regulators, the
power factor, command for reg is set to zero. The subscripts and are omitted. Variables and are used for
output signals and from the current regulators the command and feedback currents, respectively. The gains
are inputted to the compensation/transformation/pulse width and time constants associated with the various elements of the
modulation (PWM) block. To better utilize the dc bus voltage block diagram are as follows:
in the presence of utility voltage fluctuations and reduce the sampling time;
commutation losses of power devices, two-phase modulation disturbance voltage;
was implemented [8]. The effect of blanking time [9] was gain of PI regulator;
compensated for in the software. The cross coupling between time constant of PI regulator;
the and axes due to inductance was compensated using gain of the PWM block;
feedforward signals. The derivation of the algorithm for cross- time constant of the PWM block ;
coupling compensation and compensation of utility voltage is gain of the - load ;
straightforward from the synchronous reference-frame model time constant of the - load.
of the VSC in Fig. 5. The power unit, approximated with a first-order element,
Under normal operating conditons and with the proper has a time constant equal to one half of the sampling period
compensation for inductive cross-coupling, utility voltage fluc- and gain . Variations in the utility voltage and the
tuation, blanking time effect, and the outputs ( ) of the uncompensated effects of blanking time are modeled by the
current regulators are very close to zero. In other words, the disturbance signal . To further simplify the block diagram

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BLASKO AND KAURA: AC–DC VOLTAGE SOURCE CONVERTER 119

Fig. 7. Block diagram of the current control loop.

in Fig. 7, the two blocks with the smallest time constants

(sample, hold, and the PWM) are grouped together to form
a single block with gain and equivalent time constant
Fig. 8. Simulated response of the current control loop to step change in
reference iec and disturbance udis .
(18)
specify the lowest of the frequencies corresponding to these
The dominant pole in the load can be canceled by setting
conditions as the bandwidth. In a system with the sampling
the integral time constant of the PI regulator equal to that of
delay approximated with a first-order element and all of the
the load
small time constants being lumped together into an equivalent
(19) time constant, the phase becomes 45 at frequency lower
than the frequency at which the gain reduces to 3 dB.
With the simplification of (18) and the time constant selection With the current loop adjusted to be critically damped, the
of (19), the closed-loop transfer function of the system in bandwidth is obtained from (23) as
Fig. 7 becomes
(24)
(20)
From (24) it follows that the bandwidth of the current regulator
From (20) the damping factor is given as is approximately 20 times smaller than the sampling frequency.
However, due to the approximations made in the derivation of
(21) (23), (24) gives an estimate of the bandwidth which is accurate
enough for practical purposes.
For the technical optimum [6], . Thus, the pro- The adjustment of the current regulator according to (19)
portional gain of the PI regulator can be calculated from and (22) provides good response with about a 4% overshoot
(21) as to a step change of reference. The time constant of the
input choke is usually large ( 100 ms for units of 10 kW or
(22) more). According to (19), this would result in a large time
constant, , of the PI regulator and hence, poor rejection
The closed-loop transfer function (20) can be further sim- capability for disturbance . To improve the disturbance-
plified by neglecting the term (because of the very small rejection capability, the time constant of the PI regulator can
product term ). After introducing from (21) into be selected to be ten times higher than the smallest equivalent
simplified (20), the following first-order approximation is time constant in the system
obtained [6] (25)
(23) Such an adjustment would increase an overshoot to the step
change of the reference; it would not reduce the bandwith of
where ; for a critically damped system, the system with a conservative prediction according to (24).
and . A 140-kW 460-V system with s, mH,
The term often used to roughly specify the quality of a and m was simulated and tested. The simulation
control loop is “bandwidth”: a frequency at which gain of was done with current control with: 1) a reduced order model
the closed loop is reduced to 3 dB, and the phase delay according to Fig. 7 and 2) a complete nonlinear model based
becomes larger than 45 (assuming that closed-loop behavior on Figs. 5 and 6 with the PWM modeled as an amplifier.
can be approximated by a first-order delay element). In reality, The results of the simulation with the reduced model in
a closed-loop transfer function is seldom a first-order element, Fig. 7 with the proportional gain selected according to (22) and
and reduction of the gain to 3 dB and phase to 45 does not the time constant selected according to (25) are presented in
happen at the same frequency. The conservative approach is to Fig. 8. Note the overshoot of approximately 20% and the fast

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120 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 12, NO. 1, JANUARY 1997

Fig. 9. Simulated step response of d and q current regulators without cross

coupling for integral time constants Ti = TLR and Ti = 10Tei . Fig. 10. Measured response of the current to a step change of reference
current.

response to disturbance voltage . With the time constant

selected according to (19), the system is critically damped
with an overshoot of 4%.
The results of the simulation with a complete nonlinear
model with the proportional gains selected according to (22)
and the time constants selected according to (19) and (25)
are presented in Fig. 9. The cross coupling due to inductance
was not compensated for in this simulation to investigate
its influence on the dynamics of current control loops. The
response to load disturbance is slow when is selected
according to (19). The current component generated without
cross-coupling compensation slowly approaches zero. With a
much smaller selected according to (25), the overshoot to
the step change in command increased from 4% (typical Fig. 11. Measured amplitude and phase response of the closed loop of the
synchronous reference-frame current regulator.
for the technical optimum) to an acceptable level of 20%.
Under this condition, a fast rejection of load disturbance is
observed, and the cross-coupled current component decays
rapidly. With the cross-coupling compensation enabled, the of approximately 20% is obtained with the feedback current
developed due to a change of becomes negligibly small reaching the commanded value in approximately four sampling
whether (19) or (25) are used to set . Cross-coupling intervals.
compensation substantially improves the tracking capability The bode plot with the amplitude and phase responses of
of current regulators, particularly if the integral time constant the current loop were measured on the same unit. The results
is large. With the cross-coupling compensation enabled, the are show in Fig. 11. Note the flat amplitude response with 3
complete nonlinear model of the VSC and the reduced model dB at approximately 1.2 kHz and a phase delay higher than
in Fig. 7 provide very similar results. 45 after approximately 400 Hz. The theoretical prediction of
the bandwidth using (24) was 500 Hz.
B. Experimental Results
V. DC BUS VOLTAGE REGULATOR
Experimental verification was done on a 140-kW 460-V
VSC. The complete control was implemented in a DSP with
A. Synthesis and Analysis
a clock speed of 40 MHz and a sampling rate of 10 kHz.
Because of the decoupling control of the current regulators, The dc bus-voltage control loop can be modeled with
the and axis regulators produce identical results. To be the block diagram of Fig. 12. The gains and time constants
comprehensive, experimental results are shown for only one associated with the various elements of the block diagram are
of the axes. as follows:
Actual waveforms from one of the current regulators, feedback-loop delay due to sampling, processing time,
reg, are shown in Fig. 10. The gain was selected and feedback filter;
according to (22) and the time constant according to (25). gain of the PI regulator;
As expected from the simulation results (Fig. 8), an overshoot time constant of the PI regulator.

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BLASKO AND KAURA: AC–DC VOLTAGE SOURCE CONVERTER 121

Fig. 12. Block diagram of the dc bus-voltage control loop.

The inner current control loop is modeled with the first-

Fig. 13. Response of dc bus-voltage udc to the step change of reference
order transfer function (23). Combining the two smallest udc c and disturbance idis .
time constants in Fig. 12 ( and 2 of ), equivalent
time constant is obtained
Simulation results for the VSC, tuned according to the
(26) above method, are shown in Fig. 13. Substantial overshoot in
response due to a step change in command , typical
The open-loop transfer function is thus given by for the technical optimum, is noticeable. This overshoot is not
of concern because typically the bus-voltage command of a
(27) VSC is kept constant. At power-up conditions, this overshoot
can be easily reduced by limiting the rate of change of the
The method of symmetrical optimum [6], [7] is used to bus-voltage reference. The simulation also shows a strong
synthesize the control system using the open-loop transfer (load-current) disturbance-rejection capability.
function . According to this method, the amplitude and Adjustment of the bus-voltage regulator according to the
phase plot of are symmetrical about the crossover fre- method of technical optimum provides high proportional gain
quency . The crossover frequency and phase margin and a small integral time constant. This results in a fast
are related as the following: response of command and a strong rejection of disturbance. On
the other hand, a negligibly small ripple in the dc bus voltage
(28) (caused by nonsymmetrical/sinusoidal currents or voltages)
appears as a noticeable distortion of and results in the dis-
(29) tortion of the utility current. To counter this effect, additional
where filtering of the bus voltage is needed which results in reduction
of the bus-voltage regulator gain and smaller bandwidth than
(30) that predicted by (33).

Gain of the PI regulator at the crossover frequency is

B. Experimental Results
given as
Experimental results obtained on a 140-kW VSC are shown
(31) in Fig. 14 for and with
ms selected according to (31) and (30). Fig. 14 shows the
Given phase margin or factor , time constant and gain open-loop gain and phase response of the bus-voltage control
of the PI regulator can be calculated using (30) and (31). loop. The amplitude and phase plots are symmetrical at about
The closed-loop transfer function is given as a frequency of 140 Hz. This is bandwidth frequency
introduced earlier, and it is satisfactorily close to the predicted
(32) value of 166 Hz.
Fig. 15 demonstrates the disturbance-rejection capabilities
The pair of complex poles of result in a damping factor; of the bus-voltage control loop under the different settings of
for [6], [7]. If only the sampling delay the voltage regulator. To reduce the ripple in the bus voltage,
is present in the voltage feedback ( ), the equivalent a filter was introduced in the voltage feedback increasing
time constant becomes . Under the to 1 ms. Factor was selected to be four. A resistive load of
above conditions, transfer function will have a gain of 4.5 was connected across the dc bus to cause a sudden
at or the bandwidth frequency disturbance in the load current. Forced by the bus-voltage
regulator, the current regulators quickly met the demand for
(33) additional load current, and the dc bus recovered to the original
value of 750 V after a small dip. An increase in the factor

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122
Fig. 14. Measured amplitude and phase response of the open-loop bus-voltage regulator.
Fig. 15. Response of dc bus voltage udc to step change in load current from
0 to 170 A; e1 and i1 are the phase voltage and current, respectively.
form 2.4 to 4 and additional delay in dc-voltage feedback
reduced the proportional gain to and increased the
integral time constant of the voltage regulator to
ms. The consequence was an increased (but still very fast and
satisfactory) response time in dc bus voltage feedback to load
disturbance.
VI. CONCLUSION
A new mathematical model of a three-phase VSC was de-
veloped in the stationary and synchronous frames of reference.
The model was then used to synthesize the voltage and current
control loops of the VSC.
Current regulators with a sampling rate of 10 kHz were
implemented in a synchronous reference-frame. The method
of technical optimum was used to derive expressions for
gains and time constants of PI current regulators. Use of
(25) rather than (19) to calculate the integral time constant
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 12, NO. 1, JANUARY 1997
provided improved load-disturbance rejection capability with
an acceptable overshoot of 20% to a step change in the
reference. The bandwidth of the current loops was predicted
and verified to be approximately 20 times smaller than the
sampling frequency.
Analytical expressions for the gain and time constant of
the bus-voltage PI regulator were derived using the method of
symmetrical optimum. Fast response of the dc bus voltage to
the reference and strong rejection to the load-current change
were obtained. The achievable bandwidth of the voltage con-
trol loop was predicted and verified to be as high as 1/60 of
the sampling frequency.
A small ripple in the dc bus voltage causes a ripple to
appear in the current reference and consequently, increases the
total harmonic distortion (THD) of the input-line currents. To
reduce this effect, it might be necessary to introduce additional
filtering in the voltage-feedback loop in exchange for the
bandwidth of the dc bus-voltage regulator.
REFERENCES
[1] B.-T. Ooi, J. C. Salmon, J. W. Dixon, and A. B. Kulkarni, “A three-
phase controlled-current PWM converter with leading power factor,”
IEEE Trans. Ind. Applicat., vol. IA-23, no. 1, pp. 78–84, Jan./Feb. 1987.
[2] J. W. Dixon and B.-T. Ooi, “Indirect current control of a unity power
factor sinusoidal current boost type three-phase rectifier,” IEEE Trans.
Ind. Electron., vol. 35, no. 4, pp. 508–515, Nov. 1988.
[3] S. B. Dewan and R. Wu, “A microprocessor-based dual PWM converter
fed four quadrant ac drive system,” in Conf. Rec. 1987 IEEE-IAS Ann.
Meeting, pp. 755–759.
[4] R. Wu, S. B. Dewan, and G. R. Slemon, “A PWM ac to dc converter
with fixed switching frequency,” in Conf. Rec. 1988 IEEE-IAS Ann.
Meeting, pp. 706–711.
[5] R. Wu, S. B. Dewan, and G. R. Slemon, “Analysis of an ac-to-dc voltage
source converter using PWM with phase and amplitude control,” IEEE
Trans. Ind. Applicat., vol. 27, no. 2, pp. 355–364, Mar./Apr. 1991.
[6] W. Leonhard, Introduction to Control Engineering and Linear Control
Systems. New Delhi: Allied, 1976.
[7] , Control of Electrical Drives. Berlin: Springer-Verlag, 1985.
[8] V. Kaura and V. Blasko, “Operation of a voltage source converter at
increased utility voltage,” in Conf. Rec. PESC-95 Ann. Meeting, Atlanta,
GA, 1995, pp. 523–528.
[9] N. Mohan, T. M. Undeland, and W. F. Robbins, Power Electronics:
Converters, Applications and Design. New York: Wiley, 1989.
BLASKO AND KAURA: AC–DC VOLTAGE SOURCE CONVERTER
Vladimir Blasko (M’89) was born in Klenovnik,
Croatia, in 1953. He received the B.Sc., M.S., and
Ph.D. degrees in electrical engineering from the
University of Zagreb, Croatia, in 1976, 1982, and
1986, respectively.
From 1976 to 1988, he worked at the Elec-
trotechnical Institute Rade Koncar, Zagreb, in the
Power Electronics and Automatic Control Depart-
ment. From 1989 to 1992, he was with the Research
and Development Center of the Otis Elevator Com-
pany, Farmington, CT. Since 1992, he has been with
the Standard Drives Division of the Rockwell Automation–Allen Bradley
Company, Mequon, WI. He has been working on the research, development,
and design of high-power transistor choppers, drives for electrical vehicles,
high-performance ac elevator drives, and low-harmonic regenerative three-
phase VSC’s. His primary areas of interest are ac drives, intelligent power
management, power electronics, applied modern control theory, and technol-
ogy.
Dr. Blasko was with the University of Wisconsin during the 1988–89
academic year as a recipient of the IREX Scholarship.
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123
Vikram Kaura (S’86–M’89) received the B.E. de-
gree in electrical engineering from Punjab Engi-
neering College, Chandigarh, India, in 1987 and
the M.S. degree in electrical engineering from the
University of Wisconsin, Madison, in 1989. He is
also currently a student at the University of Chicago
Graduate School of Business, IL.
From 1989 to 1991, he worked as a Design
Engineer with the Drive Systems Division of the
General Electric Company. Since then, he has been
with the Standard Drives Division of the Rockwell
Automation–Allen Bradley Company, Mequon, WI, where he is currently
a Project Engineer involved with the design and development of high-
performance ac drives and low-harmonic regenerative converters. His areas
of interest include real time control and applied mathematics.