4510B UP/DOWN DECADE COUNTER DESCRIPTION — The 45108 isan Edoe-Trgpered Synchronous Up/Down 8CD Counter with aClock Yeput (CP), an active HIGH Up/Down Court Control input (Up/Dn), an astive LOW Count Enebie Inout (CE), an asynchronous active HIGH Parallel Load Input IPL], four Paral! Inputs (PoP), four Paelle Outputs [OgQ3), an active LOW Terminal Count Output (TC) and an ‘overriding asynchronous Master eset input (MA) Information on the Paritel inputs (Po:P3) is loaded into the counter while the Paelet Load Input (PL) ie HIGH, independant ofall othe” input conditions except the Master Reset Input (MR) which ‘must be LOW. With the Parallel Load Input (PL) LOW, the counter ehanges on the LOM to NIGH tronsition of the Clock Input (CP) i the Count Enabie Input ICE) # LOW. The Ua/Down Count Contra! Inout {Up/On} determines the dlvection of the count, HIGH for counting up, LOW for ounting down. When counting up, the Terminal Count Output (TCl is LOW when the Parle Outputs. Ggrg_are HIGH and the Count Ensbie (CEI ie LOW. When counting dawn, the Terminal Count Outpu: IFC) is LOW when ail she Parale! Outputs (Qg-Og] and the Count Enable Input (CE are LOW. A HIGH on the Maser Reset Input resets the counter [Qg.Q3 ~ LOW) independent ofall ther input eonstions UProOWN COUNT CONTROL SINGLE CLOCK INPUT (L-H EDGE-TRIGGERED) ASYNCHRONOUS PARALLEL LOAD INPUT ASYNCHRONOUS MASTER RESET EASILY CASCADABLE MODE SELECTION TABLE [Torn ce lo MODE 4 x x |X | Poralel Load (Pa > Qn) t x # | x [Nochanae L L t F | Count Dawn, Ovcade L H t Count Up, Decade n> Low X= Dow's care BM atcha tent FS Ponve doing 45108 STATE DIAGRAM {LOGIC EQUATION FOR TERMINAL COUNT TO*CE#[(UP #5 +05) + (TF « Go eG; «G2» Sai) Locie svmaoL Lr 2601 05 Oy fut (Connection Dispram athe TTTTT CONNECTION DIAGRAM DIP (TOP View) PIN NAMES, Parallel Lood Input (Active HIGH) Parallel Inputs ‘count Enable Input (ative LOW) Clock Pulee Input (L = Edge Triggered Up/Down Count Control ‘Terminal Count Output (derive LOW Parallel Outputs 7148FAIRCHILD CMOS + 45108 Locic DIAGRAM @ ® > ® ® de) @ CF (Chock Pu Inout 8G (true and Complimentary Output Vsg * 0 ISee Note 1) = LiMiTs svupo.| earamerer | —Vop=3V Vop=10V—[—Vpp=i8v | unirs | reme | rest conprrions TaN] FvP [wax [un | TyP [MAX [mn | TYP [MAK uiescne 20 «0 80 min, 266 Pome 150 200 eo | ** | max | aninmutsat "00 | suve TT . 0°} 2 MIN,28E] OV orV0 cane [7] | | sso | 300 ooo | ** | max 7146FAIRCHILD CMOS * 45108 AC CHARACTERISTICS AND SET-UP REQUIREMENTS: Vinp a: shown, Vss = 0V, Ta 25°C ISee Note 2) cimits ‘syMmgo, PARAMETER Vop=8V[Vpp=10V | Vpp= 78 _|uwirs | rest conortions mi [TYP [MAX [Min [Ve [Max [iN [TYP [MAX ven 150 | 950 62 | 160 at | 128 Propagation Deley, CP 10 Oy os ‘eae peas 180 | 360 59160 29 | 126 i = 167 | 460 7/180 ae 1a8 PL | propagation Delay, CP 10 TE ne ent 2s2 | 680 100 | 245 66 | 196 Pu 170 | 325 70 [156 48 | 130, ‘opasation Delay, PL t0 On os won|" on 220 | 425 90 | 195 62 | 186 teu = 225 | 600 V0 ]210 os | 168 Propagation Delay, MF t0 Qn, i tema, _ | oeastion Detev. MA £2 Gn, TE 208 | 480 120 | 190 eo | 152 STLH | oupur Tanation Tome 0 | 135 a] 76 zl | sr_| O6oUt Tension Te 65 | 195 2s | we | 4 OL 500F, EyCP | GP imum Pale Wath 138 | 50 wo ta ea Be [RL -200k0 tqPL___| PL Minimum Bue Wath 150 | 60 oo [71 ae | 16 1 | Input Transition {qWltFl| MF Minimum Pulse Wiaeh 160 | 60 0] 8 | 30 ie] Times < 20 ne ‘rec _ | MR Recovery Time 175 | 75 70 [30 56 | 20 ne eee PL Recovery Time 150 | 62 0] 24 ‘ef ne 5 ‘Set. Up Time, UPION to OP 325 [145 Tao [55 70 th Hold Time, UP/DN 10 CP 0 |-90 o | 35 o | -25 = % ‘Set-Up Time, CE 10 CF 278 118 zo | 49 36 | 3s we PS Hold Time, CE 10 CP 0-40 o |-15 0 | 40 ts Set-Up Timo, Py to PL 70 | 29 wo] tt my] 8 S & Hola Time, Py to PL 0 | -40 0 | 20 2 |-20 iMAX [Input Closk Frequency (Wares) | 2] 8 5) eis ate 1 sd 40008 Swiss CMOS Family Charcierit 2. Propapetion Deleys and Output Transition [rapmiaty onseribea inthis section cinder 40008 Series CMOS Family Charatarisin, 3. Fortaaax. tout rise ond 10S ne ana les than or equal ro 20 re 4. 100 MESSomendad out input rae sna fall timer #9 the Clack Input be leat than Ve as at Vpg = SV, Aue at Veg = 10 V, and 2.ue at 767FAIRCHILD CMOS * 4510B nore: SWITCHING WAVEFORMS MINIMUM cP WIDTH, SET-UP AND HOLD TIMES, CE TO CP AND UP/DN TO cP MINIMUM PL AND MR PULSE WIDTH, RECOVERY TIME FOR PL AND MR, AND SET‘UP AND HOLD TIMES, Py TO PL. 7488