Design Information

------------------
Command Line : C:\Xilinx91i\bin\nt\map.exe -ise C:/Xilinx91i/AR/AR.ise
-intstyle ise -p xc3s5000-fg1156-5 -cm area -pr b -k 4 -c 100 -o
topfinaln_map.ncd topfinaln.ngd topfinaln.pcf
Target Device : xc3s5000
Target Package : fg1156
Target Speed : -5

Design Summary
--------------
Number of errors: 0
Number of warnings: 2
Logic Utilization:
Total Number Slice Registers: 2,331 out of 66,560 3%
Number used as Flip Flops: 4
Number used as Latches: 2,327
Number of 4 input LUTs: 4,332 out of 66,560 6%
Logic Distribution:
Number of occupied Slices: 2,974 out of 33,280 8%
Number of Slices containing only related logic: 2,974 out of 2,974 100%
Number of Slices containing unrelated logic: 0 out of 2,974 0%
Total Number of 4 input LUTs: 4,333 out of 66,560 6%
Number used as logic: 4,332
Number used as a route-thru: 1
Number of bonded IOBs: 446 out of 784 56%
IOB Latches: 284
Number of GCLKs: 8 out of 8 100%

Total equivalent gate count for design: 45,270

Additional JTAG gate count for IOBs: 21,408
Peak Memory Usage: 250 MB
Total REAL time to MAP completion: 8 secs
Total CPU time to MAP completion: 7 secs
Device Utilization Summary:

Number of BUFGMUXs 8 out of 8 100%

Number of External IOBs 446 out of 784 56%
Number of LOCed IOBs 0 out of 446 0%

Number of Slices 2974 out of 33280 8%

Number of SLICEMs 288 out of 16640 1%

elected Device : 3s5000fg1156-5

Number of Slices: 2696 out of 33280 8%
Number of Slice Flip Flops: 2331 out of 66560 3%
Number of 4 input LUTs: 4653 out of 66560 6%
Number of IOs: 638
Number of bonded IOBs: 446 out of 784 56%
IOB Flip Flops: 284
Number of GCLKs: 8 out of 8 100%

Timing Summary:
---------------
Speed Grade: -5

Minimum period: 5.763ns (Maximum Frequency: 173.516MHz)

Minimum input arrival time before clock: 13.272ns
Maximum output required time after clock: 6.141ns
Maximum combinational path delay: No path found

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| m0/m0/m1/n4/res<14> | BUFGMUX7| No | 85 | 0.504 | 1.417 |
+---------------------+--------------+------+------+------------+-------------+
| m0/m0/m1/n4/res<13> | BUFGMUX5| No | 86 | 0.535 | 1.362 |
+---------------------+--------------+------+------+------------+-------------+
| m0/m0/m1/n4/res<15> | BUFGMUX6| No | 86 | 0.577 | 1.466 |
+---------------------+--------------+------+------+------------+-------------+
| clk_BUFGP | BUFGMUX2| No | 2 | 0.000 | 1.319 |
+---------------------+--------------+------+------+------------+-------------+
| enable_BUFGP | BUFGMUX0| No | 76 | 0.642 | 1.481 |
+---------------------+--------------+------+------+------------+-------------+
| cntrl_1_BUFGP | BUFGMUX4| No | 64 | 0.384 | 1.362 |
+---------------------+--------------+------+------+------------+-------------+
| cntrl_2_BUFGP | BUFGMUX3| No | 28 | 0.346 | 1.359 |
+---------------------+--------------+------+------+------------+-------------+
| cntrl_0_BUFGP | BUFGMUX1| No | 128 | 0.461 | 1.433 |
+---------------------+--------------+------+------+------------+-------------+
| m0/m0/m1/n4/res<8> | Local| | 87 | 1.309 | 4.730 |
+---------------------+--------------+------+------+------------+-------------+
| m0/m0/m1/n4/res<5> | Local| | 86 | 1.126 | 4.484 |
+---------------------+--------------+------+------+------------+-------------+
| m0/m0/m1/n4/res<2> | Local| | 86 | 1.125 | 4.517 |
+---------------------+--------------+------+------+------------+-------------+
| m0/m0/m1/n4/res<12> | Local| | 103 | 1.570 | 5.103 |
+---------------------+--------------+------+------+------------+-------------+
| m0/m0/m1/n4/res<11> | Local| | 87 | 0.972 | 4.571 |
+---------------------+--------------+------+------+------------+-------------+
| m0/m0/m1/n4/res<7> | Local| | 86 | 1.037 | 4.569 |
+---------------------+--------------+------+------+------------+-------------+
| m0/m0/m1/n4/res<1> | Local| | 86 | 1.128 | 4.392 |
+---------------------+--------------+------+------+------------+-------------+
| m0/m0/m1/n4/res<3> | Local| | 103 | 1.106 | 4.839 |
+---------------------+--------------+------+------+------------+-------------+
| m0/m0/m1/n4/res<0> | Local| | 86 | 0.880 | 4.548 |
+---------------------+--------------+------+------+------------+-------------+
| m0/m0/m1/n4/res<10> | Local| | 86 | 1.251 | 4.779 |
+---------------------+--------------+------+------+------------+-------------+
| m0/m0/m1/n4/res<9> | Local| | 86 | 0.958 | 4.496 |
+---------------------+--------------+------+------+------------+-------------+
| m0/m0/m1/n4/res<4> | Local| | 102 | 0.953 | 4.570 |
+---------------------+--------------+------+------+------------+-------------+
| m0/m0/m1/n4/res<6> | Local| | 86 | 0.753 | 4.552 |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

The Delay Summary Report

The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

The AVERAGE CONNECTION DELAY for this design is: 1.270

The MAXIMUM PIN DELAY IS: 19.610
The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 8.483

Listing Pin Delays by value: (nsec)

d < 4.00 < d < 8.00 < d < 12.00 < d < 16.00 < d < 20.00 d >= 20.00
--------- --------- --------- --------- --------- ---------
19566 1007 172 57 18 0
-----------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net m0/ | SETUP | N/A| 4.332ns| N/A|
0
m0/m1/n4/res<14> | HOLD | 0.623ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net m0/ | SETUP | N/A| 5.284ns| N/A|
0
m0/m1/n4/res<8> | HOLD | 0.015ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net m0/ | SETUP | N/A| 4.959ns| N/A|
0
m0/m1/n4/res<5> | HOLD | 0.012ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net m0/ | SETUP | N/A| 5.028ns| N/A|
0
m0/m1/n4/res<2> | HOLD | 0.000ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net m0/ | SETUP | N/A| 5.313ns| N/A|
0
m0/m1/n4/res<12> | HOLD | 0.045ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net m0/ | SETUP | N/A| 5.246ns| N/A|
0
m0/m1/n4/res<11> | HOLD | 0.013ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net m0/ | SETUP | N/A| 5.118ns| N/A|
0
m0/m1/n4/res<7> | HOLD | 0.018ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net m0/ | SETUP | N/A| 4.431ns| N/A|
0
m0/m1/n4/res<13> | HOLD | 0.789ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net m0/ | SETUP | N/A| 4.467ns| N/A|
0
m0/m1/n4/res<15> | HOLD | 0.642ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net m0/ | SETUP | N/A| 5.113ns| N/A|
0
m0/m1/n4/res<1> | HOLD | 0.001ns| | 0| 0
------------------------------------------------------------------------------------------------------
 Autotimespec constraint for clock net m0/ | SETUP | N/A| 4.988ns| N/A|
0
m0/m1/n4/res<3> | HOLD | 0.034ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net m0/ | SETUP | N/A| 4.911ns| N/A|
0
m0/m1/n4/res<0> | HOLD | 0.011ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net m0/ | SETUP | N/A| 5.449ns| N/A|
0
m0/m1/n4/res<10> | HOLD | 0.007ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net m0/ | SETUP | N/A| 5.108ns| N/A|
0
m0/m1/n4/res<9> | HOLD | 0.000ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net m0/ | SETUP | N/A| 4.932ns| N/A|
0
m0/m1/n4/res<4> | HOLD | 0.019ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net m0/ | SETUP | N/A| 5.010ns| N/A|
0
m0/m1/n4/res<6> | HOLD | 0.011ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 1.835ns| N/A|
0
_BUFGP | HOLD | 0.744ns| | 0| 0
------------------------------------------------------------------------------------------------------

All constraints were met.

INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
constraint does not cover any paths or that it has no requested value.
Device utilization summary:
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