Hierarchy

1.
2.
3.
4.

Packages
Top Level Modules
Nested Modules
Extern Modules

Introduction - Packages

In Verilog 2001 and 1995, there was no way to share

common code (task and function) across modules without
using `include compiler directive. Packages provide ways
to have common code to be shared across multiple
modules. SystemVerilog provides package support to help
share following

parameters
data
type
task
function
sequence
property

Rules :
Items within packages cannot have
hierarchical references.
Packages can not contain any assign
statement.
Variable declaration assignments within the
package shall occur before any initial,
always, always_comb, always_latch, or
always_ff blocks

Accessing data,functions or
types in packages
By class scope resolution operator ::
By import statement : The import statement
provides direct visibility of identifiers within
packages.

Example :
package definesPkg;
typedef enum {FALSE, TRUE} bool;
typedef struct {

bit [7:0] addr;

bit [7:0] data;
bit wr;
} mem_s;

task msg_info (string msg);

$display ("@%0dns %s INFO : %s",
$time,msgName,msg);

endtask
endpackage

`include "definesPkg.sv
import definesPkg::bool
import definesPkg::* // all

module simple_package();
bool value = definesPkg::FALSE;
initial begin
msgPkg::msg_info("Testing Packages");
#10 msgPkg::msg_info("Testing Packages");
if (value ! = definesPkg::TRUE)
#10 msgPkg::msg_fatal("Value is FALSE");

End

endmodule

Top level module

The name $root is added to unambiguously refer to a
top-level instance or to an instance path starting from
the root of the instantiation tree. $root is the root of
the instantiation tree.

Module child ()
task print();
$display(in child module);
endtask
initial begin
$root.top.U.U.print();
end
endmodule

Module parent();
task print();
$display(in parent module);
endtask
child u();
initial begin
$root.top.u2.print();
$root.top.u.print();
end
endmodule

Module top();
child u2();
parent u();
task print();
$display(in top);
endtask
endmodule

Nested Modules
In Verilog 2001 and 1995, module declaration
inside another module is not allowed, only
modules can be instanciated. But in
SystemVerilog, module declaration can be nested
The outer name space is visible to the inner
module so that any name declared there can be
used, unless hidden by a local name, provided the
module is declared and instantiated in the same
scope.
One purpose of nesting modules is to show the
logical partitioning of a module without using
ports.

Module nested_module();
Module counter(input clk,reset,enable,
output logic [3:0]data);
always@(posedge clk)
if(reset)
data <= 0;
else if(enable)
data <= data + 1;
Endmodule
Logic clk = 0;
Always #1 clk = ~clk;
Logic enable,reset;
Wire [3:0] data;
Counter c1(clk,reset,enable,data);
Initial begin
$monitor($time,reset,enable,data);
#10 reset <= 0;
#1 enable <= 1;
#10 enable <= 0;
end
endmodule

@0ns reset 1 enable x data xxxx

@1ns reset 1 enable x data 0000
@10ns reset 0 enable x data 0000
@11ns reset 0 enable 1 data 0000
@13ns reset 0 enable 1 data 0001
@15ns reset 0 enable 1 data 0010
@17ns reset 0 enable 1 data 0011
@19ns reset 0 enable 1 data 0100
@21ns reset 0 enable 0 data 0101

Extern module
To support separate compilation, extern
declarations of a module can be used to
declare the ports on a module without
defining the module itself.
An extern module declaration consists of
the keyword externfollowed by the module
name and the list of ports for the module

Extern module counter(input clk,reset,enable,ouput logic [3:0]data);

module extern_module();
logic clk = 0;
always #1 clk = ~clk;
logic enable,reset;
logic [3:0] data;
counter U(clk,reset,enable,data);
initial begin
$monitor($time,clk,reset,enable,data);
reset <= 1;
#10 reset <= 0;
#1 enable <= 1;
#10 enable <= 0;
#4 $finish;
end
endmodule
module counter (input clk,reset,enable,output logic [3:0] data);
always@(posedge clk) begin
if(reset)
data <= 0;
else
data <= data +1;
end
endmodule

@0ns reset 1 enable x data xxxx

@1ns reset 1 enable x data 0000
@10ns reset 0 enable x data 0000
@11ns reset 0 enable 1 data 0000
@13ns reset 0 enable 1 data 0001
@15ns reset 0 enable 1 data 0010
@17ns reset 0 enable 1 data 0011
@19ns reset 0 enable 1 data 0100
@21ns reset 0 enable 0 data 0101

InFo:
System verilog package globals instead of
`include
There are 2 files
globals2.svh (our include file)
example.sv (the main module)

Globals2.svh
const int I_PORTS_NUM2 = 1;
const real R_CONSTX2 = 1.66;
typedef enum {
E_MODE_X2 = 0,
E_MODE_Y2 = 1,
E_MODE_Z2 = 2
} e_modes2;

Example.sv

package globals;
const int I_PORTS_NUM = 0;
const real R_CONSTX = 1.33;
typedef enum {
E_MODE_X = 0,
E_MODE_Y = 1,
E_MODE_Z = 2
} e_modes;
endpackage // globals

module x;
`include "globals2.svh"
initial begin
$display("I_PORTS_NUM : %h", globals::I_PORTS_NUM);
$display("R_CONSTX : %f", globals::R_CONSTX);
$display("E_MODE_X : %h", globals::E_MODE_X);
$display("E_MODE_Y : %h", globals::E_MODE_Y);
$display("E_MODE_Z : %h", globals::E_MODE_Z);
$display("--");
$display("I_PORTS_NUM2: %h", I_PORTS_NUM2);
$display("R_CONSTX2 : %f", R_CONSTX2);
$display("E_MODE_X2 : %h", E_MODE_X2);
$display("E_MODE_Y2 : %h", E_MODE_Y2);
$display("E_MODE_Z2 : %h", E_MODE_Z2);
end
endmodule // x

#
#
#
#
#
#
#
#
#
#
#

I_PORTS_NUM : 00000000
R_CONSTX : 1.330000
E_MODE_X : 00000000
E_MODE_Y : 00000001
E_MODE_Z : 00000002
-I_PORTS_NUM2: 00000001
R_CONSTX2 : 1.660000
E_MODE_X2 : 00000000
E_MODE_Y2 : 00000001
E_MODE_Z2 : 00000002

Conclusion
We create a package called"globals"which has constants
defined in it - the same ones with a slightly different name
than in globals2.svh. Then, we define a module"x"and
have$displaystatements to show how to use those
variables the package way and the`includeway.
You have a choice to use the scope of
the"globals::"package, which I think is very nice for things
like constants - you get to know where the constant came
from. Or, you could choose to import everything"import
globals::*"and have those variables in your name space.
Or lastly, you could choose to only import certain
constants"import globals::I_PORTS_NUM". The choice is up
to you. But, youdohave a choice and some of those
possibilities might lead to easier code to reuse or read.

Quiz

What is $root?
Ans:$root refers to the top level instance in
SystemVerilog
1.packageABC;
2.$root.A;// top level instance A
3.$root.A.B.C;// item C within instance B
within top level instance A

What is the use of package?

In Verilog declaration of data/task/function within
modules are specific to the module only. They can't be
shared between two modules. Agreed, we can achieve
the same by including the files, which is known to be
not a great solution.
The package construct of SystemVerilog aims in
solving the above issue. It allows having global
data/task/function declaration which can be used
across modules. It can contain
module/class/function/task/constraints/covergroup
and many more declarations

Thank You