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DRV8305
SLVSCX2A AUGUST 2015 REVISED SEPTEMBER 2015
DRV8305 Three Phase Gate Driver With Current Shunt Amplifiers and Voltage Regulator
1 Features
3 Description
PACKAGE
2 Applications
DRV8305
HTQFP (48)
(1)
7.00 mm 7.00 mm
Simplified Schematic
4.4 to 45 V
MCU
PWM
SPI
Shunt Amps
nFAULT
DRV8305
3-Phase
Brushless
Pre-Driver
Gate Drive
LDO
Sense
N-Channel
MOSFETs
EN_GATE
Shunt Amps
Protection
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8305
SLVSCX2A AUGUST 2015 REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
1
1
1
2
3
5
10 Layout................................................................... 45
10.1 Layout Guidelines ................................................. 45
10.2 Layout Example .................................................... 45
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
46
46
46
46
4 Revision History
Changes from Original (August 2015) to Revision A
Page
Change the Electrical Characteristics Condition From: TJ = 40C to 150C To: TA = 25C ............................................... 7
Changed Table 18 - Bit 10 , 9, and 8 DEFAULT From: = 0x1 To: 0x0 ............................................................................... 37
DRV8305
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37
38
39
40
41
42
43
44
45
46
36
35
34
33
32
1
2 PAD
POWER
3
(GND)
6
7
31
30
29
24
23
22
21
GHA
SHA
SLA
GLA
GLB
SLB
SHB
GHB
GHC
SHC
SLC
GLC
PWRGD
GND
AVDD
SO1
SO2
SO3
SN3
SP3
SN2
SP2
SN1
SP1
20
25
19
12
18
26
16
11
15
27
14
28
13
9
10
17
EN_GATE
INHA
INLA
INHB
INLB
INHC
INLC
nFAULT
nSCS
SDI
SDO
SCLK
47
48
VREG
WAKE
DVDD
GND
VDRAIN
CP1H
CP1L
PVDD
CP2L
CP2H
VCPH
VCP_LSD
PHP Package
48-Pin HTQFP
Top View
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
EN_GATE
Enable gate
INHA
INLA
INHB
INLB
INHC
INLC
nFAULT
OD
Fault indicator
nSCS
10
SDI
SPI input
11
SDO
SPI output
12
SCLK
SPI clock
13
PWRGD
Power Good
OD
DRV8305
SLVSCX2A AUGUST 2015 REVISED SEPTEMBER 2015
www.ti.com
NAME
I/O
DESCRIPTION
14
45
GND
Device ground
15
AVDD
Analog regulator
5.0 V analog internal supply regulator; bypass to GND with a 6.3V, 1-F ceramic capacitor
16
SO1
17
SO2
18
SO3
19
SN3
20
SP3
21
SN2
22
SP2
23
SN1
24
SP1
25
GLC
26
SLC
27
SHC
28
GHC
29
GHB
30
SHB
31
SLB
32
GLB
33
GLA
34
SLA
35
SHA
36
GHA
37
VCP_LSD
38
VCPH
39
CP2H
40
CP2L
PPAD
External Components
COMPONENT
PIN 1
PIN 2
RECOMMENDED
CPVDD
PVDD
GND
CAVDD
AVDD
GND
CDVDD
DVDD
GND
CVCPH
VCPH
PVDD
CVCP_LSD
VCP_LSD
GND
CCP1
CP1H
CP1L
CCP2
CP2H
CP2L
CVREG
VREG
GND
RVDRAIN
VDRAIN
PVDD
RnFAULT
(1)
nFAULT
VCC
(1)
VCC is not a pin on the DRV8305, but a VCC supply voltage pullup is required for open-drain output nFAULT
DRV8305
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range referenced with respect to GND (unless otherwise noted)
Power supply voltage (PVDD)
(1)
MIN
MAX
UNIT
0.3
45
V/s
0.3
PVDD + 12
57
12
High side gate driver source pin voltage (SHA, SHB, SHC)
45
0.3
15
0.3
45
Max source current (VDRAIN) limit current with external series resistor
20
V
mA
mA
10
10
Control pin voltage range (INHA, INLA, INHB, INLB, INHC, INLC, EN_GATE, SCLK,
SDI, SCS, SDO, nFAULT, PWRGD)
0.3
5.5
mA
0.3
45
mA
0.3
5.5
100
40
125
40
150
55
150
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Electrostatic
discharge
(1)
UNIT
2000
(2)
500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
DRV8305
SLVSCX2A AUGUST 2015 REVISED SEPTEMBER 2015
www.ti.com
MAX
UNIT
V
VPVDD
4.4
45
(1)
VPVDD
4.3
45
(2)
VPVDDRAMP
Power supply voltage ramp rate (PVDD = 0 to 20 V rising <3-mA pin sink
current)
V/s
VPVDD-SH_X
4.5
ISRC_VCPH
10
mA
CO_OPA
60
pF
InFAULT
Fgate
IGATE
Total average gate driver current (HS + LS) charge pump limited
TA
(1)
(2)
-40
mA
200
kHz
30
mA
125
(1)
PHP (HTQFP)
UNIT
48 PINS
RJA
26.6
C/W
RJC(top)
12.9
C/W
RJB
7.6
C/W
JT
0.3
C/W
JB
7.5
C/W
RJC(bot)
0.6
C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
DRV8305
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TEST CONDITIONS
MIN
TYP
MAX
UNIT
45
4.3
45
VPVDD
IPVDD_Operating
15
IPVDD_Standby
mA
IPVDD_Sleep
60
175
5.15
VAVDD
VDVDD
PVDD = 5.3 to 45 V
4.85
PVDD
0.22
PVDD
V
mA
3.3
VVREG
VLineReg
5.3 V VIN 12 V; IO = 1 mA
VLoadReg
Load regulation
VOUT/IOUT
100 A IOUT 50 mA
Vdo
Dropout voltage
VSET
(0.03
VSET)
VSET
PVDD 0.4
V
VSET
(0.03
VSET)
VSET +
(0.03
VSET)
PVDD
VSET
VSET +
(0.03
VSET)
10
30
mV
30
mV
0.05
0.1
0.2
0.4
LOGIC-LEVEL INPUTS (INHA, INLA, INHB, INLB, INHC, INLC, EN_GATE, SCLK, nSCS)
VIL
VIH
RPD
0.8
2
To GND
5
100
V
V
k
VOH
IOH
IO = 5 mA
0.5
2.4
VO = 3.3 V
1.1
1.41
VIH_WAKE
1.42
1.75
VGHS
7.2
7.2
10
10.5
DRV8305
SLVSCX2A AUGUST 2015 REVISED SEPTEMBER 2015
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VGLS
TEST CONDITIONS
MIN
TYP
MAX
10
10.5
10.5
UNIT
tDRIVE
220
440
880
1660
ns
IDRIVEP_HS
IDRIVEP_HS = 0000
0.01
IDRIVEP_HS = 0001
0.02
IDRIVEP_HS = 0010
0.03
IDRIVEP_HS = 0011
0.04
IDRIVEP_HS = 0100
0.05
IDRIVEP_HS = 0101
0.06
IDRIVEP_HS = 0110
0.07
IDRIVEP_HS = 0111
0.125
IDRIVEP_HS = 1000
0.25
IDRIVEP_HS = 1001
0.5
IDRIVEP_HS = 1010
0.75
IDRIVEP_HS = 1011
IDRIVEN_HS
0.05
IDRIVEN_HS = 0000
0.02
IDRIVEN_HS = 0001
0.03
IDRIVEN_HS = 0010
0.04
IDRIVEN_HS = 0011
0.05
IDRIVEN_HS = 0100
0.06
IDRIVEN_HS = 0101
0.07
IDRIVEN_HS = 0110
0.08
IDRIVEN_HS = 0111
0.25
IDRIVEN_HS = 1000
0.5
IDRIVEN_HS = 1001
0.75
IDRIVEN_HS = 1010
IDRIVEN_HS = 1011
1.25
0.06
DRV8305
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TEST CONDITIONS
MIN
TYP
MAX
UNIT
IDRIVEP_LS
IDRIVEP_HS = 0000
0.01
IDRIVEP_HS = 0001
0.02
IDRIVEP_HS = 0010
0.03
IDRIVEP_HS = 0011
0.04
IDRIVEP_HS = 0100
0.05
IDRIVEP_HS = 0101
0.06
IDRIVEP_HS = 0110
0.07
IDRIVEP_HS = 0111
0.125
IDRIVEP_HS = 1000
0.25
IDRIVEP_HS = 1001
0.5
IDRIVEP_HS = 1010
0.75
IDRIVEP_HS = 1011
0.05
IDRIVEN_LS
IDRIVEN_HS = 0000
0.02
IDRIVEN_HS = 0001
0.03
IDRIVEN_HS = 0010
0.04
IDRIVEN_HS = 0011
0.05
IDRIVEN_HS = 0100
0.06
IDRIVEN_HS = 0101
0.07
IDRIVEN_HS = 0110
0.08
IDRIVEN_HS = 0111
0.25
IDRIVEN_HS = 1000
0.5
IDRIVEN_HS = 1001
0.75
IDRIVEN_HS = 1010
IDRIVEN_HS = 1011
1.25
0.06
RSTANDBY_PD
IOPERATING_PD
2000
750
50
mA
mA
50
IPULLDOWN
1.25
DRV8305
SLVSCX2A AUGUST 2015 REVISED SEPTEMBER 2015
www.ti.com
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GATE TIMING
tpd_lf-O
200
ns
tpd_lr-O
200
ns
td_min
280
ns
tdtp
DEAD_TIME = 000
35
DEAD_TIME = 001
52
DEAD_TIME = 010
88
DEAD_TIME = 011
440
DEAD_TIME = 100
880
DEAD_TIME = 101
1760
DEAD_TIME = 110
3520
DEAD_TIME = 111
5280
ns
tPD_MATCH
50
ns
tDT_MATCH
50
ns
GCSA
GERR
tSETTLING
GAIN_CSx = 00
10
GAIN_CSx = 01
20
GAIN_CSx = 10
40
GAIN_CSx = 11
80
3%
V/V
3%
300
600
1.2
2.4
ns
VIOS
DC input offset
VVREF_ERR
VDRIFTOS
IBIAS
IOFFSET
VIN_COM
0.15
0.15
VIN_DIFF
-0.48
0.48
CMRR
2%
V/C
100
60
80
60
80
A
A
dB
150
VSWING
0.3
VSLEW
GCSA = 10; RL = 0 ; CL = 60 pF
5.2
20 kHz; GCSA = 10
mV
2%
10
PSRR
10
dB
90
4.7
10
V
V/s
DRV8305
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TEST CONDITIONS
IVO
UGB
GCSA = 10
MIN
TYP
MAX
UNIT
20
mA
MHz
VOLTAGE PROTECTION
VAVDD_UVLO
Relative to GND
3.3
3.5
VREG_UV_LEVEL = 00
VSET-10%
VREG_UV_LEVEL = 01
VSET-20%
VREG_UV_LEVEL = 10
VSET-30%
VREG_UV_LEVEL = 11
VSET-30%
VVREG_UV
VVREG_UV_DGL
VPVDD_UVFL
Undervoltage protection
Warning, PVDD
VPVDD_UVLO1
Undervoltage protection
lockout, PVDD
PVDD falling
4.1
PVDD rising
4.3
VPVDD_UVLO2
Undervoltage protection
Fault, PVDD
PVDD falling
4.2
4.4
PVDD rising
4.4
4.6
VPVDD_OVFL
Overvoltage protection
Warning, PVDD
PVDD falling
33.5
36
PVDD rising
32.5
35
VVCPH_UVFL
VVCPH_UVLO
VVCP_LSD_UVLO
1.5
PVDD falling
7.7
8.1
PVDD rising
7.9
8.3
Relative to PVDD
s
V
V
V
V
V
4.5
4.9
4.2
4.6
Relative to PVDD
6.4
7.5
VVCPH_OVLO
Relative to PVDD
14
18
VVCPH_OVLO_ABS
Relative to GND
60
TEMPERATURE PROTECTION
OTW_CLR
140
OTW_SET/
OTSD_CLR
155
OTSD_SET
175
TEMPFLAG1
105
TEMPFLAG2
125
TEMPFLAG3
135
TEMPFLAG4
175
(1)
11
DRV8305
SLVSCX2A AUGUST 2015 REVISED SEPTEMBER 2015
www.ti.com
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PROTECTION CONTROL
tpd,E-L
tpd,E-SD
24
VDS_TRIP
tVDS
tBLANK
12
Drain-source voltage
protection limit
VDS_LEVEL = 00000
0.06
VDS_LEVEL = 00001
0.068
VDS_LEVEL = 00010
0.076
VDS_LEVEL = 00011
0.086
VDS_LEVEL = 00100
0.097
VDS_LEVEL = 00101
0.109
VDS_LEVEL = 00110
0.123
VDS_LEVEL = 00111
0.138
VDS_LEVEL = 01000
0.155
VDS_LEVEL = 01001
0.175
VDS_LEVEL = 01010
0.197
VDS_LEVEL = 01011
0.222
VDS_LEVEL = 01100
0.25
VDS_LEVEL = 01101
0.282
VDS_LEVEL = 01110
0.317
VDS_LEVEL = 01111
0.358
VDS_LEVEL = 10000
0.403
VDS_LEVEL = 10001
0.454
VDS_LEVEL = 10010
0.511
VDS_LEVEL = 10011
0.576
VDS_LEVEL = 10100
0.648
VDS_LEVEL = 10101
0.73
VDS_LEVEL = 10110
0.822
VDS_LEVEL = 10111
0.926
VDS_LEVEL = 11000
1.043
VDS_LEVEL = 11001
1.175
VDS_LEVEL = 11010
1.324
VDS_LEVEL = 11011
1.491
VDS_LEVEL = 11100
1.679
VDS_LEVEL = 11101
1.892
VDS_LEVEL = 11110
2.131
VDS_LEVEL = 11111
2.131
TVDS = 00
TVDS = 01
1.75
TVDS = 10
3.5
TVDS = 11
TBLANK = 00
TBLANK = 01
1.75
TBLANK = 10
3.5
TBLANK = 11
DRV8305
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TEST CONDITIONS
MIN
TYP
MAX
UNIT
56
Fixed voltage
tCLK
tCLKH
NOM
MAX
10
UNIT
ms
100
ns
40
ns
tCLKL
40
ns
tSU_SDI
20
ns
tHD_SDI
30
tD_SDO
tHD_SDO
40
ns
tSU_SCS
50
ns
tHD_SCS
50
ns
tHI_SCS
tACC
10
ns
tDIS
10
ns
ns
CL = 20 pF
20
400
ns
ns
13
DRV8305
SLVSCX2A AUGUST 2015 REVISED SEPTEMBER 2015
www.ti.com
30
5.9
25
T A = 40C
S u p p ly C u r r e n t ( m A )
S u p p ly C u r r e n t ( m A )
5.8
T A = 25C
5.7
T A = 125C
5.6
5.5
5.4
20
15
10
5.3
T A = 40C
T A = 25C
5.2
T A = 125C
5.1
10
20
30
40
50
PVDD (V)
10
20
30
40
PVDD (V)
D001
50
D002
200
12
180
10
140
120
V C P H (V )
S u p p ly C u r r e n t ( m A )
160
100
80
60
40
T A = 40C
T A = 40C
T A = 25C
20
T A = 25C
T A = 125C
T A = 125C
10
20
30
PVDD (V)
40
50
D003
10
20
30
PVDD (V)
40
50
D004
DRV8305
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7 Detailed Description
7.1 Overview
The DRV8305 is a 4.4-V to 45-V gate driver IC for three-phase motor driver applications. This device reduces
external component count by integrating three half-bridge drivers, three current shunt amplifiers, and a LDO. The
DRV8305 provides overcurrent, overtemperature, and undervoltage protection. Fault conditions are indicated by
the nFAULT pin and specific fault indication can be read back from the SPI registers.
Adjustable dead time control and peak gate drive current allows for finely tuning the switching of the external
MOSFETs. Internal hand-shaking is used to prevent FET shoot through.
VDS sensing of the external MOSFETs allows for the DRV8305 to detect overcurrent conditions and respond
appropriately. Individual MOSFET overcurrent conditions are reported through the SPI status registers.
There are three versions of DRV8305 with separate part numbers:
DRV8305N VREG pin is used as input that supplies the reference for the CSA and SPI.
DRV83053 VREG is a 3.3-V LDO output pin.
DRV83055 VREG is a 5.0-V LDO output pin.
15
DRV8305
SLVSCX2A AUGUST 2015 REVISED SEPTEMBER 2015
www.ti.com
DVDD
AVDD
CP1L
CP1H
CP2L
CP2H
VCP_LSD
AVDD
DVDD
VCP_LSD
VCPH
DVDD
LDO
AVDD
LDO
Low Side
Gate Drive
LDO
VCPH
PVDD
VREG
WAKE
PVDD
VREG
VDRAIN
VREG
LDO
VDRAIN
PWRGD
VDRAIN
VCPH
GHA
+
HS
VDS
-
SHA
EN_GATE
VCP_LSD
GLA
+
INHA
LS
VDS
-
SLA
INLA
Phase A Pre-Driver
INHB
INLB
VDRAIN
Digital
Inputs
and
Outputs
PVDD
VCPH
GHB
+
HS
VDS
-
SHB
Core Logic
INHC
VCP_LSD
GLB
+
INLC
LS
VDS
Control
SLB
nFAULT
Configuration
Phase B Pre-Driver
VDRAIN
PVDD
VCPH
GHC
Timing
HS
VDS
SCLK
SHC
Protection
VCP_LSD
nSCS
GLC
SPI
LS
VDS
SDI
SDO
SLC
Thermal
Sensor
Voltage
Monitoring
SO1
Phase C Pre-Driver
VREG
Current
Sense
Amplifier 1
Ref/k
VREG
VREG
Ref/k
GND
16
Current
Sense
Amplifier 2
Ref/k
GND
SP1
SN2
AVDD
SO2
SO3
SN1
AVDD
SP2
SN3
AVDD
Current
Sense
Amplifier 3
SP3
PowerPAD
DRV8305
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INHX
INLX
GHX
GLX
1
1
Three independent high-side PWM inputs (low-side complimentary PWMs generated internally).
In this mode all activity on INLA, INLB and INLC is ignored.
Table 2. 3-PWM Truth Table
INHX
INLX
GHX
GLX
L
One single PWM that uses internally stored 6-step block commutation tables. In this mode of operation,
DRV8305 can be operated using a single PWM sourced from a low cost microcontroller. The PWM is applied
on pin PWM_IN (INHA) from the microcontroller along with three GPIO pins PHC_0 (INLA), PHC_1 (INHB),
PHC_2 (INLB) that serve to set the bits of a three bit register. The PWM may be operated from 0-100% duty
cycle. The three bit register is used to select the state of each of the phases for a total of eight states
including an align and stop state. The 1-PWM mode tables will use all the applicable settings from the control
registers as set up by the user.
An additional and optional GPIO (INHC) can be used to facilitate the insertion of dwell states or phase current
overlap states between the six commutation steps. This may be used to reduce acoustic noise and improve
motion through the reduction of abrupt current direction changes when switching between states. INHC must
be high when the states are changed and the dwell state will exist until INHC is taken low. If the dwell states
are not being used, the INHC pin can be simply tied low.
In this mode all activity on INLC is always ignored.
The commutation tables ( Table 3 and Table 4) may be selected through the appropriate SPI register.
17
DRV8305
SLVSCX2A AUGUST 2015 REVISED SEPTEMBER 2015
www.ti.com
AH
AL
BH
BL
CH
CL
AB
0110
PWM
!PWM
LOW
HIGH
LOW
LOW
AB_CB
0101
PWM
!PWM
LOW
HIGH
PWM
!PWM
CB
0100
LOW
LOW
LOW
HIGH
PWM
!PWM
CB_CA
1101
LOW
HIGH
LOW
HIGH
PWM
!PWM
CA
1100
LOW
HIGH
LOW
LOW
PWM
!PWM
CA_BA
1001
LOW
HIGH
PWM
!PWM
PWM
!PWM
BA
1000
LOW
HIGH
PWM
!PWM
LOW
LOW
BA_BC
1011
LOW
HIGH
PWM
!PWM
LOW
HIGH
BC
1010
LOW
LOW
PWM
!PWM
LOW
HIGH
BC_AC
0011
PWM
!PWM
PWM
!PWM
LOW
HIGH
AC
0010
PWM
!PWM
LOW
LOW
LOW
HIGH
AC_AB
0111
PWM
!PWM
LOW
HIGH
LOW
HIGH
Align
1110
PWM
!PWM
LOW
HIGH
LOW
HIGH
Stop
0000
LOW
LOW
LOW
LOW
LOW
LOW
CH
CL
AH
AL
BH
BL
AB
0110
PWM
LOW
LOW
HIGH
LOW
LOW
AB_CB
0101
PWM
LOW
LOW
HIGH
PWM
LOW
CB
0100
LOW
LOW
LOW
HIGH
PWM
LOW
CB_CA
1101
LOW
HIGH
LOW
HIGH
PWM
LOW
CA
1100
LOW
HIGH
LOW
LOW
PWM
LOW
CA_BA
1001
LOW
HIGH
PWM
LOW
PWM
LOW
BA
1000
LOW
HIGH
PWM
LOW
LOW
LOW
BA_BC
1011
LOW
HIGH
PWM
LOW
LOW
HIGH
BC
1010
LOW
LOW
PWM
LOW
LOW
HIGH
BC_AC
0011
PWM
LOW
PWM
LOW
LOW
HIGH
AC
0010
PWM
LOW
LOW
LOW
LOW
HIGH
AC_AB
0111
PWM
LOW
LOW
HIGH
LOW
HIGH
Align
1110
PWM
LOW
LOW
HIGH
LOW
HIGH
Stop
0000
LOW
LOW
LOW
LOW
LOW
LOW
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The gate driver is implemented as constant current sources for up to 80 mA (sink)/70 mA (source) currents in
order to maintain the accuracy required for precise slew rate control. Beyond that, resistors are switched to
create the desired settings up to 1.25 A (sink)/1 A (source).
7.3.5 IDRIVE/TDRIVE
The DRV8305 gate driver has an integrated state machine (TDRIVE/IDRIVE scheme) to protect against high
current events on the outputs (shorts or inadvertent clamp activation) and also dV/dt turn on due to switching on
the phase nodes.
When changing the state of the gate driver, the peak current (source or sink, IDRIVE) is applied for a fixed period
of time (TDRIVE) until the gate capacitances are charged or discharged completely. After this time has expired, a
fixed current source of IHOLD is used to hold the gate at the desired state (pulled up or pulled down).
INHX
GHX (V)
tDRIVEP
tDRIVEN
IDRIVEP
IHOLD
GHX (mA)
-IHOLD
-IPULLDOWN
-IPULLDOWN
IDRIVEN
tDEAD
`
IDRIVEP
GLX (mA)
IHOLD
IHOLD
- IHOLD
-IPULLDOWN
IDRIVEN
tDRIVEN
tDRIVEP
GLX
INLX
Figure 7. TDRIVE/IDRIVE Waveforms
This fixed TDRIVE time ensures that under abnormal circumstances like a short on the FET gate, or the
inadvertent turning on of a FET VGS clamp, the high peak current through the DRV8305 gate drivers is limited to
the energy of the peak current during TDRIVE. Limiting this energy helps to prevent the gate driver from
damage.
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Select a TDRIVE time that is longer than the time needed to charge or discharge the gate capacitances. IDRIVE
and TDRIVE are selected based on the size of external FETs used and the desired rise and fall times. These
registers must be configured so that the FET gates are charged completely during TDRIVE. If IDRIVE and
TDRIVE are too low for a given FET, then the FET may not turn on completely. TI suggests to adjust these
values in-system with the required external FETs to determine the best possible setting for any application.
Note that TDRIVE will not increase the PWM time and will simply terminate if a PWM command is received while
it is active. A good starting point is to select a TDRIVE that is about 2 longer than the external FET switching
rise (turn ON) and fall (turn OFF) times.
The IDRIVE/TDRIVE state machine protects against dV/dt turn on of a FET due to switching of the phase nodes.
A strong pulldown current source of value IPULLDOWN is switched on between (GHX to SHX) or (GLX to SLX),
every time an opposing FET is commanded to turn on.
7.3.6 Slew Rate/Slope Control
Control of the FET VDS rise and fall times during the Miller region of the FET is one of the most important
parameters for optimizing emitted radiations and power. The rise and fall times also influence the energy and
duration of the diode recovery inductive spikes and also dV/dt turn on of the LS FET.
The ability of a driver to control the rise and fall times across the entire range of gate drive temperature, voltage,
and process variation is essential to design robust systems. The key control knob is the ability to turn on and turn
off the external FET with the least amount of variation.
The DRV8305 uses temperature compensated constant current sources up to 80-mA (sink) and 70-mA (source)
current. The current source architecture helps eliminate the temperature, process, and load-dependent variation
associated with internal and external series limiting resistors.
For higher currents, internal series resistors are used to minimize the power losses associated with mirroring
such large currents.
The 12 settings that are available on the DRV8305 allow the user to optimize the system using only SPI
commands. This flexibility allows the system designer to tune the performance of the driver for different operating
conditions through software alone.
The slew rate settings may be set separately for source and sink values and can also be set separately for the
high-side FETs (the high sides of all three phases share the same setting) and the low-side FETs (the low sides
of all three phases share the same settings)
7.3.7 Current Shunt Amplifiers
The DRV8305 includes three high performance low-side current shunt amplifiers for accurate current
measurement. The current amplifiers provide output bias up to 2.5 V to support bidirectional current sensing.
Current shunt amplifier has following features:
Each of the three current sense amplifiers can be programmed and calibrated independently.
The independent current shunt amplifiers may be used either for sensing current through individual phase
shunt resistors or the total current delivered to the motor through a single shunt resistor.
Programmable gain: four gain settings through SPI command
Internally or externally provided reference voltage to set output bias for amplifiers. Reference voltage is
internally sourced from DRV8305 voltage regulator VREG, if also used to power microcontroller. It can
alternatively be applied externally on the VREG pin.
Programmable output bias scaling. The scaling factor k can be programmed through SPI to be equal to, half
or a fourth of the reference voltage.
Programmable blanking time (delay) of the amplifier outputs. The blanking time is implemented from any
rising or falling edge (any of the outputs) of the internal gate driver gate signals. The blanking time is applied
to all three current sense amplifiers equally. In case the current sense amplifiers are already being blanked
when another gate driver rising or falling edge is seen, the blanking interval will be restarted at the edge.
Note that the blanking time options do not include delay from internal amplifier loading or delays from the
trace or component loads on the amplifier output. The programmable blanking time may be overridden to
have no delay (default value).
Minimize DC offset and drift through temperature with DC calibrating through SPI command. When DC
calibration is enabled, device will short input of current shunt amplifier and disconnect the load. DC calibrating
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can be done at anytime, even when the FET is switching because the load is disconnected. For best result,
perform the DC calibrating during switching off period when no load is present to reduce the potential noise
impact to the amplifier.
The output of current shunt amplifier can be calculated as:
VVREF
VO
G u SNX SPX
k
where
400
DC _ CAL(SPI)
SN
200 kO
S3
100 kO
S2
50 kO
S1
5 kO
AVDD
100 O
S5
SO
5 kO
+
SP
50 kO
S1
100 kO
S2
200 kO
S3
400 kO
S4
DC _ CAL(SPI)
VREF/k
VREF
AVDD
k = 2, 4
+
Figure 8. Current Shunt Amplifier Simplified Block Diagram
7.3.8 Internal Regulators (DVDD and AVDD)
The DRV8305 has two internal regulators, DVDD and AVDD, that power internal circuits. These regulators
cannot be used to drive external loads and may not be supplied externally.
DVDD is the voltage regulator for the internal logic circuits and is maintained at a value of about 3.3 V through
the entire operating range of the device. DVDD is derived from the PVDD supply.
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AVDD is the voltage regulator that provides the voltage rail for the internal analog circuit blocks including the
current sense amplifiers. AVDD is derived from the PVDD voltage supply.
Because the allowed operating range of the device permits operation below the nominal value of AVDD, this
regulator operates in two regimes: namely a linear regulating regime and a dropout region. In the dropout region,
the AVDD will simply track the PVDD voltage minus a voltage drop.
If the device is expected to operate within the dropout region, take care while selecting current sense amplifier
components and settings to accommodate this reduced voltage rail.
7.3.9 Voltage Regulator Output for Driving External Loads (VREG)
The DRV8305 integrates an LDO voltage regulator (VREG) that is dedicated for driving external loads like an
MCU directly. The two versions of the device provide different voltages: DRV83053 provides 3.3 V, DRV83055
provides 5.0 V. Because the user can supply microcontroller and other system power from the DRV8305, the
user does not need to add an external regulator IC for system power.
The DRV8305 voltage regulator is standalone, uncommitted, and is not used internally.
The DRV8305 voltage regulator also features a PWRGD pin to protect against brownouts on externally driven
devices. The PWRGD pin is often tied to a reset pin on a microcontroller to ensure that the microcontroller is
always reset when the voltage is outside of its recommended operation area.
When the voltage output of the LDO drops or exceeds the set threshold (programmable).
The PWRGD pin will go low for a period of 64 s.
After the 64-s period has expired, the LDO voltage will be checked and PWRGD will be held low until the
LDO voltage has recovered.
The voltage regulator also has undervoltage protection implemented for both the input voltage (PVDD) and
output voltage (VREG).
7.3.10 Protection Features
Fault / Warning Classes and Recovery summarizes the protection features, fault responses, and recovery
sequences.
7.3.10.1 Fault and Protection Handling
The DRV8305 handles fault (latched fault) and warnings (unlatched faults) separately. Both latched and
unlatched faults are reported in status registers and can be read through SPI.
A latched nFAULT pin indicates an error event has occurred that has caused part of the gate driver to shut
down and force outputs to a safe state (external FETs in high impedance).
A latched fault is indicated by the nFAULT pin going low (and staying low) and reporting the details of the
fault in the status registers (0x02 and 0x03). The appropriate recovery sequence must be performed in
order to reset the latched fault. In addition, the register (0x01) contains a single status bit if any latched
faults are detected.
The nFAULT pin will stay low until the appropriate recovery sequence is performed.
TI recommends to inspect the system and board when a latched nFAULT faults occurs.
An unlatched warning on nFAULT pin indicates that an event that requires a warning to be communicated has
occurred.
An unlatched fault is indicated by the nFAULT pin going low for a period of 64 s, reporting the warning
and then recovering back high for a period of 64 s before reporting any subsequent errors.
When a warning has been read by SPI through the warning register (0x01), that same warning will not be
reported through nFAULT again unless that warning or condition passes and then reoccurs.
However, the SPI registers will continue to report the latest status of the condition even after it has been
cleared by the read, that is, if the condition has cleared, then the warning will clear in the SPI registers.
Note that if the microprocessor does not read the warning, then the nFAULT pin will continue to toggle.
In case another warning or warnings are received during the 64-s period but after the warning register
has been read, then after the expiration of 64 s, the nFAULT pin will go high for another 64 s and then
report those warning or warnings by going low for another 64 s.
If a latched fault occurs during a period where nFAULT is low, then the nFAULT pin will stay low.
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Note that nFAULT is an open-drain signal and must be pulled up through an external resistor.
7.3.10.2 Shoothrough Protection
DRV8305 integrates analog and digital monitors to prevent shoot-through in the external FETs.
An Internal handshake through analog comparators is performed between high-side and low-side FETs
during switching transition.
A minimum dead time (digital) of 40 ns is always inserted after a successful handshake. This digital dead-time
is programmable and is in addition to the time taken for the handshake.
7.3.10.3 VDS Sensing External FET Protection and Reporting (OC Event)
To protect the external FETs from damage due to high currents, VDS sensing circuitry is implemented in the
DRV8305.
The VDS sensing is implemented for both the high-side and low-side MOSFET through these pins:
High-side MOSFET: VDS measured between VDRAIN and SHX pins
Low-side MOSFET: VDS measured between SHX and SLX pins
Based on RDS(on) of the power MOSFETs and the maximum allowed IDS, a voltage threshold can be calculated,
which when exceeded, triggers the VDS protection feature.
This voltage threshold level is programmable through SPI command and may be programmed during operation if
needed.
The VDS protection logic also has an adjustable blanking time and deglitch time to prevent false trips.
VDS blanking time (tBLANK): This time is inserted digitally and is programmable. The tBLANK time is a delay inserted
at each output after that particular output has been commanded to turn ON. During tBLANK time, the VDS
comparators are not being monitored in order to prevent false trips when the FETs first turn ON.
VDS deglitch time (tVDS): This time is inserted digitally and is programmable. The tVDS time is a delay inserted after
the VDS sensing comparators have tripped to when the protection logic is informed that a VDS event has
occurred.
Note that the dead time and blanking time are overlapping counters as shown in Figure 9
INx_x
Gx_x
1
2
3
tDead
Input Signal
Output Slew
Expiration of Blanking
tBLANK
1
tdeglitch
2
3
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The device integrates VGS clamps inside the gate driver that will turn on when the GHX voltage exceeds SHX
voltage by a value that could be damaging to the FETs. If the voltage continues to rise, in spite of the clamps
turning on, the TDRIVE architecture ensures that the energy through the clamps is limited. If the high VGS
voltage is due to an abnormal condition on the charge pump, the charge pump overvoltage fault will trip in order
to protect the FETs from damage.
7.3.11.6 Gate Driver Faults
The DRV8305 protects against abnormal short to battery or short to ground conditions on the gate driver outputs
that could result in an incorrect state of the gate driver outputs. The gate driver integrates VGS comparators that
check the status of the gate driver output against the commanded PWM signal to ensure that they match. This
comparison occurs shortly after the expiration of the TDRIVE time. If the comparison indicates a mismatch, a
gate driver fault is indicated.
7.3.11.7 Reverse Battery Protection
The VCPH pin on the DRV8305 is designed to be able to supply an external load of up to 10 mA. This feature
allows implementation of an external reverse battery protection scheme using a MOS and a BJT. The MOS gate
can be driven through VCP through a current limiting resistor to limit the current drawn from VCP. The current
limit resistor must be sized not to exceed the maximum external load on VCPH.
The VDRAIN pin (sense) may also be protected against negative transients on it by use of a current limiting
resistor. The current limit resistor must be sized not to exceed the maximum current load on the VDRAIN pin.
BATTERY
PVDD
VDRAIN
Figure 10. Typical Scheme for Reverse Battery Protection Using VCPH
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OUTPUTS
PD PULL
DOWN
O OPERATING
None
PD
SD
SD
SD
Latched
PD
SD
Warning
Warning
Warning
Latched
PD
SD
Latched
PD
SD
AVDD undervoltage
Latched
PD
SD
SD
Real time
OT warning (OTW)
Warning
OT shutdown (OTS)
Latched
PD
SD
CONDITION
CHARGE PUMP
AVDD / DVDD
O OPERATING O OPERATING
SD SHUTDOWN SD SHUTDOWN
VOLTAGE
REGULATOR
O OPERATING
SD SHUTDOWN
Latched
PD
Report only
Not reported
SNS OCP
Latched
PD
Latched
PD
SD
MCU watchdog
Latched +
PWRGD
PD
VREG_UV
Latched +
PWRGD
PD
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nFAULT
PWRGD
SPI REPORT
SPI REPORT
RECOVERY
Latched
Low
No action
Yes
Warning
No action
Yes
No action
Yes
Real time
No action
No action
Yes
Not reported
No action
No action
No
None
None
Latched +
PWRGD
Low
Yes
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SLEEP State
The SLEEP state is invoked by issuing a SLEEP command through SPI. After the SLEEP command is received,
the VREG and the gate driver safely power down internally after a programmable delay.
The DRV8305 can then only be enabled through the WAKE pin which is a high-voltage-tolerant input pin.
For the DRV8305 to be brought out of SLEEP, the WAKE pin must be at a voltage greater than 3 V. This allows
the WAKE to be driven, for example, directly by the battery through a switch, through the inhibit pin (INH) on
standard LIN interface or through standard digital logic. The WAKE pin will only react to a wake-up command if
PVDD > VPVDD_UVLO2.
After the DRV8305 is out of SLEEP mode, all activity on the WAKE pin is ignored.
SLEEP state erases the values in the SPI control registers. TI does not recommend to write through SPI in
SLEEP state.
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7.5 Programming
7.5.1 SPI Communication
7.5.1.1 SPI
SPI is used to set device configuration, operating parameters, and read out diagnostic information. The
DRV8305 SPI operates in slave mode.
The SPI input data (SDI) word consists of a 16-bit word with 11-bit data and 5-bit (MSB) command. The SPI
output data (SDO) word consists of 11-bit register data. (The first 5 bits (MSB) are to be ignored.)
A
Data is always shifted out on the rising edge of the clock in the same frame following the 5-bit MSB.
Data is always sampled on the falling edge of the clock in the same frame following the 5-bit MSB.
When SCS is asserted high, any signals at the SCLK and SDI pins are ignored, and SDO is forced into a highimpedance state. When SCS transitions from HIGH to LOW, SDO is enabled and the SPI response word loads
into the shift register based on 5-bit command.
The SCLK pin must be low when SCS transitions low. While SCS is low, at each rising edge of the clock, the
response bit is serially shifted out on the SDO pin with MSB shifted out first.
While SCS is low, at each falling edge of the clock, the new control bit is sampled on the SDI pin. The SPI
command bits are decoded to determine the register address and access type (read or write). The MSB will be
shifted in first. If the word sent to SDI is less than 16 bits or more than 16 bits, it is considered a frame error and
the data will not be written into the destination address. If it is a write command, the data will be ignored.
For a write command, the existing data in the register being written to is shifted out on SDO following the 5-bit
MSB.
SCS should be taken high for at least 500 ns between frames.
7.5.1.2 SPI Format
SPI input data control word is 16-bit long, consisting of:
1 read or write bit W [15]
4 address bits A [14:11]
11 data bits D [10:0]
SPI output data response word is 11-bit long (first 5 bits are ignored) and its content is the content of the register
being accessed
For a Write transaction: The response word is the data currently in the register being written to.
For a Read Command: The response word is the data currently in the register being read.
Table 7. SPI Input Data Control Word Format
R/W
ADDRESS
DATA
Word Bit
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Command
W0
A3
A2
A1
A0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Command
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
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NAME
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0x1
FAULT
Reserved
TEMP_FLAG4
PVDD_UVFL
PVDD_OVFL
VDS_STATUS
VCPH_UVFL
TEMP_FLAG1
TEMP_FLAG2
TEMP_FLAG3
OTW
0x2
OV/VDS Faults
FETHA_VDS
FETLA_VDS
FETHB_VDS
FETLB_VDS
FETHC_VDS
FETLC_VDS
Reserved
Reserved
SNS_C_OCP
SNS_B_OCP
SNS_A_OCP
0x3
IC Faults
PVDD_UVLO2
WD_FAULT
OTS
Reserved
VREG_UV
AVDD_UVLO
VCP_LSD_UVLO
Reserved
VCPH_UVLO
VCPH_OVLO
VCPH_OVLO_A
BS
0x4
FETHA_VGS
FETLA_VGS
FETHB_VGS
FETLB_VGS
FETHC_VGS
FETLC_VGS
Reserved
Reserved
Reserved
Reserved
Reserved
0x5
HS Gate Driver
Control
Reserved
TDRIVEN[1]
TDRIVEN[0]
IDRIVEN_HS[3]
IDRIVEN_HS[2]
IDRIVEN_HS[1]
IDRIVEN_HS[0]
IDRIVEP_HS[3]
IDRIVEP_HS[2]
IDRIVEP_HS[1]
IDRIVEP_HS[0]
0x6
LS Gate Driver
Control
Reserved
TDRIVEP[1]
TDRIVE[0]
IDRIVEN_LS[3]
IDRIVEN_LS[2]
IDRIVEN_LS[1]
IDRIVEN_LS[0]
IDRIVEP_LS[3]
IDRIVEP_LS[2]
IDRIVEP_LS[1]
IDRIVEP_LS[0]
0x7
Gate Drive
Control
Reserved
COMM_OPTION
PWM_MODE[1]
PWM_MODE[0]
DEAD_TIME[2]
DEAD_TIME[1]
DEAD_TIME[0]
TBLANK[1]
TBLANK[0]
TVDS[1]
TVDS[0]
0x8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DIS_GDRV
FAULT
EN_SNS_CLAM
P
WD_DLY[1]
WD_DLY[0]
DIS_SNS_OCP
WD_EN
SLEEP
CLR_FLTS
SET_VCPH_UV
0x9
IC Operation
FLIP_OTS
DISABLE
VPVDD_UVLO2
0xA
Shunt Amplifier
Control
DC_CAL_CH3
DC_CAL_CH2
DC_CAL_CH1
CS_BLANK[1]
CS_BLANK[0]
GAIN_CS3[1]
GAIN_CS3[0]
GAIN_CS2[1]
GAIN_CS2[0]
GAIN_CS1[1]
GAIN_CS1[0]
0xB
Voltage
Regulator Control
Reserved
VREF_SCALE[1]
VREF_SCALE[0]
Reserved
Reserved
Reserved
SLEEP_DLY[1]
SLEEP_DLY[0]
DIS_VREG_PW
RGD
VREG_UV_LEVE
L[1]
VREG_UV_LEVE
L[0]
0xC
VDS Sense
Control
Reserved
Reserved
Reserved
VDS_LEVEL[4]
VDS_LEVEL[3]
VDS_LEVEL[2]
VDS_LEVEL[1]
VDS_LEVEL[0]
VDS_MODE[2]
VDS_MODE[1]
VDS_MODE[0]
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R/W
NAME
DEFAULT
DESCRIPTION
10
FAULT
0x0
0 - Warning,
1 - Latched fault
Reserved
0x0
TEMP_Flag4
0x0
PVDD_UVFL
0x0
PVDD_OVFL
0x0
VDS_STATUS
0x0
VCHP_UVFL
0x0
TEMP_Flag1
0x0
TEMP_Flag2
0x0
TEMP_Flag3
0x0
OTW
0x0
Overtemperature warning
R/W
NAME
DEFAULT
DESCRIPTION
10
FETHA_VDS
0x0
FETLA_VDS
0x0
FETHB_VDS
0x0
FETLB_VDS
0x0
FETHC_VDS
0x0
FETLC_VDS
0x0
4:3
Reserved
0x0
SNS_C_OCP
0x0
SNS_B_OCP
0x0
SNS_A_OCP
0x0
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R/W
NAME
DEFAULT
DESCRIPTION
10
PVDD_UVLO2
0x0
WD_FAULT
0x0
Watchdog fault
OTS
0x0
Overtemperature fault
Reserved
0x0
VREG_UV
0x0
AVDD_UVLO
0x0
VCP_LSD_UVLO
0x0
Reserved
0x0
VCPH_UVLO
0x0
VCPH_OVLO
0x0
VCPH_OVLO_ABS
0x0
R/W
NAME
DEFAULT
DESCRIPTION
10
FETHA_VGS
0x0
FETLA_VGS
0x0
FETHB_VGS
0x0
FETLB_VGS
0x0
FETHC_VGS
0x0
FETLC_VGS
0x0
4:0
Reserved
0x0
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BIT
R/W
NAME
DEFAULT
10
R/W
Reserved
0x0
DESCRIPTION
9:8
R/W
TDRIVEN
0x3
7:4
R/W
IDRIVEN_HS
0x4
3:0
R/W
IDRIVEP_HS
0x4
- 30 mA
- 70 mA
- 0.75 A
- 60 mA
b'0010
b'0110
b'1010
b'1110
- 40 mA
- 80 mA
- 1.00 A
- 60 mA
b'0011
b'0111
b'1011
b'1111
- 50 mA
- 0.25 A
- 1.25 A
- 60 mA
- 30 mA
- 70 mA
- 0.75 A
- 50 mA
b'0011
b'0111
b'1011
b'1111
- 40 mA
- 0.125 A
- 1.00 A
- 50 mA
- 40 mA
- 80 mA
- 1.00 A
- 60 mA
b'0011
b'0111
b'1011
b'1111
- 50 mA
- 0.25 A
- 1.25 A
- 60 mA
- 30 mA
- 70 mA
- 0.75 A
- 50 mA
b'0011
b'0111
b'1011
b'1111
- 40 mA
- 0.125 A
- 1.00 A
- 50 mA
7.6.7.2
b'0001
b'0101
b'1001
b'1101
b'0001
b'0101
b'1001
b'1101
- 20 mA
- 60 mA
- 0.50 A
- 50 mA
b'0010
b'0110
b'1010
b'1110
BIT
R/W
NAME
DEFAULT
10
R/W
Reserved
0x0
DESCRIPTION
9:8
R/W
TDRIVEP
0x3
7:4
R/W
IDRIVEN_LS
0x4
3:0
R/W
IDRIVEP_LS
0x4
- 30 mA
- 70 mA
- 0.75 A
- 60 mA
b'0010
b'0110
b'1010
b'1110
34
b'0001
b'0101
b'1001
b'1101
b'0001
b'0101
b'1001
b'1101
- 20 mA
- 60 mA
- 0.50 A
- 50 mA
b'0010
b'0110
b'1010
b'1110
DRV8305
www.ti.com
7.6.7.3
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R/W
Reserved
0x0
R/W
COMM_OPTION
0x1
8:7
R/W
PWM_MODE
0x0
PWM Mode
b'00 - PWM with 6 independent inputs
b'01 - PWM with 3 independent inputs
b'10 - PWM with one input
b'11 - PWM with 6 independent inputs
6:4
R/W
DEAD_TIME
0x1
Dead time
b'000 - 40 ns
b'011 - 500 ns
b'110 - 4000 ns
3:2
R/W
TBLANK
0x1
1:0
R/W
TVDS
0x2
b'001 - 60 ns
b'100 - 1000 ns
b'111 - 6000 ns
b'010 - 100 ns
b'101 - 2000 ns
35
DRV8305
SLVSCX2A AUGUST 2015 REVISED SEPTEMBER 2015
7.6.7.4
www.ti.com
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R/W
Flip_OTS
0x0
Enable OTS
b'0 - Disable OTS
b'1 - Enable OTS
R/W
DIS_VPVDD_UVLO2
0x0
R/W
DIS_GDRV_FAULT
0x0
R/W
EN_SNS_CLAMP
0x0
6:5
R/W
WD_DLY
0x1
R/W
DIS_SNS_OCP
0x0
R/W
WD_EN
0x0
R/W
SLEEP
0x0
R/W
CLR_FLTS
0x0
Clear faults
b'0 - Normal operation
b'1 - Clear fault bits
R/W
SET_VCPH_UV
0x0
36
DRV8305
www.ti.com
7.6.7.5
BIT
R/W
NAME
DEFAULT
DESCRIPTION
10
R/W
DC_CAL_CH3
0x0
DC Calibration of CS amplifier 3
b'0 - Normal operation
b'1 - DC calibration mode
R/W
DC_CAL_CH2
0x0
DC Calibration of CS amplifier 2
b'0 - Normal operation
b'1 - DC calibration mode
R/W
DC_CAL_CH1
0x0
DC Calibration of CS amplifier 1
b'0 - Normal operation
b'1 - DC calibration mode
7:6
R/W
CS_BLANK
0x0
5:4
R/W
GAIN_CS3
0x0
Gain of CS amplifier 3
b'00 - 10 V/V
b'01 - 20 V/V
b'10 - 40 V/V
b'11 - 80 V/V
3:2
R/W
GAIN_CS2
0x0
Gain of CS amplifier 2
b'00 - 10 V/V
b'01 - 20 V/V
b'10 - 40 V/V
b'11 - 80 V/V
1:0
R/W
GAIN_CS1
0x0
Gain of CS amplifier 1
b'00 - 10 V/V
b'01 - 20 V/V
b'10 - 40 V/V
b'11 - 80 V/V
7.6.7.6
BIT
R/W
NAME
DEFAULT
10
R/W
Reserved
0x0
9:8
R/W
VREF_SCALING
0x1
7:5
R/W
Reserved
0x0
4:3
R/W
SLEEP_DLY
0x1
R/W
DIS_VREG_PWRGD
0x0
0:1
R/W
VREG_UV_LEVEL
0x2
DESCRIPTION
VREF Scaling
b'00 - RSVD
b'01 - k = 2
b'10 - k = 4
b'11 - RSVD
Delay to power down VREG after SLEEP
b'00 - 0 s
b'01 - 10 s
b'10 - 50 s
b'11 - 1 ms
VREG undervoltage set point
b'00 - VSET-10%
b'01 - VSET-20%
b'10 - VSET-30%
b'11 - VSET-30%
37
DRV8305
SLVSCX2A AUGUST 2015 REVISED SEPTEMBER 2015
7.6.7.7
www.ti.com
BIT
R/W
NAME
DEFAULT
10:8
R/W
Reserved
0x0
7:3
R/W
VDS_LEVEL
0x19
DESCRIPTION
VDS comparator threshold
b'00000
V
b'00100
V
b'01000
V
b'01100
V
b'10000
V
b'10100
V
b'11000
V
b'11100
V
2:0
38
R/W
VDS_MODE
0x0
- 0.060
- 0.097
- 0.155
- 0.250
- 0.403
- 0.648
- 1.043
- 1.679
b'00001 - 0.068
V
b'00101 - 0.109
V
b'01001 - 0.175
V
b'01101 - 0.282
V
b'10001 - 0.454
V
b'10101 - 0.730
V
b'11001 - 1.175
V
b'11101 - 1.892
V
b'00010
V
b'00110
V
b'01010
0.197V
b'01110
V
b'10010
V
b'10110
V
b'11010
V
b'11110
V
- 0.076
- 0.123
- 0.317
- 0.511
- 0.822
- 1.324
- 2.131
b'00011
V
b'00111
V
b'01011
V
b'01111
V
b'10011
V
b'10111
V
b'11011
V
b'11111
V
- 0.086
- 0.138
- 0.222
- 0.358
- 0.576
- 0.926
- 1.491
- 2.131
VDS mode
b'000 - Latched shut down when over-current detected
b'001 - Report only when over current detected
b'010 - VDS protection disabled (no overcurrent sensing or reporting)
DRV8305
www.ti.com
39
DRV8305
SLVSCX2A AUGUST 2015 REVISED SEPTEMBER 2015
www.ti.com
PVDD
1 F
2.2 F
1 F
PVDD
24
23
22
21
13
10 k
27
26
25
1 F
SH_C
GL_A
GL_B
34.8 k
SL_A
GL_B
34.8 k
GL_A
GL_C
SL_A
SN1
GH_C
1000 pF
SH_C
SP1
SL_B
SN2
1000 pF
SP2
SL_C
SN3
1000 pF
0.1 F
SH_B
GH_B
4.99 k
SL_B
CSENSE
28
VCC
SH_B
5 m
29
SH_A
0.1 F
30
SH_A
4.99 k
31
GH_C
VCC
34.8 k
32
GH_B
VCC
BSENSE
GL_C
33
1 F
1 F
SCLK
34
GH_A
GH_A
SP3
SL_C
GL_B
SP1
SL_C
SN1
SH_C
SDO
SP2
SDI
SN2
GH_C
SP3
nSCS
35
4.99 k
GH_B
36
5 m
nFAULT
VCC
PVDD
PVDD
37
VCP_LSD
38
39
CP2H
VCPH
41
40
CP2L
PVDD
42
CP1L
CP1H
43
44
VDRAIN
46
45
GND
DVDD
SH_B
PWRGD
12
INLC
20
11
SL_B
DRV8305
SN3
10
SPI
INHC
SO3
GL_B
19
GPIO
INLB
SO2
SL_A
GL_A
18
10 k
INHB
17
INLA
SO1
VCC
GH_A
SH_A
AVDD
INHA
16
3
PWM
EN_GATE
GND
15
GPIO
WAKE
48
VREG
POWER
47
1 F
VCC
14
MCU
5 m
0.1 F
0.1 F
0.1 F
ASENSE
100
VCC
PVDD
VCC
34.8 k
0.01 F
0.1 F
470 F
470 F
SP1
SP2
SN1
SP3
SN2
1 F
SN3
GPIO
ADC
ASENSE
0.1 F
4.99 k
PVDDSENSE
PVDDSENSE
BSENSE
CSENSE
40
DRV8305
www.ti.com
REFERENCE
VALUE
PVDD
12 V
MR
0.5
ML
0.28 mH
Motor poles
MP
16 poles
MRPM
2000 RPM
NSW
Switching frequency
fSW
45 kHz
IDRIVEP
IDRIVEP
50 mA
IDRIVEN
IDRIVEN
60 mA
MOSFET QG
Qg
36 nC
MOSFET QGD
QGD
9 nC
RDS(on)
4.1 m
MOSFET RDS(on)
Target full-scale current
IMAX
30 A
Sense resistor
RSENSE
0.005
VDS_LVL
0.197 V
Amplifier bias
VBIAS
1.65 V
Amplifier gain
Gain
10 V/V
(2)
(3)
(4)
Submit Documentation Feedback
41
DRV8305
SLVSCX2A AUGUST 2015 REVISED SEPTEMBER 2015
www.ti.com
42
DRV8305
www.ti.com
43
DRV8305
SLVSCX2A AUGUST 2015 REVISED SEPTEMBER 2015
www.ti.com
Power Supply
Parasitic Wire
Inductance
Motor
Driver
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 16. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
44
DRV8305
www.ti.com
10 Layout
10.1 Layout Guidelines
Use the following layout recommendations when designing a PCB for the DRV8305.
The DVDD and AVDD 1-F bypass capacitors should connect directly to the adjacent GND pin to minimize
loop impedance for the bypass capacitor.
The CP1 and CP2 0.047-F flying capacitors should be placed directly next to the DRV8305 charge pump
pins.
The VCPH 2.2-F and VCP_LSD 1-F bypass capacitors should be placed close to their corresponding pins
with a direct path back to the DRV8305 GND net.
The PVDD 4.7-F bypass capacitor should be placed as close as possible to the DRV8305 PVDD supply pin.
Use the proper footprint as shown in the Mechanical, Packaging, and Orderable Information section.
Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the DRV8305
GH_X to the power MOSFET and returns through SH_X. The low-side loop is from the DRV8305 GL_X to the
power MOSFET and returns through SL_X.
45
DRV8305
SLVSCX2A AUGUST 2015 REVISED SEPTEMBER 2015
www.ti.com
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
46
www.ti.com
16-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
DRV83053PHP
ACTIVE
HTQFP
PHP
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV83053
DRV83053PHPR
ACTIVE
HTQFP
PHP
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV83053
DRV83055PHP
ACTIVE
HTQFP
PHP
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV83055
DRV83055PHPR
ACTIVE
HTQFP
PHP
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV83055
DRV8305NPHP
ACTIVE
HTQFP
PHP
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV8305N
DRV8305NPHPR
ACTIVE
HTQFP
PHP
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV8305N
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
www.ti.com
16-Sep-2015
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DRV8305 :
Automotive: DRV8305-Q1
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
16-Sep-2015
Device
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DRV83053PHPR
HTQFP
PHP
48
1000
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
DRV83055PHPR
HTQFP
PHP
48
1000
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
DRV8305NPHPR
HTQFP
PHP
48
1000
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
Pack Materials-Page 1
16-Sep-2015
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV83053PHPR
HTQFP
PHP
48
1000
367.0
367.0
38.0
DRV83055PHPR
HTQFP
PHP
48
1000
367.0
367.0
38.0
DRV8305NPHPR
HTQFP
PHP
48
1000
367.0
367.0
38.0
Pack Materials-Page 2
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