01

1. How to find word which is occuring number of times with linux in just one command?
Ans:
With Grep Command:
grep -o 'needle' file | wc -l
With AWK command:
awk -F'^needle | needle | needle$' '{c+=NF-1}END{print c}'
2. What is grep -v?
Ans:
Too find pattern matching word, use grep command & it switch -v is added then the found word
will be neglected including that raw.
3. How to find pattern in TCL?
Ans:
string match f* foo
4. what is diff between blocking & nonblocking? explain with example.
Ans:-Blocking assignments evaluate the RHS and update the LHS without interruption from any
other verilog statement
-A nonblocking assignment evaluates the RHS at the beginning of the time step and updates the
LHS at the end of the time step.
module block_nonblock();
reg a, b, c, d , e, f ;
// Blocking assignments
initial begin
a = #10 1'b1;// The simulator assigns 1 to a at time 10
b = #20 1'b0;// The simulator assigns 0 to b at time 30
c = #40 1'b1;// The simulator assigns 1 to c at time 70
end
// Nonblocking assignments
initial begin
d <= #10 1'b1;// The simulator assigns 1 to d at time 10
e <= #20 1'b0;// The simulator assigns 0 to e at time 20
f <= #40 1'b1;// The simulator assigns 1 to f at time 40
end
endmodule
5. What is diff between $finish & $stop?
Ans:$finish;
Finishes a simulation and exits the simulation process.
$stop;
Halts a simulation and enters an interactive debug mode.

6. Draw FSM sequence 110011 using overlap & nonoverlap.

Ans:-

7. Write verilog code for T-flipflop.

Ans:module tff_sync_reset (data,clk,reset,q);
input data, clk, reset ;
output q;
reg q;
always @ ( posedge clk)
if (reset)
begin
q <= 1'b0;
end
else if (data)
begin
q <= !q;
end
endmodule

8. Explain CMOS inverter

ANS :

You can easily see that the CMOS circuit functions as an inverter by noting that when VIN is five
volts, VOUT is zero, and vice versa. Thus when you input a high you get a low and when you input
a low you get a high.

9. What is Latchup?
ANS :

CMOS structure is a pair of parasitic bipolar transistors. The collector of each BJT is connected to
the base of the other transistor in a positive feedback structure.
A phenomenon called latchup can occur when:
(1) both BJT's conduct, creating a low resistance path between Vdd and GND and
(2) the product of the gains of the two transistors in the feedback loop, b1 x b2, is greater than one.
The result of latchup is at the minimum a circuit malfunction, and in the worst case, the destruction
of the device.
Latchup may begin when Vout drops below GND due to a noise spike or an improper circuit
hookup (Vout is the base of the lateral NPN Q2). If sufficient current flows through Rsub to turn on
Q2 (I Rsub > 0.7 V ), this will draw current through Rwell. If the voltage drop across Rwell is high
enough, Q1 will also turn on, and a self-sustaining low resistance path between the power rails is
formed.
If the gains are such that b1 x b2 > 1, latchup may occur.
Once latchup has begun, the only way to stop it is to reduce the current below a critical level,
usually by removing power from the circuit.

Preventing latchup:
1). Reduce the gain product b1 x b1
move n-well and n+ source/drain farther apart increases width of the base of Q2 and reduces
gain beta2 > also reduces circuit density
buried n+ layer in well reduces gain of Q1
2). Reduce the well and substrate resistances, producing lower voltage drops
higher substrate doping level reduces Rsub
reduce Rwell by making low resistance contact to GND
guard rings around p- and/or n-well, with frequent contacts to the rings, reduces the parasitic
resistances.

10. FSM sequence for 1011

Ans:

11. Why TCL is use instead of perl?

Ans:Those without a C/Unix background generally find Tcl syntax far easier to learn and retain.
Tcl is smaller. It is Tool command language.
Tcl is easier to extend and customize.
Tcl source code traditionally is a model of lucidity. perl source code traditionally is dense in
magic.
TCl is far more portable than perl and generally more current.
Tcl's exec, open and socket are gems of accessible and portable functionality, in comparison
to the analogous Perl offerings.
Tcl is a pure interpreter; Perl uses a bytecode engine.

12. How to add character in end of string in TCL?

Ans: append puts one string directly on the end of another, without adding any extra
characters beyond those in the incoming variables.
Ex:
set people "John Joan Jane"
# append adds to string, lappend adds to list puts $people
append people t
puts $people
output:John Joan Janet

13. What is regsub?

Ans:regsub - Perform substitutions based on regular expression pattern matching .
ex.
regsub -all a+ A b+ B aaaacccbbddda
output:AcccBdddA

14. What is testability?

Ans:Design for testing or design for testability (DFT) consists of IC design techniques that add
testability features to a hardware product design. The added features make it easier to develop and
apply manufacturing tests to the designed hardware. The purpose of manufacturing tests is to
validate that the product hardware contains no manufacturing defects that could adversely affect the
products correct functioning.

15. How to use TCL in vim Editor?

Ans:[dhruv@dhruv 1]$ gvim ex1.tcl

output:[dhruv@dhruv 1]$ tclsh ex1.tcl

The sum of 2 + 3 is: 5
The for command has been replaced by a puts
The arguments were: set i 1
$i < 10
incr i

16. Use of llength,append,lappend.

Ans:1)llength
#!/usr/bin/tclsh
set var {orange blue red green}
puts [llength $var]
output:4
2)append
set people "John Joan Jane"
# append adds to string, lappend adds to list puts $people
append people t
puts $people
output:John Joan Janet
3)lappend
set people "John Joan Jane"
lappend people Julian
puts $people
output:John Joan Jane Julian

17. How to check memory in Linux?

Ans:1. free command

The free command is the most simple and easy to use command to check memory usage on
linux. Here is a quick example
2. /proc/meminfo
The next way to check memory usage is to read the /proc/meminfo file. Know that the /proc
file system does not contain real files. They are rather virtual files that contain dynamic
information about the kernel and the system.
3. vmstat
The vmstat command with the s option, lays out the memory usage statistics much like the
proc command.
4. top command
The top command is generally used to check memory and cpu usage per process. However it
also reports total memory usage and can be used to monitor the total RAM usage. The
header on output has the required information. Here is a sample output

18. What is the use of cut command in linux?

Ans:Linux command cut is used for text processing. You can use this command to
extract portion of text from a file by selecting columns.
ex.
$ cat test.txt
cat command for file oriented operations.
cp command for copy files or directories.
ls command to list out files and directories with its attributes.
$ cut -c2 test.txt
a
p
s

19. Can you use linux commands in TCL?

Ans:Yes, we can use linux commands in TCL.

20. What is WLM? use of it.

Ans:Wire load modeling allows us to estimate the effect of wire length and fanout on the resistance,
capacitance, and area of nets. Synthesizer uses these physical values to calculate wire delays and
circuit speeds. Semiconductor vendors develop wire load models, based on statistical information
specific to the vendors process. The models include coefficients for area, capacitance, and
resistance per unit length, and a fanout-to-length table for estimating net lengths (the number of
fanouts determines a nominal length).

21 What is synthesis?
Ans. Synthesis is a process if conversion of RTL file (that is technology independent) to get level
NETLIST file (that is technology dependent).
22 What is synthesis process?
Ans. There are 3 steps in Synthesis Process:
Translation: RTL code is translated to technology independent representation. The converted logic
is available in boolean equation form.
Optimization: Boolean equation is optimized using SoP or PoS optimization methods.
Technology mapping: Technology independent boolean logic equations are mapped to technology
dependant library logic gates based on design constraints, library of available technology gates.
This produces optimized gate level representation which is generally represented in verilog.
23 Input and Output of synthesis.
Ans.
INPUT:RTL- Register Transfer Level
RTL is the functional description of the design to logic synthesis which is represented by
HDIs.
Register: Storage element like F-F, latches
Transfer: Transfer data between input, output and register using combinational logic.
Level: Level of Abstraction modeled using HDL.
Target Library:

Standard cell library corresponding to a particular technology node (eg. 45nm).

Collection of combinational logic gates and sequential logic elements which are used to
convert HDL to gate level netlist.
These libraries have all Logical and Physical information required for fabrication of IC.

Constraints:Meet the optimization constraints specified by the designer.

Timing Constraints: Clock definition. The synthesis tool tries to meet the setup and hold
timing constraints on the sequential logic in the design.
Output:

Gate Level Netlist

A netlist consists of a list of the terminals ("pins") of the electronic components in a circuit and a
list of the electrical conductors that interconnect the terminals.

24 How to extract word from script file?

Ans. Using AWK command FS input field separator variable
command:- awk BEGIN{FS:}{print$2} test.txt

use of print$2 in above command to extract word after the pattern : matching as shown in above
fig.

And use of print$1 in above command to extract word before the pattern : matching as shown in
above fig.
25. In cmos inverter if we change nmos instead of pmos so what effect occurred.
Ans. If we change the position of nmos and pmos so it work as a week buffer.

26. What is netlist file?

Ans. A netlist consists of a list of the terminals ("pins") of the electronic components in a circuit
and a list of the electrical conductors that interconnect the terminals.
27. Differance between scan mux dff and mux followed by dff in dft.
Ans.
Normal Flip-Flop have D, Clk & Q.
Scan flop have D, SI (scan in), SE (scan enable), Clk, Q and/or SO (scan out).
Scan mux dff is an optimized.

28. Which command you use in LINUX?

Ans.
Cd, pwd, ls -al , cd . , cd .. , ls -al |more , cat, echo, passwd, date, hostname, arch,uname -a,
dmesg , uptime, who am I, who, id, last, w, top, echo $SHELL , man, clear, time sleep 5, history,
awk, sed, lappend, grep, mkdir, rm,tar, find, ssh, vim, diff, sort, xargs, find, gzip, unzip, shutdown,
ps, free, kill, mount, chmod, chown, ifconfig, head, tail, yum
29. What is LINUX? why we use this?
Ans.
Linux is, in simplest terms, an operating system. It is the software on a computer that enables
applications and the computer operator to access the devices on the computer to perform desired
functions.
Why we use
~> Linux is free of charge and in case you still doubt, then know that it is.
~> Linux is more secured than any other server
~> It has a wide compatibility to several hardware
~> Easy to operate
~> It comes inclusive of drivers
~> Linux is speedy
~> Smooth and easy Updating Process
30. What is the commmand to check CPU & memory info.?
Ans.
For cpu info :- /proc/cpuinfo
For memory info: /proc/meminfo
or
top
31. What is grep? How we can use?
Ans.
grep mainly searches the input file(s) for lines containing a match to the given strings or words. By
default, it prints the matching lines. There are various other ways to use grep command
Syntax
grep "string_to_match" input_file_name
or
command | grep "string"
32. What is blocking and non Blocking ? with example
Ans.
Blocking assignments evaluate the RHS and update the LHS without interruption from any
other verilog statement
A nonblocking assignment evaluates the RHS at the beginning of the time step and updates the LHS
at the end of the time step.
module block_nonblock();
reg a, b, c, d , e, f ;
// Blocking assignments

initial begin
a = #10 1'b1;// The simulator assigns 1 to a at time 10
b = #20 1'b0;// The simulator assigns 0 to b at time 30
c = #40 1'b1;// The simulator assigns 1 to c at time 70
end
// Nonblocking assignments
initial begin
d <= #10 1'b1;// The simulator assigns 1 to d at time 10
e <= #20 1'b0;// The simulator assigns 0 to e at time 20
f <= #40 1'b1;// The simulator assigns 1 to f at time 40
end
endmodule
33. What is the difference between $monitor & $finish?
Ans.
$monitor displays every time one of its parameters changes.
$finish exits the simulator back to the operating system.
34. What is FSM?
Ans.
In general, a state machine is any device that stores the status of something at a given time and can
operate on input to change the status and/or cause an action or output to take place for any given
change.
35. Write a code for D_FF?
Ans.
module dff (q,data,clk,reset);
output q;
reg q;
input data,clk,reset;
always @(reset or posedge clk)
if (~reset)
begin
q <= 1'b0;
end
else
begin
q <= data;
end
endmodule
36. What is lappend?
Ans.
Lappend is similar to append except that the values are appended as list elements rather than raw
text. This command provides a relatively efficient way to build up large lists.

37. What is synthesis?

Ans.
Synthesis is the process to convert RTL in to GATE level netlist.
In other sense,
Synthesis is the step of mapping RTL files to the targeted library cells and convert it to the actual
hardware.
38. What are the steps for sysnthesis?
Ans
~>import library
~>import RTL
~>perform high-level optimization.
~>Select a scan style.
~>Perform area-based optimization.
~>Apply timing constraints.
~>Flatten user hierarchy
~>Check DFT ru;es and insert scan.
~>Perform constraints-based optimization.
~>Perform timing and strength analysis.
39. How many libraries are in sysnthesis?
Ans.
1. Symbolic lib.
2. design ware lib. Or synthetic lib.
3. link lib.
4. target lib.
40. What is Max,Min and typ. cases in files?
Ans.
the worst case libs (max delay) for setup checks and best case libs (min delay) for hold checks,
because setup violatons are caused due to slow data paths or fast clock paths and hold violatons are
caused due to fast data and slow clock paths
41. What is optimization?
Ans.
Finding an alternative with the most cost effective or highest achievale performence under the given
constraints, by maximizing desired factors and minimizing undesired ones.
42. What is TCL ?
Ans.
It stands for tool command language.While it's hard to give accurate numbers or input, in that cases
we can use TCL.
43. Why we need TCL ?
Ans.
As a developer we get instant gratification and can see immediate results since Tcl is interpreted and
we don't have to wait for compilation. Tcl also has allowed us to build an easy-to-use, intuitive, and
easy-to-maintain graphical user interface for our product.

44. What is DFT?

Ans.
To add circuitary that allows designer to perform controlability and observability on every cell is
called DFT.
45. Full form of PERL.
Ans.
Practical extraction reporting language.
46. what is scan chain?
Ans.
It the the process of converting normal FF into scanalable ff such that designer can modify the
design to use either in functional mode or test mode as & when needed with proper test vectors.
47. Why we need DFT? at which stage we use DFT?
Ans.
To determine the presence of faults in a given circuit.
Which stage we use:~>Software process executed once during the design.
~>tests applied to hardware after manufaturing.
48. What is JTAG?
Ans.
JTAG is an IEEE standard developed in 1980s to solve electronic board manudacturing issue.
Nowdays it finds more use as programming, debug and probuing port.
49. TAP Registers in JTAG
Ans.
1. Boundary scanalable reg.
2. Bypass reg.
3. Device id reg.
4. Data-specific reg.
5. Instruction reg.
50. What is BIST? Types of it.
Ans.
BIST is a Built in self test is a DFT tech. That places a device testing function within the device
itself thereby eliminating or least minimizing the need for external test equipment.
Two types 1. Lbist 2. Mbist.
51. MBIST working modes?
Ans.
It works in 4 modes
1. Functional mode
2. Go/No-go test mode
3. Debug mode
4. Retention mode
52. Do we have to give input for BIST and ATPG ?
Ans.
NO.

53. Describe process of BIST?

Ans.
Many designs need to be tested or retested in a system or board. For this, you need logic BIST (Fig.
2). A BIST engine is built inside the chip and requires only an access mechanism like the test access
port (TAP) to start. When a device is powered on, BIST can also check that the logic is working
properly before starting any functional tests.

BIST sends out test patterns generated by a pseudorandom pattern generator (PRPG) along scan
chains and then collects the responses in a multiple-input signature register (MISR). The final
content of the MISR is a signature that determines the pass/fail result. The signature is typically sent
out via the TAP and then compared to a pre-calculated, or expected, signature.
54. Syntax for pattern matching.
Ans.
grep "string_to_match" input_file_name
or
command | grep "string"
55. what is awk ? Describe about in brief.
Ans.
Awk is kind of a text processing programming language, and can be used to manipulate text in
many ways. It can also be used for data processing from text files.
A simple 'awk' command can be run from the command line. More complex tasks should be
written as 'awk' program to a file, kind of a script file.
Awk Variables:
'awk' variables do not need to be declared before and also are independent of any data type.
Variable name should be started with a letter and can be continued with letters, digits,
underscores. Also variable name is case sensitive. Here are commonly used built-in variables:
~>NR: The current line's sequential number
~>NF: The number of fields in the current line
~>FS: The input field separator; which is set default to white space and can be reset by -F
command line parameter.

56. What is DFT? What is the requirement and What happens after DFT to the ckt?
- To add circuitary that allows designer to perform controlability and observability on every cell is
called
DFT. To determine the presence of faults in a given circuit.
The circuit becomes bulky as we include testing circuitry and get observable and controllable after
the manufacture.
57. What is Synthesis? Inputs and Outputs of synthesis. Libraries used in synthesis.
- Synthesis is the process to convert RTL in to GATE level netlist.
In other sense, Synthesis is the step of mapping RTL files to the targeted library cells and convert it
to the actual hardware.
Inputs RTL file, Constraints, Technology Library
Outputs Gate level Netlist
Libraries in synthesis are Synthetic lib, Symbol lib, link lib and Target library.
58. What happens if I replace the PMOS & NMOS in inverter? Yes it acts as a buffer but why
dont we use that buffer in circuit?
- Because if we put NMOS with Vcc, it will need more threshold, while the PMOS will be needing
less threshold. And hence we say, NMOS is good to pass logic 0 and PMOS is good to pass logic 1.
59. Extracting data using awk
- We can simply write awk '{print $1}' abc.txt (file name)
Where $1 will replace or $2 will represent the column of the file.
60. What is the reason we are shifting from MOSFET to FINFET?
- Because as the technology is shrinking, it is difficult to avoid short channel effects.
Like for e.g., below 24nm tech, the short channel effects goes uncontrollable, so we moved to
FINFET.
61. Difference between target library & link library
- Target library is basically used for mapping...while for link library we can say it is used for
resolving functional references.
62. What are the short channel effects?
- When in MOSFET, the channel length keeps on shrinking, few loses occurs between drain and
source terminals due to parasitic drain and source terminals. Hence we had to move for FINFET.
63. Difference between CMOS and FINFET
Ans. Structure wise difference:
CMOS structure:

FINFET 3D structure:

The traditional transistor takes significantly higher amount of power so the entire chipset will
consume a greater amount of power because a chipset contains billions of transistors. Due to this
high power consumption, the sustainability of the processor will decrease along with heat increase,
which is not desired. Talking about FinFET transistors, these will use standard drain and contacts so
it takes less power and expose less heat so the processor performance wont fall like the traditional
chip. This is the main reason; all the chip makers are interested in FinFET technology. There is
another important reason that is, FinFET transistors will take a lot less power at the stand-by time.
Advantages over planer MOSFET:
1.Higher transconductance (current out per voltage in)
2.Lower apparent input capacitance for the same gain
3.Less wafer area per transistor to get high gain, as the fin height can be increased in order to get
high gain
4.Fully depleted structure, enabling better on/off contrast
5.I-V curves get flatter, meaning lower dynamic power consumption.
6.Reducing short-channel effects by more effectively physically separating the source and drain
rather than letting them couple as a PNP or NPN structure beneath the channel
64. Perl Script (Email Assignmnet)
Ans.

In email assignment the task was that, there is one .xlxs perl doubt sheet that was on google drive
using perl script access that file and find the unanswered queries and then that unanswered queries
are sent by email to TA or student.
Following cpan modules are used:
Email::Send;
Email::Send::Gmail;
Email::Simple::Creator;
Email::Send::SMTP::Gmail;
Spreadsheet::Read;
then we installed google drive package to my pc and get access to google drive. After that we
downloaded that doubt sheet and read that file. To find unanswered queries we checked the column
of queries if there is no data in particular cell then that questions are unanswered. So we compared
with white-space and find out list of unanswered queries, then save to text file and that text had
been mailed to TA or Student.

65. How finfet is faster than CMOS

Ans. Faster switching speed because of lower input capacitance and higher dynamic current density
in finfet compare to cmos.
66. what is fanout? How fanout and capacitance affect driving strength
Ans.

Fanout : It defines the maximum number of gates which can be driven by driving gate.if output load
capacitance increases number of fanout increases so driving strength will increase.
67. lib files for DC tool and its contents
Ans.

Three types of lib files are there. 1) max lib 2) min lib and 3) Typical lib file.
These library file contain wire load model, default specifications, operating condition.
Max lib is for worst case scenario, min lib is for best case scenario and typical is for normal
scenario.
68. From lib file, which cell is taken by synthesis tool from the list of cells like AND2X1,
AND2X2, etc...
69. how to match two different pattern using grep command. Use only single grep command
Ans.
grep -e can match multiple pattern.
grep -e pattern1 -e pattern2 file_name

70. design frequency divider in verilog

module freq_divider_by_2 ( input clk,rst,

output reg clk_d2);
always @(posedge clk)
begin
if (~rst)
clk_d2 <= 1'b0;
else
clk_d2 <= ~clk_d2;
end
endmodule

71. Why DFT?

Ans.
Post-production testing is necessary because, the process of manufacturing is not 100% error
free. There are defects in silicon which contribute towards the errors introduced in the physical
device.
Of course a chip will not work as per the specifications if there are any errors introduced in
the production process. But the question is how to detect that. Since, to run all the functional tests
on each of say a million physical devices produced or manufactured, is very time consuming, there
was a need to device some method, which can make us believe without running full exhaustive tests
on the physical device, that the device has been manufactured correctly. DFT is the answer for that.
It is a technique which only detects that a physical is faulty or is not faulty.
After the post-production test is done on a device, if it is found faulty, trash it, dont ship to
customers, if it is found to be good, ship it to customers. Since it is a production fault, there is
assumed to be no cure. So it is just a detection, not even a localization of the fault. That is our
intended purpose of DFT. For the end customer, the DFT logic present on the device is a redundant
logic.
To further justify the need of DFT logic, consider an example where a company needs to
provide 1 Million chips to its customer. If there isnt any DFT logic in the chip, and it takes for
example, 10 seconds (Its very kind and liberal to take 10 seconds as an example, in fact it can be
much larger than that) to test a physical device, then it will take approx. three and a half months just
to test the devices before shipping. So the DFT is all about reducing three and a half months to may
be three and a half days. Of course practically many testers will be employed to test the chips in
parallel to help reduce the test time.
72. What is Synthesis and Input & output of Synthesis flow?
Ans.

Synthesis is the process to convert RTL in to GATE level netlist .

In other sense,

Synthesis is the step of mapping RTL files to the targeted library cells and convert it to the
actual hardware.

73. AWK to print a given particular column from the report generated in synthesis.
Ans. Report.txt
SIMULATION TIME : 2MS
VOLTAGE

: 3V

TEMPERATURE

: 25

$ awk '{if($1=="SIMULATION")print $2if($1=="VOLTAGE")print $2}' file

74. What is ATPG?
ATPG(acronym for both Automatic Test Pattern Generation and Automatic Test Pattern
Generator) is an electronic design automation method/technology used to find an input (or
test) sequence that, when applied to a digital circuit, enables automatic test equipment to
distinguish between the correct circuit behaviour and the faulty circuit behaviour caused
by defects.
75.How we perform ATPG?
Ans.

Given the design complexity, manual generation of test vectors is time-consuming. Almost
IMPOSSIBLE.
So, we have tools to do it FastScan, TK, TetraMax etc..

ATPG tool picks faultsfrom the target list

Generates patternsto detect faults

Fault simulates the pattern against all other faults

Removes detected faults from list.

Repeats until no more faults in list

76. Which are the Optimization constraints Types?

Ans.Three types of constraints can be set for the design in Design Compiler (DC). They are:
1) DRC constraints
2) Optimization constraints
3) Environmental constraints.
DRC constraints exist in library. DRC constraints cant be relaxed. They can be chosen
from library.
DRC constraints are: set_max_fanout, set_max_transition, set_max_capacitance.
If DRC constraints are not specified, then default values from the library are taken.
Three types of optimizations are possible-area, power and timing. We have optimization
constraints related to all these. set_max_area, set_min_area are area constraints.
Only basic level of power optimization is carried out by DC. Its primary target is to meet
timing constraints. set_max_leakege and set_max_dynamic are the two power constraints
that can be provided to DC.
Both DRC and optimization constraints follow environmental constraints. Setting up of
operating conditions and wire load model falls under environmental constraints. The
constraints

are:

set_operating_conditions,

set_wire_load_model

and

set_wire_load_mode. By default enclosed wire load mode is considered by DC.

77. What is a USE of Different Libraries in synthesis Design Compiler?

Ans.

link_library : the library used for interpreting input description

Any cells instantiated in your HDL code

Wire load or operating condition modules used during synthesis

target_library : the ASIC technology which the design is mapped

symbol library _library : used for schematic generation

search_path : the path for unsolved reference library

synthetic_path : designware library]

78. What is Scan D-Flipflop?

79. Scan cells working For MUX and DFF cells.
Ans.

What are scan chains: Scan chains are the elements in scan-based designs that are used to
shift-in and shift-out test data. A scan chain is formed by a number of flops connected back to
back in a chain with the output of one flop connected to another. The input of first flop is
connected to the input pin of the chip (called scan-in) from where scan data is fed. The output
of the last flop is connected to the output pin of the chip (called scan-out) which is used to take
the shifted data out. The figure below shows a scan chain.

A scan chain

Purpose of scan chains: As said above, scan chains are inserted into designs to shift the test data into
the chip and out of the chip. This is done in order to make every point in the chip controllable and
observable as discussed below.
How normal flop is transformed into a scan flop: The flops in the design have to be modified in order
to be put in the scan chains. To do so, the normal input (D) of the flip-flop has to be multiplexed with
the scan input. A signal called scan-enable is used to control which input will propagate to the output.

Figure showing transition of a normal flop to scan flop

If scan-enable = 0, data at D pin of the flop will propagate to clock at the next active edge
If scan-enable= 1, data present at scan-in input will propagate to Q at the next active edge
Scan terminology: Before we talk further, it will be useful to know some signals used in scan chains
which are as follows:

Scan_in ->Input to the flop/scan-chain that is used to provide scan data into

 Scan_out ->Output from flop/scan-chain that provides the scanned data to the next flop/output
Scan_enable ->Input to the flop that controls whether scan_in data or functional data will propagate to
output
Purpose of testing using scan: Scan testing is carried out for various reasons, two most prominent of them
are:
To test stuck-at faults in manufactured devices
To test the paths in the manufactured devices for delay; i.e. to test whether each path is working at
functional frequency or not
How a scan chain functions: The fundamental goal of scan chains is to make each node in the circuit
controllable and observable through limited number of patterns by providing a bypass path to each flipflop. Basically, it follows these steps:
1.Assert scan_enable (make it high) so as to enable (SI -> Q) path for each flop
2.Keep shifting in the scan data until the intended values at intended nodes are reached
3.De-assert scan_enable (for one pulse of clock in case of stuck-at testing and two or more
cycles in case of transition testing) to enable D->Q path so that the combinational cloud output
can be captured at the next clock edge.
4.Again assert scan_enable and shift out the data through scan_out
The PDF (How does scan work) provides a very good explanation to how scan chains function.
How Chain length is decided: By chain length, we mean the number of flip-flops in a single scan
chain. Larger the chain length, more the number of cycles required to shift the data in and out. However,
considering the number of flops remains same, smaller chain length means more number of input/output
ports is needed as scan_in and scan_out ports. As
Number of ports required = 2 X Number of scan chains
Since for each scan chain, scan_in and scan_out port is needed. Also,
Number of cycles required to run a pattern = Length of largest scan chain in design
Suppose, there are 10000 flops in the design and there are 6 ports available as input/output. This means
we can make (6/2=) 3 chains. If we make scan chains of 9000, 100 and 900 flops, it will be inefficient as
9000 cycles will be required to shift the data in and out. We need to distribute flops in scan chains
almost equally. If we make chain lengths as 3300, 3400 and 3300, the number of cycles required is
3400.
Keeping almost equal number of flops in each scan chain is referred to as chain balancing.

80.How two different CLK works in clocked Scan DFF?

Ans.
Clocked-Scan The clocked-scan architecture is very similar to the mux-DFF architecture,
but uses a dedicated test clock to shift in scan data instead of a multiplexer. Figure 1.3 shows an
original design flip-flop replaced with clockedscan circuitry.

Fig.1 clocked scan replacement In normal operation, the system clock (sys_clk) clocks
system data (data) into the circuit and through to the output (Q). In scan mode, the scan clock
(sc_clk) clocks scan input data (sc_in) into the circuit and through to the output (sc_out).
81.What is Stuck-at Fault Models?
Ans:

The stuck-at-0 fault means a signal that is permanently low regardless of the other signals that

normally control the node, as shown in Figure 1. The stuck-at-1 fault represents a signal that is
permanently high regardless of the other signals that normally control the node. For example,
assume that you have a two-input AND gate that has stuck-at-0 fault on the output pin.
82. jagathi.txt and abc.txt which contains word jagathi .If we write egrep -r jagathi.txt then
what it returns?
A. then it searches the word jagathi in the text files and print them with the number of counts of
jagathi is found.
83. what if I consider $a= @a then print $a?
A. then it prints all the elements present in the @a.
84. I have a word like *- xxx jag xxx 123 in between of 10 lines then I need a command to find
and print this jag and 123?
A. then I need to print it with perl like /((\d+) (\w+) (\d+))/; so that it will identify the digits and
alphabets.
85. what is the command to find out the word in grep ?
A. grep -w word *

86. how many types of greps are available ?

A. fgrep , egrep, pgrep, rgrep.
87. what are the advantages of linux over windows?
A. linux is multi tasking, its a multi user, its having multi processing, its a free open source no
license activation required for linux, and we are using kernel for the interfacing with hardware and
its an convertible language for the user using hardware from machine language to user language.
And software cost is also low.
88. what is major role of shell scripting ?
A. its functionality gets increased and it can be used to control and communicate the with other
software tools, scripting languages, graphic tools, telecommunication tools.
89. why Nacl is called as the electrons even though Na is having holes as its majority?
A. An atom of sodium has one 3s electron outside a closed shell, and it takes only 5.14 electron
volts of energy to remove that electron. The chlorine lacks one electron to fill a shell, and releases
3.62 eV when it acquires that electron (it's electron affinity is 3.62 eV). This means that it takes only
1.52 eV of energy to donate one of the sodium electrons to chlorine when they are far apart. When
the resultant ions are brought closer together, their electric potential energy becomes more and more
negative, reaching -1.52 eV at about 0.94 nm separation. This means that if neutral sodium and
chlorine atoms found themselves closer than 0.94 nm, it would be energetically favorable to transfer
an electron from Na to Cl and form the ionic bond.
90. why we are using sensitivity list in verilog what its role ?
A. the sensitivity list is having the instances which are helpful in declaring the nets and regs in the
exact functionality in the circuit , and if u consider the example of clk as positive edge or negative it
depends on the functionality of the clock so that the effect will be less on circuit so we are using the
sensitivity list.
91. explain the cmos with its diagram ?

A. Metal-Oxide-Semiconductor (MOS) transistor was introduced in terms of its operation as an

ideal switch. the performance and power of a chip depend on the current and capacitance of the
transistors and wires. the MOS transistor is a majority-carrier device in which the current in a
conducting channel between the source and drain is controlled by a voltage applied to the gate. In
an nMOS transistor, the majority carriers are electrons; in a pMOS transistor, the majority carriers
are holes. The behavior of MOS transistors can be understood by first examining an isolated MOS
structure with a gate and body but no source or drain. The top layer of the structure is a good
conductor called the gate. Early transistors used metal gates. Transistor gates soon changed to use

polysilicon, i.e., silicon formed from many small crystals. The middle layer is a very thin insulating film of SiO2 called the gate oxide. The bottom layer is the doped silicon body. The figure
shows a p-type body in which the carriers are holes. The body is grounded and a voltage is applied
to the gate. The gate oxide is a good insulator so almost zero current flows from the gate to the
body.
92. Explain cMOs iverter
ANS :

You can easily see that the CMOS circuit functions as an inverter by noting that when VIN is five
volts, VOUT is zero, and vice versa. Thus when you input a high you get a low and when you input
a low you get a high.
93. What is Latchup ?
ANS :

CMOS structure is a pair of parasitic bipolar transistors. The collector of each BJT is connected to
the base of the other transistor in a positive feedback structure.
A phenomenon called latchup can occur when:
(1) both BJT's conduct, creating a low resistance path between Vdd and GND and
(2) the product of the gains of the two transistors in the feedback loop, b1 x b2, is greater than one.
The result of latchup is at the minimum a circuit malfunction, and in the worst case, the destruction
of the device.
Latchup may begin when Vout drops below GND due to a noise spike or an improper circuit
hookup (Vout is the base of the lateral NPN Q2). If sufficient current flows through Rsub to turn on
Q2 (I Rsub > 0.7 V ), this will draw current through Rwell. If the voltage drop across Rwell is high

enough, Q1 will also turn on, and a self-sustaining low resistance path between the power rails is
formed.
If the gains are such that b1 x b2 > 1, latchup may occur.
Once latchup has begun, the only way to stop it is to reduce the current below a critical level,
usually by removing power from the circuit.

Preventing latchup:
1). Reduce the gain product b1 x b1
move n-well and n+ source/drain farther apart increases width of the base of Q2 and reduces
gain beta2 > also reduces circuit density
buried n+ layer in well reduces gain of Q1
2). Reduce the well and substrate resistances, producing lower voltage drops
higher substrate doping level reduces Rsub
reduce Rwell by making low resistance contact to GND
guard rings around p- and/or n-well, with frequent contacts to the rings, reduces the parasitic
resistances.
94. FSM sequence for 1011
Ans:

95. Explain : Setup and Hold time

Ans: Setup Time:
The time required for the input data to be stable before the triggering clock edge.
So, Set-up check establishes that the path is fast enough for the desired clock frequency.

Hold Time:
The time required for the data to remain stable after the triggering clock edge.
So, hold check ensures that the path is not too fast so that data is not passed through.

How to remove
Setup & Hold
violations:
To solve setup violation
1. By optimizing and restructuring the combinational logic between the flops of design. In
big designs, we dont do this by ourselves, generally tool does this for us. And what are the
ways that tool follows for the same? We'll discuss that in next post.

2. By using Tweak flops to offer less setup delay. Since, Tweak launch-flop have better
slew at the clock pin and this makes CK->Q of launch flop faster, so that it helps in fixing
setup violations.
3. By using Useful- skews.
To solve Hold Violations
1. By adding delay/buffer cell. Since the simple buffer offers less delay, so we use special
Delay cells whose functionality remains same, i.e. Y=A, but with more delay.
2. By providing delay to the launch flop clock.
3. Where the hold time requirement is huge, we can use Lock-up Latches also.
96. Asynchronous D-FF veilog code
Ans : module dff_async_reset (data , clk ,reset,q);
input data, clk, reset ;
output q;
reg q;
always @ ( posedge clk or negedge reset)
if (~reset) begin
q <= 1'b0;
end else begin
q <= data;
end
endmodule
97. Synthesis steps in detail.
Ans : Synthesis is the process to convert RTL in to GATE level netlist.
(1)Translation
(2)Mapping
(3)Optimization
98. How many times DFT comes into the picture and when?
Ans : DFT will be done after synthesis and after manufacturing.
98. I/p of logic synthesis.
Ans: -----Requires inputs:
(1) RTL files.
(2) Synopsys Constraints file ,Design constraints file.
(3) Technology specific libraries.
-----Its Output :
Gate level netlist which is technology dependent.

99. What is.sdc and .sdf files?

Ans: The SDF file extension can be used as a schedule data file, a source definition file, a standard
data format, a standard delay format, and a system data format.
The SDF file extension is a data file with a fixed length of ASCII, when it works as a system data
format file. But when it functions as the standard delay format, the SDF file extension becomes an
OVI standard and it is used to represent and interpret the different timing of data, which will be
used for the process of electronic designing.
SDF - Standard Delay Format
Used to convey the timing information of a design after implementation (it can be generated at all
of above steps). This is what says whats the delay at each cell, net, node. This is exported to do the
simulation of design and to find if the design is operating at the Frequency without any setup/hold
violations.
Design Compiler generates SDC files (Synopsys Design Constraints)
It is clear from the replies here that many of you have not done a real chip design. You do need a
"seed" sdc file which defines clocks and input/output delays for the synthesizer. It should also have
false paths, multicycle paths, and generated clocks. After synthesis you generate a NEW sdc from
DC, you get many new paths generated, lots of nets. You run Primetime on this netlist and read in
that sdc. After all the false timing paths have been analyzed and constraints are updated, you write a
new sdc which is given to PnR. Primetime is run several times: post-synth, after FloorPlanning &
Global PnR, after CTS & Detailed Route, and after Parasitic extraction.
SDC - Synopsys Design Constraints
This file is used for all implementation tools starting from synthesis, timing analysis,
place&route,dft,fpga..etc. This is very important file to ensure proper operation of your design,
fpga, silicon.
100. What's the difference between the target library to the link library in Synopsys DC
setup?
Ans :link_library: is the library you use components from
target_library: is the library you synthesise to
If RAM or PLL is included it will be in link_library and not the target_library.
101. linux cmds:
Ans : (1) awk
(2) grep
(3)find
(4)sed
(5)shutdown
102. DFT scan_chain,scan_reordering
What are scan chains: Scan chains are the elements in scan-based designs that are used to shift-in
and shift-out test data. A scan chain is formed by a number of flops connected back to back in a
chain with the output of one flop connected to another. The input of first flop is connected to the
input pin of the chip (called scan-in) from where scan data is fed. The output of the last flop is
connected to the output pin of the chip (called scan-out) which is used to take the shifted data out.
The figure below shows a scan chain.

103. Scan Chain Reordering:scan chain reordering is a process which is done in the physical
design to optimise the congestion while doing placement. When we do scan Stitching , we do not
have, resistor which are placed far from each other but getting stitched in same scan chain. Also
they may not be having any valid paths between them,functionally.hence physical design tool ,has
to route between these two far away FlipFlop just for scan purpose.But with scan reordering, the
physical design toolreordering the resistors in the chain bsed on the placement of them to reduce the
wire length.
104.From how many ways we can Extract perticular string from file?
Using linux command line
awk
sed
Using perl scripting
Split your report from : and put it into array
now apply regular expression for string which you want to find
print that element
TCL scripting
As I said split your file with repeatation character and make list
Apply regx and find string
print
105. What happen if we swap nmos amd pmos in circuit?
first if we swap nmos and pmos than we will not get exact 5v at output side.
second it will work as an inverter
From this we also know about why pmos pass strong 1 and nmos pass strong 0.

106. Design flow of design vision Synhesis tool?

107. Tell me in brief about Constrains?

Design Rule Constraints

Design rule constraints reflect technology-specific restrictions your design must meet in
order to function as intended. Design rules constrain the nets of a design but are associated
with the pins of cells from a technology library. Most technology libraries specify default
design rules. Design Compiler cannot violate design rule constraints, even if it means
violating optimization constraints (delay and area goals). You can apply more restrictive
design rules, but you cannot apply less restrictive ones.
Optimization Constraints
Optimization constraints represent speed and area design goals and restrictions that you
want but that might not be crucial to the operation of a design. Speed (timing) constraints
have higher priority than area.
The optimization constraints comprise
Timing constraints (performance and speed)
Input and output delays (synchronous paths)
Minimum and maximum delay (asynchronous paths)
Maximum area (number of gates)
108.What is Stuck at fault and how it came
stuck at fault Aries with many reason like parasitic effect , short circuit with Vcc or GND,
glitches , human error etc.
when any net or pin is fix at some constant voltage then it is called stuck at fault.
109. There is difference in link library and target libraries than why we give both libraries
same in design vision tool ? Why do not merge that libraries?
110.What is Finfet ?
FinFET, also known as Fin Field Effect Transistor, is a type of non-planar or "3D" transistor used
in the design of modern processors. As in earlier, planar designs, it is built on an SOI (silicon on
insulator) substrate.

The FinFET technology is a technological breakthrough in recent years. It redefined the entire
chipset industry with newly implemented 3D transistors. Ok..here again, what is 3D transistor? The
traditional planar transistors contain Source and Drain parts, which separated by High K-Dielectric
surface. The entire power flow goes through Dielectric surface gate only. The 3D transistor drain

part raised like Fin structure in FinFET transistors, so these transistors are called FinFETs. Usually,
this kind of protruding parts will allow power to pass through all three parts at the same time. Also,
it will allow multiple transistors to share a common gate and common contacts so the ultimate
power supply consumption will significantly be reduced. Ok , so I will try to put it in simple words.
FinFET technology will allow chipset makers to build ultra-powerful processors, which only take a
little power when compared to traditional planar transistors.
111. huzaifa_ab.*/-_kapasi--Detect a pattern like this.

Ans. [w\]+\_ab\.\*\/\-\_[w\]+.
112.huzaifa.txt and abc.txt which contains word huzaifa.If we write egrep -r huzaifa.txt then
what it returns?

Ans. abc.txt:huzaifa
113.To print multiples of 5 till 10 using shell scripting

Ans. N=5
i=1
while [$i -lt 11]
do
echo " $n x $i = `expr $n \* $i`"
i=`expr $i + 1`
done
114. Display hashes according to key values

Ans.
foreach my $name (sort keys %planets) {
printf "%-8s %s\n", $name, $planets{$name};
}
115. Different methods to find the length of array

Ans.

@length = $#array1.
print scalar(@array1)
$length = @array

116. What is sensitivity list?what if we specify & for all the parameters inside it?

Ans.

It is the no. of parameters which are specified while triggering a block.

If any of the parameters specified in the sensitivity list changes then the block gets executed
again.
If we specify & then if all the parameters changes then only the block gets triggered.

117. Why we need to store the output values as reg?what if the output is not driving any load?

Ans.

Because in the always block it is not continuous assignment thus until the block is triggered
again we need to store the output values thus reg is required to be defined for every output
port.
If output is not driving any load then it will be floating,thus in that case also we need to store
it as reg.

118. Example related to blocking and non-blocking

Ans.

Initially a =3,b=5,c=8;
a=b;
b<= c;
c = a;
the output will be a=5, c= 5, b= 8;

119. Why delays are not synthesizable?

Ans.9 Because there is no hardware to describe delay.

120. Why we write ports in TB and in design file as opposite of each other?

Ans.10 Because TB is the top level module which is driving the DUT thus the ports that are input
for DUT are outputs of TB actually and the same goes for input ports.Thus we write ports as
opposite of each other in TB and DUT.
121.Cmos structure and characteristics of output voltage
Ans.

CMOS structure

Id vs Vd characteristics
122. What is threshold voltage?

Ans. It is the minimum voltage required to be applied to the device to turn it ON.
123.What is the impact of change in gate voltage on the device?

Ans. If the gate voltage decreases then the no. of electrons in case of nmos are less attracted as a
result weak channel is formed,thus current from drain to source will be less.

124. What is synthesis?

Ans. It is the process of converting RTL design to Gate level netlist so that it can be further done
for physical design of the required design.
125. What are the contents of .sdc files?

Ans. It describes the default values for input delay,output delay,clock latency,max transition,setting
input and output ports,multicycle path,etc.
126. Process of synthesis?

Ans. First the design file is read and then before compile it maps acc. To Gtech lib. And design
ware lib. And then constraints are given and then afte compilation it is mapped acc. To tech.
Lib. And then various reports are generated and checked whether DRC are violated or not.If
violated then constraints are changed and then reports are again generated until all DRC are
fixed.
127.What is dft why we need it and how it is done?

Ans. It is used to test the manufactured hardware.

We need it because we don't have any access to hardware if the fault is generated during
manufacturing or not.Thus to have controlability and observability at the top level we need it.
It is done by various methods such as Scan chain,ATPG,BIST,JTAG,etc.
128. Difference between mealy and moore machine
Ans.

129. Difference between windows and linux

Ans. Linux is open source while windows is not.

We have access to source code in linux while in windows we don't

We can modify acc. To our own in linux while in windows we don't.
130. Why linux is virus free?
Ans. In linux to install anything we need to go to root direc. Which requires password thus any

guest(virus) will not have any access to the system thus it is virus free while in windows to
install anything we need to run as administrator which does not require any password thus it
is not virus free.

131. Multiplication Table of 5.

Ans:
N=5
i=1
while [$i -lt 11]
do
echo " $n x $i = `expr $n \* $i`"
i=`expr $i + 1`
done
132. ls lrt

Ans:
ls for list command
l -list
r- reverse
t- time
133. Faviourite command of linux.

Ans:
cd ls pwd etc.
134. Command to check in which directory we are in vi editor

Ans:
pwd
135. How to go in previous directory using command

Ans:
cd 136. Find the word from zip file

Ans:
using zgrep command
137. Syntex grep command.

Ans:
grep 'word' inputfile name
138. Difference in hash and array.

Ans:
Arrays are ordered, integer-indexed collections of any object. Array indexing starts at 0, as in C or
Java. A negative index is assumed to be relative to the end of the arraythat is, an index of -1
indicates the last element of the array, -2 is the next to last element in the array, and so on.
A Hash is a collection of key-value pairs. It is similar to an Array, except that indexing is done via
arbitrary keys of any object type, not an integer index. Hashes enumerate their values in the order
that the corresponding keys were inserted.
Hashes have a default value that is returned when accessing keys that do not exist in the hash. By
default, that value is nil

139. If I print 5 times hash and five times array what will be the difference in the output

Ans:
thre will be no change in output.
140. Sorting of a hash in alphabetic orde

Ans:
foreach my $name (sort keys %planets) {
printf "%-8s %s\n", $name, $planets{$name};
}
this syntax will give sorted values.
141. Difference in a and $a

Ans:
a is used to define the variable and $a will be used to fetch the value which is stored in that variable.
142. 3 ways to print how many values are there in any array.

Ans:
my @arr = (2);
print scalar @arr;
my $arrSize = @arr;
print $arrSize;
my @planets = qw(mercury venus earth mars jupiter);
my $size = $#planets + 1;
print "$size\n";
143. Difference of mealy and moore.

Ans:

144. What chomp does.

Ans:
chomp removes the last new line character.

145. What is asynchronous and synchronous reset.

Ans:
Synchronous Reset
A synchronous reset signal will only affect or reset the state of the flip-flop on the active edge of the
clock. The reset signal is applied as is any other input to the state machine.
Asynchronous Reset
An asynchronous reset will affect or reset the state of the flip-flop asynchronously i.e. no matter
what the clock signal is. This is considered as high priority signal and system reset happens as soon
as the reset assertion is detected.
146. How cmos characteristics and when pinch off occure Id equation at pinchoff.

Ans:
Pinch of will take place when vds and more then vdsat. And very small amount of current will pass.

147. What is body effect.

Ans:
For simplicity , it is assumed that the source and the bulk of the transistor are tied together , but in
reality it is not.
It is one of the Second-Order effects in analysis of a mosfet.
The voltage difference between the source and bulk(substrate) (Vsb) affects Vth of transistor.
And in order to see the body effect in transistor you have to add a current source in the drain of the
small signal model of a mosfet.it is parallel with ro resistor and gm*Vin current source. and its
value is gmb*Vbs.
148. Application of Shebang line in shell scripting

Ans:
The #! syntax used in scripts to indicate an interpreter for execution under UNIX / Linux operating
systems.
149. Explain nand2 or nor2 cmos.

Ans:

150. Optimization techniques in logic Synthesis.

Ans:
Architectural optimization
arithmetic
resource sharing
design ware implementation
gate level optimization
area optimization
time optimization
logic optimization
structuring
flattening

151. Constraints in logic synthesis.

Ans:
Design rule constraints
max tansition
max/min capacitance
fanout
Optimization constraints
max area
max timing
152. Types of leakage current in CMOS explain all currents.

Ans:
Subthreshold conduction when the transistors are off
Tunnelling current through gate oxide
Leakage current through reverse-biased diodes
153. Initial block is synthesizable or not?

Ans:
It is not synthesizable.