Synthesis of a Traffic Light Sequence Circuit

Adrian B. Abiera, Dino F. Ligutan, Carl B. Matulac, Daniel G. Navarrete, and Marc C. Serzo
Abstract - In order to fully understand the topics covered in the
course logcist, a project showing the application of said topics
was necessary to make. In creating a traffic light sequence in an
intersection using integrated circuit chips, 7 segment LED
display and other passive elements in the circuit, truth tables,
state tables, state diagrams and Karnaugh maps (topics that were
covered during the term) were then used to analyze the results.
Index Termscombinational circuits; digital circuits; flipflops; logic circuits; logic gates; sequential circuits
Figure 2 - 2 The 555 timer and its pin assignments
I.

INTRODUCTION

The first few chapters of the paper discusses the theory

behind logic circuits including the functions of commercially
available integrated circuits used for logic circuits. It is
followed by the discussion of the synthesis of a traffic light
sequential circuit by means of all the tools of Boolean algebra
and by analysis of state transition tables and diagrams. The
circuits obtained then are put into test by means of a
simulation software using Multisim. Finally, the simulation
results obtained are to be discussed for analysis.
II. THEORETICAL FRAMEWORK

When operating in monostable the 555 timer acts as a one-shot

monostable multivibrator used as a pulse generator circuit.
The multivibrator circuit has only one stable state and
produces a single output pulse when triggered externally.
During Bistable mode, the 555 operates as a flip-flop when its
DIS pin is not connected and no capacitor is used. Lastly
Astable mode, which was used in this project where the 555
timer operates as an oscillator. The output from the 555 timer
is a continuous pulse waveform of a frequency that is
dependent on the values of two resistors and capacitors used in
its circuit.

A. Boolean algebra
Boolean algebra is mathematics specifically used to
manipulate logic expressions in a more concise form. Logic
expressions can be manipulated with the use of theorems that
create or comprehend optimized switching, digital and
computer circuits.

Figure 2 - 3 The 555 timer circuit in Astable mode

During astable mode the 555 timer generates pulse

waveforms, the frequency of the pulse depends on the values
of R1, R2 and C. given by the equation:

f=
Figure 2 - 1 Examples

1
ln ( 2) C ( R 1+2 R 2)

of Boolean algebra Theorems

There are many established methods in order to simplify

Boolean expressions such as K-mapping, making use of a
truth table which are used to minimize the cost in creating
logic circuits.
B. 555 IC timer
The NE555 timer IC is an eight pin dip package IC which
performs varying tasks that involves timing in electronic
circuits. The 555 timer has three operating modes:
Monostable, Astable, and Bistable.

C. Multiplexer 74LS153
A multiplexer is a device that selects one of several analog
inputs and outputs the input into a single line. Having an input
of 2n and having select lines n. A multiplexer IC 74LS153 was
used in this project.

Figure 2 - 4 a 74LS153 MUX IC connection diagram

This IC Permits multiplexing from N lines to 1 line, performs

at parallel-to-serial conversion, High fan-out, low impedance,
totem pole outputs. It averages a propagation delay of 14
nanoseconds from data, 19 nanoseconds from strobe and 22
nanoseconds from select.
D. Decoder
A 1-of-n binary decoder has n output bits, and the integer
inputs bits serve as the "address" or bit number of the output
bit that is to be activated. When a binary decoder
receives n inputs it activates one and only one of its 2n outputs
based on that input with all other outputs deactivated. A 2-to4 binary decoders were used in this project.

Figure 2 - 6 the internal diagram of HCF4556B

Figure 7 sees the HCF4556B having two decoders which have

inputs (A&B) and four outputs (Q0 to Q4).

Figure 2 - 7 the truth table for HCF4556B

E. JK Flip-Flop
A JK flip-flop is said to be a refinement of the SR flip-flop, it
may be due to having similar inputs of an SR flip-flop, where
J (set) and K (reset). It was named after the Texas Instrument
engineer inventor Jack Kilby.

Figure 2 - 5 a block diagram of a 2-to-4 Decoder

This project made use of a Decoder IC HCF4556, which

comprises of two 2-to4 decoders. It features a monolithic
integrated circuit fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages. The
HCF4556B is a dual 1 of 4 decoder/ de-multiplexer. Each
decoder has two select inputs (A and B), an Enable input (E),
and four mutually exclusive outputs. On the HCF4556B the
outputs are low on select. When the Enable input is high, the
outputs is high regardless of the state of the select inputs A and
B.
Figure 2 - 8 JK flip-flop Logic diagram, Characteristic Table and
Equation

F.

4-bit binary counter 74LS93

Figure 2-12 BCD up/down counter internal circuit

Figure 2 - 9 74LS93 IC binary Counter

Figure 2-13 BCD up/down counter Function table

Figure 2 - 10 74LS92 IC excitation table

G. BCD up-down decade counter 74LS192

Figure 2 - BCD up/down counter pin config. , Logic symbol, and

IEC logic symbol

H. 7-segment LED decoder/driver 74LS47

Third flow

Fourth flow

Fig. 3-1. The order of traffic flow sequence. After the fourth flow, the first
flow follows and the sequence repeats.

Figure 2 13 74LS47 circuit diagram

Figure 2 13 74LS47 Transition table

III. SEQUENTIAL CIRCUIT SYNTHESIS

The design begins by considering the structure of the traffic
light sequence and the duration (in seconds) of each traffic
light state. The structure of the sequence is as follows: in a
four-way road intersection, the straight traffic flow of a pair of
opposite roads is considered first, followed by the leftward
traffic flow for the same pair. The straight flow must be
stopped before the leftward flow commences. After the
leftward traffic flow of the first pair of opposite roads, the
straight traffic flow of another pair of opposite roads follows,
then also followed by the leftward traffic flow for the same
pair. After the leftward traffic flow for second pair of opposite
roads, the straight traffic flow follows for the first pair of
opposite roads and the sequence repeats.

First flow

Second flow

For each flow, there are three traffic light states: green,
yellow and red states. For convenience, the duration of the
yellow state is considered as the unit length of time in the
design of traffic light sequential circuit since it has the shortest
duration. The duration of green state was decided to be thrice
the duration of yellow state for convenience in circuit design.
The duration of red state follows from the duration of yellow
and green states and will be determined later on. Furthermore,
it was decided that the duration of the yellow state shall be 4
seconds from which follows that the duration of the green
state be 12 seconds again, these values were chosen for
simplicity of circuit design. A pair of 7-segment display for
countdown for each traffic light panel will indicate the number
of seconds left for the current state before the transition to the
next state will occur. It too has its own sequential circuit to
consider that must be synchronized with the sequential circuit
of the traffic light. To make things clear, we will divide the
discussion of synthesis of sequential circuits into two: one for
the traffic light sequence and the other for the 7-segment
display countdown timer. These circuits will be combined later
on.
A. Traffic Light Sequential Circuit
For each flow, there are three traffic light states: green,
yellow and red states. The sequence goes as follows: green
state, followed by yellow state then by the red state. The red
state is followed by the green state and the sequence repeats.
However, since the traffic flow sequence also repeats, we must
consider the sequences of all traffic light panels for all roads
so that we can determine which panels are in green, yellow or
red state at a given moment. Let us first denote the two pairs
of opposite roads as 1 and 2, the straight and leftward flow by
S and L and the green, yellow and red states as G, Y and R
respectively. A sequence of symbols such as GS1 refers to the
green state for straight flow for the first pair of opposite roads.
Similarly, YL2 refers to the yellow state for leftward flow for
the second pair of opposite roads. Now with the notation set
and following the discussion earlier in this chapter, the
succession of traffic light states goes as follows:

G
2
L
S
Y
1

Fig. 3-2. The state diagram for the sequence of traffic light states for all
panels.

Note that the red state was not included in Fig.3-2. What we
are showing in the state diagram is the succession of states by
looking at all panels. If one will look at a panel, the state
diagram goes as follows:

G
R
x
Y

Fig. 3-3. The state diagram for the sequence of traffic light states for one
panel.

The red state for each panel occurs after the yellow state of
that panel until it goes into green state again. Obviously, the
red state has the longest duration of all the states in a panel.
Now, if we denote GS1 as S0, YS1 as S1 and so on, we will
come up with a state table like so:

different duration, depending on the current state and (2)

maintain equal duration of each state but add same states
corresponding to green state. Adding same states will make
the duration of those state longer, since they are one; only
combinational circuits will ensure that they are for the green
state. Despite the redundancy of states, the synthesis will be
far simpler than the first option.
In this regard, we shall add two more states for all the green
states in Fig. 3-2. This implies that the duration of the green
state would be thrice as long as the duration of the yellow state
this is one of the reasons why it was decided that the length
of green state be as thrice as long as the yellow state. Another
reason is that the addition of these states will make 16 states in
total a power of 2 where 4 flip-flops would suit best the
design. Fig. 3-4 shows the modified state diagram.
Now, the new states will be designated by symbols S0
through S15 with S0 being the first GS1 state. We will employ
the T flip-flop for the design. To begin with, the states are to
be converted to binary designation for us to be able to create a
state transition table shown in Table 3-2. The flip-flops are
designated by A, B, C and D with A being the most significant
bit. The flip-flop inputs are obtained from the present state, the
next state and the T flip-flop excitation table. Based from the
flip-flop inputs columns, we will determine the combinational
circuit necessary for each inputs by using Karnaugh map.
Based from Fig. 3-5, the input equation for flip-flop D is
T D =1 ; for flip-flop C is T C =D ; for flip-flop B is

T B=CD ; and for flip-flop A is

T A =BCD . The

synthesized circuit based from these equations is shown on

Fig.
1 3-6.
G
2
L
Y
S

TABLE 3-1
STATE TABLE FOR EACH PANEL

Stat
e
GS1
YS1
RS1
GL1
YL1
RL1
GS2
YS2
RS2
GL2
YL2
RL2

S0

S1

S2

S3

S4

S5

S6

S7

1
0
0
0
0
1
0
0
1
0
0
1

0
1
0
0
0
1
0
0
1
0
0
1

0
0
1
1
0
0
0
0
1
0
0
1

0
0
1
0
1
0
0
0
1
0
0
1

0
0
1
0
0
1
1
0
0
0
0
1

0
0
1
0
0
1
0
1
0
0
0
1

0
0
1
0
0
1
0
0
1
1
0
0

0
0
1
0
0
1
0
0
1
0
1
0

Here, the rows in the first column indicate the state for each
panel. The 1 indicates that the row is the active state for a
given column state and a 0 indicates that the row is not the
active state for a given column state for a panel.
However, employing the state diagram in Fig. 3-2 entails
that the duration of the green state is the same as yellow state.
In order to make the green state longer, there are two options:
(1) design the circuit such that the different states have

Fig. 3-4. The final state diagram as the basis for circuit synthesis.
TABLE 3-2
STATE TRANSITION TABLE USING T FLIP-FLOPS
Stat
e
No.

Present State
A B C D

Next State
A B C D

Flip-Flop Inputs
TA

TB

TC

TD

S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0

0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0

0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1

0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

TD

00

01

11

10

TC

00

01

11

10

00
01
11
10

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

00
01
11
10

0
0
0
0

1
1
1
1

1
1
1
1

0
0
0
0

00
01
11
10
TA
00
00
0
0
1
0
01
01
0
0
1
0
11
11
0
0
1
0
10
10
0
0
1
0
Fig. 3-5. Karnaugh maps for T flip-flop inputs.

00

01

11

10

0
0
0
0

0
0
0
0

0
1
1
0

0
0
0
0

TB

Fig. 3-6. The synthesized sequential circuit using T flip-flops.

However, there is a commercially available IC that

functions the same as the circuit in Fig. 3-6 and is called the 4bit binary ripple counter 74LS93. 74LS93 will be used for
simulation.

Let us now develop the equations pertaining to traffic light

states for each panels. The truth table for the traffic light state
for straight and leftward flow for pair of opposite roads 1 is
shown on Table 3-3.
TABLE 3-3
TRUTH TABLE FOR TRAFFIC LIGHT STATE FOR OPPOSITE ROADS 1
Stat
e
No.

S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15

A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Present State
B
C
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

G
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0

S1
Y
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0

R
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1

G
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0

L1
Y
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0

R
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1

A look at the K-map for GS1 from Fig. 3-7 reveals that its
equation is given by
GS1=A ' B' C' + A ' B ' D ' .
Similarly, YS 1= A ' B ' CD and RS 1= A+ B . For
the
leftward
flow:
GL 1= A' B C ' + A ' BD ' ,
YL1= A ' BCD , and RL1= A+ B ' .
By similar fashion, we will also develop the equations for
the
GS1

00

01

11

10

YS1

00

01

11

10

00
01
11
10

1
0
0
0

1
0
0
0

0
0
0
0

1
0
0
0

00
01
11
10

0
0
0
0

0
0
0
0

1
0
0
0

0
0
0
0

RS1

00

01

11

10

GL
1

00

01

11

10

00
01
11
10

0
1
1
1

0
1
1
1

0
1
1
1

0
1
1
1

00
01
11
10

0
1
0
0

0
1
0
0

0
0
0
0

0
1
0
0

YL
1

00

01

11

10

RL1

00

01

11

10

00
00
0
0
0
0
1
1
1
01
01
0
0
1
0
0
0
0
11
11
0
0
0
0
1
1
1
10
10
0
0
0
0
1
1
1
Fig. 3-7. Karnaugh maps for traffic light states for opposite roads 1.

1
0
1
1

second pair of opposite roads. Shown below is the truth table

for such traffic light states.

TABLE 3-4
TRUTH TABLE FOR TRAFFIC LIGHT STATE FOR OPPOSITE ROADS 2
Stat
e
No.

S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15

A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Present State
B
C
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

G
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0

S2
Y
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0

R
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1

G
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0

L2
Y
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1

Fig. 3-8. Karnaugh maps for traffic light states for opposite roads 2.

states,
R
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0

A look at the K-map for GS2 from Fig. 3-8 reveals that its
equation is given by
GS 2= A B ' C' + AB' D ' .
Similarly, YS 2= AB ' CD and RS 2= A '+ B . For
'
the
leftward
flow:
GL 2= ABC + ABD ' ,
YL2=ABCD , and RL2= A ' + B ' .
Now that we have completed the set of traffic light state
equations, one may go ahead and implement them directly.
However, these equations can be simplified further by
observing several patterns, thus making the implementation
even simpler.
To begin with, let us factor out the common terms in GS1,
giving
us
Similarly,
GS1=A ' B' (C '+ D ' ) .

GL 1= A' B ( C ' + D' ) . Continuing in the same fashion

for the rest of the green
GS2

00

01

11

10

YS2

00

01

11

10

00
01
11
10

0
0
0
1

0
0
0
1

0
0
0
0

0
0
0
1

00
01
11
10

0
0
0
0

0
0
0
0

0
0
0
1

0
0
0
0

RS2

00

01

11

10

GL
2

00

01

11

10

00
01
11
10

1
1
1
0

1
1
1
0

1
1
1
0

1
1
1
0

00
01
11
10

0
0
1
0

0
0
1
0

0
0
0
0

0
0
1
0

YL
2

00

01

11

10

RL2

00

01

11

10

00
01
11
10

0
0
0
0

0
0
0
0

0
0
1
0

0
0
0
0

00
01
11
10

1
1
0
1

1
1
0
1

1
1
0
1

1
1
0
1

we

notice

G xx =xx ( C

'

that the equation has the form

+ D ' ) . The same pattern can be observed

for the yellow states Y xx =xx CD . Only the two most

significant bits are changed as we move from panel to panel.
Also note that the equations of the green and yellow states are
complementary in the same panel so that G+Y =1 . In
fact, if we use De Morgans theorem on the equation of the
green states, we could write
G xx =xx ( CD ) ' , from
which it is obvious that the least two significant bits are just
the complement of the yellow states least two significant bits
namely CD. Now, instead of using two 3-input AND gates
and a 2-input OR gate for each green state, we could have
used a single 2-input NAND gate for all the green states.
Similarly, we could have used a single 2-input AND gates for
all yellow states. We will deal with the red states later on.
One may argue that the proposed simplification would
result in all green states simultaneously active at all panels; the
same case for the yellow states. What we will do now is to
analyze the two most significant bits, which will now
determine the panel whose green or yellow state is active. The
table below shows which panel is active as a function of the
two most significant bits A and B.
TABLE 3-5
TRUTH TABLE FOR ACTIVE PANELS AS A FUNCTION OF A AND B

A
0
0
1
1

B
0
1
0
1

S1
1
0
0
0

L1
0
1
0
0

S2
0
0
1
0

L2
0
0
0
1

As discussed in Chapter 2, the truth table is reminiscent of a

2-to-4 decoder circuit. Essentially, the decoder acts as a
selector that determines which panel will have an active green
or yellow state. The red state will then be just the complement
of the selector bit for each panel.
However, we must make adjustments so that we may be
able to implement it by using commercially available ICs. One
such IC is the dual 2-to-4 decoder CD4556 whose output is
active LOW. This means that all the outputs of the decoder
must be complemented to obtain the truth table shown in Table
3-5. In this regard, we decided to create a logic circuit out of
transistors to take advantage of this characteristics and to
minimize the costs. The transistorized logic circuit behind
each panel is shown below:

Fig. 3-9. Transistorized logic circuit behind each traffic light panel.

The transistorized logic circuit provides several advantages

than using ICs: first is the reduced cost for implementing the
logic circuit for each traffic light panel, second is that the
circuit will provide larger current handling capability than if
ICs were used and third is that it requires less wiring than
using ICs. The transistorized circuit also allows us to use the
concept of multiplexing. The circuits truth table is shown on
Table 3-6.
TABLE 3-6
TRUTH TABLE OF TRANSISTORIZED LOGIC CIRCUIT FOR EACH TRAFFIC
LIGHT PANEL

SEL
0
0
0
0
1

Y
0
0
1
1
X

G
0
1
0
1
X

Red
0
0
0
0
1

Yellow
0
0
1
1
0

Green
0
1
0
1
0

Integrating all the synthesized circuits into one, we will

have more or less the circuit shown on Fig. 3-10. Note that for
each panel, the LED lights are from red to yellow to green
from up to down. For each set, the panels are arranged from
S1 to L1 to S2 to L2 from up to down. For the yellow states,
the NAND gate was used as an inverter in order to utilize the
excess gates that comes with the commercially available IC,
instead of using a different IC such as the hex inverter.
As a side note, the state diagram found in Fig. 3.4 was
designed to take advantage of the 74LS93 binary counter. Not
including the timer IC, the traffic light sequence circuit
requires just three integrated circuits to perform its function.

Fig. 3-10.
sequence.

The synthesized sequential circuit for the traffic light state

B. 7-segment Display Logic Circuit

For the 7-segment display, two ICs will be necessary: the 7segment driver 74LS47 and the presettable BCD/decade
counter 74LS192. The interconnection between these ICs and
the display are straightforward; the problem that only remains
is to determine the right countdown time to display and when
the counter should be reloaded. What we will consider here is
the combinational circuit that will perform the requirements.
The state transitions can be based from the traffic light
sequence with little modifications to be made on Fig. 3-10
later on.
From this chapters introduction, we have set that the
duration of the green state must be 12 seconds followed by the
yellow state whose duration is 4 seconds. Now, we would like
to clarify the physical setup of these traffic light LEDs and the
7-segment display. A physical panel (not the panel that was
referred in the previous section) is shown in the figure below:

However, since the number of states is just 4, the required

number of flip-flops is just 2. Following the procedure as
discussed in the previous section, the synthesized circuit is
shown below:

Fig. 3-11. The physical panel setup for the traffic light LEDs and 7-segment
display

Note that the set of red, yellow and green states on the right
side is for the straight flow while on the left side is for the
leftward flow. Based from the considerations stated earlier,
Table 3-7 shows the sequence of countdown that is loaded to
7-segment display whenever a light state transition occurs.
TABLE 3-7
LOADED COUNTDOWN SEQUENCE FOR A 7-SEGMENT DISPLAY IN OPPOSITE
ROADS 1

State
GS1
YS1
GL1
YL1
Rx1

Starting Countdown Display

12
4
12
4
32

Fig. 3-12. The 4-state sequential circuit to replace the clock in 74LS93.

In effect, the total number of states once the circuit in Fig.

3-12 is to be connected becomes 26=64 states. The
figure below shows how the synthesized circuit from Fig. 3-12
is connected to the clock input of 74LS93 by means of a
NAND gate.

The time displayed for the duration of the red state is

calculated by adding the duration of green and yellow states
for each side of the physical panel, so that
12+4 +12+ 4=32 . The same loaded countdown
sequence applies to the physical panel corresponding to the
opposite road. For the second pair of opposite roads, the table
below shows the sequence of countdown that is loaded to 7segment display whenever a light state transition occurs.
TABLE 3-8
LOADED COUNTDOWN SEQUENCE FOR A 7-SEGMENT DISPLAY IN OPPOSITE
ROADS 2

State
Rx2
GS2
YS2
GL2
YL2

Starting Countdown Display

32
12
4
12
4

Note that the loaded sequence for opposite roads 2 is just

the complement of the opposite roads 1; that is whenever the
traffic light state on opposite roads 1 is not in red state, the
starting countdown display for opposite roads 2 is 32 and vice
versa.
Having stated that the duration of the yellow state is 4
seconds, we must now modify the sequential circuit from the
previous section. The modification is as follows: the clock
input for 74LS93 (from Fig. 3-10) is to be connected to a
sequential circuit so that the transition occurs for every 4
seconds that the clock triggers. The synthesis of the circuit is
essentially the same as discussed in the previous section.

Fig. 3-13. The modified sequential circuit based from Fig. 3-10.

All 64 states shall form the basis of the design of the

combinational circuit that will load the proper timer
countdown display at the right time instants such that the new
countdown will be loaded whenever a light state transition
occurs. The table below shows all the 64 states, the load bit
and the BCD number to be loaded for the digits of the 7segment display for opposite roads 1. Note that the outputs of
the additional 4-state sequential circuit are the least significant
bits.
TABLE 3-9
TRUTH TABLE FOR THE DIGITS OF THE 7-SEGMENT DISPLAY FOR OPPOSITE
ROADS 1

Stat
e
0
1

L1

P13

P12

P11

P10

P03

P02

P01

P00

1
0

0
X

0
X

0
X

1
X

0
X

0
X

1
X

0
X

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58

0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

X
X
X
X
X
X
X
X
X
X
0
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
0
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
0
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
0
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
0
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
1
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
0
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
0
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

59
60
61
62
63

0
0
0
0
0

X
X
X
X
X

X
X
X
X
X

X
X
X
X
X

X
X
X
X
X

X
X
X
X
X

X
X
X
X
X

X
X
X
X
X

X
X
X
X
X

By using logic simplification software, we will find that the

logic equations are as follows:

L1= A' C ' D' E' F ' + B' C' D ' E' F ' + A ' CDE ' F '
P13=0 , P12=0 , P11= A , P10=C '
P03=0 , P02=D , P01=C ' , P00=0
Similarly, applying the same procedure for the 7-segment
display for opposite roads 2 yields the following truth table:
TABLE 3-10
TRUTH TABLE FOR THE DIGITS OF THE 7-SEGMENT DISPLAY FOR OPPOSITE
ROADS 2

Stat
e
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37

L2

P33

P32

P31

P30

P23

P22

P21

P20

1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0

0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X

0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X

1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X

1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X

0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X

0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X

1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X

0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X

38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0

X
X
X
X
X
X
0
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X

X
X
X
X
X
X
0
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X

X
X
X
X
X
X
0
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X

X
X
X
X
X
X
0
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X

X
X
X
X
X
X
0
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X

X
X
X
X
X
X
1
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X

X
X
X
X
X
X
0
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X

X
X
X
X
X
X
0
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X

Again, by using logic simplification software, we will find

that the logic equations are as follows:

L2=B' C ' D' E ' F' + A C ' D' E' F' + ACDE' F '
P33 =0 , P32=0 , P31=A ' , P30=C '
P23=0 , P22=D , P21=C ' , P20=0
Now that all pertinent logic equations were derived, we may
proceed in the design of the combinational circuit. Shown in
Fig. 3-14 is the logic circuit diagram.
Now, instead of connecting all the outputs of 4 74LS192 ICs
into 4 separate 74LS47 ICs, we have decided to use the
74LS153 multiplexer to reduce the costs of buying 3 more
74LS47 IC and thereby reduce the wires that are necessary for
the 8 7-segment LED displays. Since there are 4 different
74LS192 ICs differing in values, it becomes necessary again
to design a 4-state sequential circuit to switch between the 4
different digit values. Accordingly, the second 2-to-4 decoder
of CD4556 IC will be utilized so that the digit is displayed on
the correct 7-segment LED display. The same circuit as in Fig
3-12 will be used as the sequential circuit, but the clock input
is required to have higher frequency than the clock that is
being used for countdown timer. An additional timer may be

Fig. 3-14. The combinational circuit to load the proper countdown timer at
light state transitions.

constructed by several ways, but in order to maximize that all

logic gates are being used up, we decided to construct an
oscillator based from two inverters. The circuit configuration
is called an inverter oscillator and is relatively stable in terms
of frequency and amplitude. The said oscillator shall be used
as a clock input for another set of 2 T flip-flops sequential
circuit. The figure below shows the setup. Note that output T0
is the least significant bit.

Fig. 3-15. The inverter oscillator connected to a 4-state sequential circuit.

IV. SIMULATION AND ANALYSIS

For the traffic light state sequential circuit, it is necessary to
perform Boolean manipulation to the logic equations formed
earlier so that its hardware implementation ready. The logic
diagram in the simulation is already in the form ready for

hardware implementation. The circuit for the traffic light state

sequential circuit together with the modification made for the
7-segment display is shown on Fig. 4-1. Notice that the flipflops that were used where JK flip-flop instead of T flip-flops
because it is commercially available and can reproduce the
same function as the T flip-flop. The timer circuit generator
that was used uses the LM555 timer IC whose resistance and
capacitance values where adjusted to generate a 1 Hz square
waveform output.
The logic analyzer was connected to the output of the 2 JK
flip-flops and the 74LS93 binary counter so that the first
waveform shows the least significant bit and the sixth
waveform shows the most significant bit. The output of the
logic analyzer is shown on Fig. 4-2. The bottom most
waveform shown is the clock waveform. Notice that it has the
highest frequency among all other waveforms. The length of
time that the sequential circuit state repeats is about 64
seconds since there were 26=64 possible states given 6
bits combination.
Let us now look at the transition of the traffic light states.
Fig 4-3 shows six waveforms; the first two are for the yellow
and green states respectively while the last four are for the
output of the HCF4556 decoder. Notice that the waveforms for
green and yellow states are complementary in nature as was
discussed in the previous chapter. The last four waveforms
resembles the inverted logic truth table for a 2-to-4 decoder; it
is inverted because it is the commercially available decoder.
The succession of the last four waveforms corresponds to the
succession of which of the panels will be having an active
green or yellow state at a given instant.
For the combinational circuit, Boolean manipulation is also
necessary because there is no commercially available AND
gate with 5 inputs. In the simulation, the logic equations that
were used for L1 and L2 are as follows:

Fig 4-7. First four waveforms are the outputs for the ones digit
in the 7-segment display situated for the pair of opposite roads
1. The second four waveforms is for the tens digit of the same

L1=[ E+ F + ( A' C' D' + B' C ' D' + A ' CD ) ' ] '
L2=[ E+ F + ( A C D + B C D + ACD ) ' ] '
'

'

'

'

'

which requires 3 3-input AND and 2 3-input NOR gates.

However, the load pin of the 74LS192 IC is active LOW so
that it is necessary to apply a logic inverter first before the
given logic equations is fed into the load pin of all 74LS192
ICs. Fig 4-4 shows the logic circuit of these load pin logic
equations.
The logic analyzer output shown in Fig 4-5 shows the
output waveform for the two load pin equations. The first two
waveforms represent L1 and L2 respectively. The last
two waveforms are the outputs after the filtering RC network.
Physically, the RC network is not necessary it was placed
there to eliminate any logic result delays inherent to the
simulator itself.
Let us now look at the outputs present at the 74LS192 BCD
decimal counters. The circuit shown in Fig 4-6 shows the
interconnection between the 4 74LS192 ICs to 2 74LS153
dual 4-to-1 multiplexers. The multiplexers were used to merge
the four different outputs of BCD decimal counters into one 7segment BCD decoder/driver.
The logic analyzer output for the 74LS192 ICs is shown on

Fig. 4-1. The logic circuit simulation for the traffic light state sequential
circuit.

road pair. In the same manner, the third and fourth four
waveforms belongs to the ones and tens digit in the 7-segment
display situated for the opposite roads 2.

V. CONCLUSION AND RECOMMENDATIONS

Based from the results obtained from the previous chapter, the
simulation results shows that the desired sequential circuit that
was synthesized in the third chapter met the expected timing
diagrams. We are also able to demonstrate the effectiveness of

the circuit is used to eliminate any spurious signals caused by

the delay in the propagation of the result of logic operations
and in fact is inherent to the computers processing power.

Fig. 4-3. The output of the logic analyzer for the traffic light state transitions.
Fig. 4-2. The output of the logic analyzer for the JK flip-flops and 74LS193
binary counter.

the sequential circuit synthesis methods to perform the desired

traffic light state transitions, as well as synthesizing
combinational circuits to properly load the countdown timer
that the 7-segment LED displays must display. However,
several modifications for the circuit in simulation, such as
placing an RC network, may not be necessary when the circuit
is to be implemented in reality. The RC networks present in

We found out that it may be possible to modify the circuit

so that the timer countdown is flexible that is for example
that the duration of a green light state need not be always 12
seconds. For further improvements, it would even be better if
there is an input mechanism for which the circuit would base
the duration of each light state without referring to an
internally set value. It may be achieved by the use of DIP
switches and the use of binary adder logic circuits.

Fig. 4-5. The output of the logic analyzer for the load pin combinational
circuits.

Fig. 4-4. The logic circuit simulation for the combinational circuit used for
loading the proper countdown display at traffic light state transitions.

Fig. 4-6. The logic circuit simulation for the connection between the 74LS192
to 74LS153 ICs into one 74LS47 IC.

Fig. 4-7. The logic circuit simulation for the connection between the 74LS192
to 74LS153 ICs into one 74LS47 IC.

REFERENCES
[1] B. G. Liptak, "Optimized Logic circuit construction," in
Instrument Engineers' Handbook, Fourth Edition, Volume
Two: Process Control and Optimization, CRC Press,
2005, pp. 901-903.
[2] D. B. Pdr, "LECTURE: LOGIC (BOOLEAN)
ALGEBRA AND APPLICATIONS," buda University,
Microelectronics and Technology Institute, 2012-2013.
[3] H. Goyal, "Understanding of IC555 Timer and,"

International Journal of Inventive Engineering and

Sciences (IJIES), vol. 3, no. 2, pp. 2-3, 2015.
[4] a. hassaei, "555 Timer: Astable Mode Circuit," Autodesk,
Inc., 2005. [Online]. Available:
http://www.instructables.com/id/555-Timer/?ALLSTEPS.
[Accessed 12 July 2015].
[5] T. Dean, in Network+ Guide to Networks, Boston, MA,
Cengage Learning, 2009, pp. 82-85.
[6] D. De, "Multiplexers," in Basic Electronics, New Delhi,
Dorling Kindersley, 2010, p. 557.
[7] F. Semiconductor, DM74LS153 Dual 1-of-4 Line Data
Selectors/Multiplexers Data sheets, 2000.
[8] M. M. Mano and M. D. Ciletti, "Chapter 5 : Synchronous
Sequential Logic," in Digital Design, Pearson, 2013, pp.
199-201.