c.

Min width - min

spacingd. Min width +
min spacing

32) In Physical
Design following
step is not there
___.
a. Floorplaningb.
Placementc. Design
Synthesisd. CTS

33) In technology
file if 7 metals are
there then which
metals you will use
for power?
a. Metal1 and
metal2b. Metal3 and
metal4c. Metal5 and
metal6d. Metal6 and
metal7

34) If metal6 and

metal7 are used for
the power in 7 metal
layer process
design then
whichmetals you
will use for clock ?
a. Metal1 and
metal2b. Metal3 and
metal4c. Metal4 and

metal5d. Metal6 and

metal7

35) In a reg to reg

timing
path Tclocktoq
delay is 0.5ns
andTCombo delay
is5ns and Tsetup is
0.5ns then the
clock period should
be ___.

a. 1nsb. 3nsc. 5nsd.

6ns

36) Difference
between Clock
buff/inverters
and normal
buff/inverters is __.
a. Clock buff/inverters
are faster than normal
buff/invertersb. Clock
buff/inverters are

slower than normal

buff/invertersc. Clock
buff/inverters are
having equal rise and
fall times with
high drive strengths
compare to
normalbuff/invertersd.
Normal buff/inverters
are having equal rise
and fall times with

high drive strengths

compare
to Clockbuff/inverters.

37) Which
configuration
is more preferred
duringfloorplaning ?
a. Double back with
flipped rowsb. Double
back with non flipped
rowsc. With channel

spacing between
rows and no double
backd. With channel
spacing between
rows and double back

38) What is the

effect of high drive
strength buffer
when added in long
net ?

a. Delay on the net

increasesb.
Capacitance on the
net increasesc. Delay
on the net
decreasesd.
Resistance on the net
increases.

39) Delay of a cell

depends on which
factors ?
a. Output transition
and input loadb. Input
transition and Output
loadc. Input transition
and Output
transitiond. Input load
and Output Load.

40) After the final

routing
the violations in the
design ___.
a. There can be no
setup, no hold
violationsb. There can
be only
setup violation but no
holdc. There can be
only hold violation not

Setup violationd.
There can be both
violations.

41) Utilisation of the

chip after placement
optimisation will be
___.
a. Constantb.
Decreasec.
Increased. None of
the above

42) What is routing

congestion in the
design?
a. Ratio of required
routing tracks
to available routing
tracksb. Ratio of
available routing
tracks to required
routing tracksc.
Depends on the

routing
layers availabled.
None of the above

43) What are

preroutes in your
design?
a. Power routingb.
Signal routingc.
Power and Signal
routingd. None of the
above.

44) Clock
tree doesn't contain
following cell ___.
a. Clock buffer b.
Clock Inverter c. AOI
celld. None of the
above

Answers:
1)b2)c3)b4)c5)b6)d7)
a8)c9)d10)b11)d12)d

13)b14)c15)b16)a17)
c18)a19)d20)a21)b22
)b23)d24)d25)c26)b2
7)a28)c29)d30)c31)d
32)c33)d34)c35)d36)c
37)a38)c39)b40)d41)
c42)a43)a44)c