FACULTY OF ENGINEERING SCIENCE

DEPARTMENT OF ELECTRICAL ENGINEERING - ESAT/MICAS

DESIGN OF ELECTRONIC CIRCUITS
KASTEELPARK ARENBERG 10 B-3001 LEUVEN

Design of Electronic Circuits [H09J7A]

Exercise Report

Christopher Chare (0610199)

Francesco DellAnna (0609115)

27 Nov 2015

Contents

Contents
1 Introduction

1.1

Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Hand Calculations

3 Optimization

3.1

Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2

Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Layout

5 Analysis

5.1

Unity Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2

Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Conclusion

A Simulation Sweep Results

B DRC and LVS Results

11

Introduction

1
1.1

Introduction
Objectives

This report details the design, optimization and layout of a one-stage OTA. The layout of the OTA is
shown in Figure 1.

VDD

M6

M5

Ibias
Vb
Vin+

VinM1

M2
Vout

M3

M4
CL

Figure 1: Schematic of the One-Stage OTA

1.2

Specifications

The specifications for the OTA are listed in Table 1.

Table 1: OTA Specifications
Parameter
Bandwidth (BW )
Gain (Av )
Imax
CL

Value
0.6 MHz
21 dB
420 A
20 pF

The OTA was optimized towards the following objectives; gain, bandwidth, power, and layout footprint.

Hand Calculations

Hand Calculations

The initial estimation of the channel lengths and widths of M1/2/3/4 in Figure 1 were calculated
using the GBW where,
GBW = Av BW = 10(21/20) 0.6M Hz = 6.7M Hz
Therefore the transconductance gm1 is given by,
gm1 = 2Cout GBW = 2(20pF )(6.7M Hz) = 0.85mS
where Cout = CL + Cpar CL and Cpar 0 for these calculations. Assuming that VGS1 VT = 0.2V
and the transistor is in saturation, the current IDS1 is then,
IDS1 =

gm1 (VGS VT )
(0.85mS)(0.2V )
=
= 84.6A
2
2

Given BW = 0.6M Hz we get,

Rout =

1
2Cout BW

1
= 13.3k
2(20pF )(0.6M Hz)

Assuming the minimum channel length for M1/2 such that L1 = L2 = 45nm then,



1


IDS
1
IDS 1
1
84.6A
84.6A
L3 =

= 23nm
=
VEn
Rout VEp L1
70V /m
13.3k (81V /m)(45nm)
Since the channel length for M3/4 is below the minimum channel length, this initial estimate is not
feasible. In order to achieve feasible channel lengths, the approach was reversed such that the channel
lengths for M1,2,3,4 were specified with IDS modulation to acquire the operating parameters. The
1
main motivation for this approach is due to the fact that AV is dependent on gm1 IDS and Rout IDS
and BW IDS . Thus modulating the channel lengths affects both AV and BW whereas modulating
IDS mainly affects BW and hence GBW . The following equations were scripted in MATLAB in order
to determine the optimal OTA parameters.


1
1
1
Rout = IDS
+
VEp L1 VEn L3
2IDS
VGS V T
1
BW =
2Rout Cout
AV = gm1 Rout
gm1 =

with L1 , L3 45nm and IDS (0, 420A].

It was determined that for minimum channel lengths L1 = L3 = 45nm that IDS 130A for
BW = 0.61M Hz and AV = 24.6dB. Note that the channel lengths are equal, however rDS1 6= rDS3
since they are pMOST and nMOST respectively. As the channel lengths were at their minimum, the
gain AV was fixed and therefore IDS would only vary the BW and hence GBW of the OTA.
The width of the transistors M1/2/3/4 were determined using the following equation,



IDS
2
Wi =
Li
Cox,i
(VGS V T )2
where i = 1, 3. The overall hand calculated specifications are detailed in Table 2.

(1)

Optimization

Table 2: Hand Calculated OTA Specifications

Parameter
Bandwidth (BW )
Gain (Av )
Itail
L1 , L2 , L3 , L4
W1 , W2
W3 , W4

3
3.1

Value
0.61 MHz
24.6 dB
260 A
45nm
1.2 m
0.83 m

Optimization
Setup

Vb
VinDM
2
VDD

Vin+
+
Vout

Ibias
VinCM

VinDM
2

Vin-

VSS
Figure 2: Schematic of the One-Stage OTA Testbench
The schematic in Figure 1 was created in Cadence and simulated in SPECTRE with the following
testbench setup shown in Figure 2. Given that V DD = 1.2V and VIN,CM = 0.6V with VIN,DM = 1V ,
optimization was carried out by setting the channel lengths of M1 (=M2) and M3 (=M4) and Ibias
as variables in ADE L. The channel widths were linked with the length variables via Eqn 1 where
VGS VT = 0.2V and IDS = 0.5Ibias assuming at the current source Ibias Itail since the transistors
are identical. A heuristic method of optimization was performed based on selecting and iteratively
incrementing a fixed parameter while conducting a 2 variable parametric sweep at each iteration in
terms of DC, AC, and transient analysis.
Parametric sweep was conducted with the following variables as shown in Table 3 and evaluated with
respect to the simulated output gains and bandwidths.
Table 3: Parametric Sweep Setup
Parameters
L1 vs. L2 w/ Ibias fixed
L1 vs. Ibias w/ L2 fixed

Sweep Range
[45nm, 500nm] and [45nm, 500nm]
[45nm, 500nm] and [60 A, 420 A]

Optimization

30

Gain 21.1dB

Bandwidth 960MHz

20
10

GBW 10.7MHz

Gain [dB]

-10
-20
-30
-40
-50
-60
-70
10 2

10 4

10 6

10 8

10 10

10 12

10 10

10 12

Frequency [Hz]

(a) Plot gain vs. frequency.

180

160

Phase [deg]

140

120

100

80

60

40
10 2

10 4

10 6

10 8
Frequency [Hz]

(b) Plot of phase vs. frequency.

Figure 3

3.2

Results

The optimized device and performance parameters for the OTA are detailed in Table 4 with corresponding gain and phase outputs in Figure 3. Note that the channel width and lengths for the current
source were determined such that they would have high output impedance and remain in saturation
for the majority of the parametric sweeps.
The GBW being the figure of merit is larger than the required value. However the GBW Itail is
limited such that we can achieve a suitable AV 21dB while minimising the current Itail such that
BW > 0.6M Hz. This ensures the lowest possible power consumption while meeting all the required
specifications. As Imax = 420A a higher GBW can be achieved at the cost of power efficiency.
The results of the parametric sweeps supporting this result are shown in the Appendix along with a
discussion of the simulation.

Layout

Table 4: Parameters for transistors and performance characteristics

Parameters
L1 , L2
W1 , W2
L3 , L4
W3 , W4
L5 , L6
W5 , W6
Ibias
Itail
POT A
BW
AV
Rout

Value
150nm
8 m
150nm
5.6 m
1 m
400 m
260 A
242 A
0.29 mW
960M Hz
21.1dB
7.9k

The discrepancy between the simulated and hand-calculations results from a mismatch between device
constants such as CL (Cpar 6= 0), VEn /VEp , effective Cox and operating points listed in Table 5. E.g.
VGS VT is lower than the hand calculated 0.2 V.
Table 5: Simulated values for DC operating points
Transistor
M1
M2
M3
M4
M5
M6

VG (V)
Vin+
Vin0.60
0.60
0.78
0.78

VD (V)
0.60
0.60
0.60
0.60
0.96
0.78

VS (V)
0.96
0.96
0
0
1.2
1.2

VGS VT (V)
0.12
0.12
0.11
0.11
0.08
0.08

gm (mS)
1.47
1.47
1.33
1.33
5.3
5.6

Saturation
Y
Y
Y
Y
Y
Y

Layout

The layout of the OTA and attached bondpads is shown in Figure 4. The constant current source
pair, differential pair, and the current mirror contain 40, 10, and 10 fingers respectively.
Due to the size of the load capacitor (nMOScap) and bondpads, space is not at a premium so the
footprint of the layout for the differential pair is a neat and simple back-to-back arrangement. All DC
nets are routed with a wider trace, whereas all AC signal lines are routed with the minimum width
(0.06m) and shortest length possible.
If the layout footprint must be minimised as much as possible (i.e. for integration into a larger circuit),
then there are more options to consider. Optimization of the layout could further be improved as all
the transistor pairs have a common source, hence the fingers of each pair can be interleaved to further
reduce the overall parasitic capacitance. The transistor pairs would result in a longer transistor
footprint, however this would fill the wasted blank space and reduce the overall footprint perimeter
by approx. 30%.

Layout

(a) Overall Layout with bondpads visible.

(b) Layout of constant current source, capacitor and differential pair.

Figure 4

(c) Layout of differential pair.

Analysis

Analysis

5.1
5.1.1

Unity Gain
Hand Calculation

An estimation of the second order pole can be given by looking at all the parasitic capacitances
connected in parallel to the gate of M3 and M4.
f nd =

gm2
2.03mS
=
15M Hz
2Cx
2 41f F

where
Cx = Cgs3 + Cgd3 + Cgs4 + Cgd4 + Cgd1 + Cds1
10f F + 1f F + 6f F + 7f F + 11f F + 6f F
= 41f F
5.1.2

Results

Vb

+
VDD

Vout
Ibias

Vin

VSS
Figure 5: Schematic of the unity gain testbench
After the optimization phase the circuit ha been tested applying a unity feedback, the output pin of
the OTA has been connected to the negative input terminal as shown in Figure 5. The positive input
pin has been connected to a voltage source that generates a sine wave ranging from 0 to 1 V. The
obtained gain after the simulation is
From the estimated location of the non dominant pole it can deduced that the OTA has to be further
optimized taking into account also stability issue. To guarantee stability the fnd > 3 GBW and in
our case the fnd 15M Hz.

5.2

Slew Rate

From the obtained parameters after the optimization phase a rough approximation of the slew rate
can be given.
Ibias
260A
SR =

= 13V /ms
C
21pF
The slew rate in the hand calculations is slightly overestimated because all the parasitics capacitances
are not taken into account and also the Ibias is smaller. The measured results obtained looking at the

Conclusion

15

10

Gain [dB]

-5

-10

-15

-20

-25
10 2

10 3

10 4

10 5

10 6

10 7

10 8

10 9

Frequency [Hz]

Figure 6: UNITY GAIN BLAH BLAH ***

simulation plots give different results, the measures have been taken considering the voltage variation
on 10% and 90% of the signal.
SRHL =

540mV 60mV
5V /ms
503ns 408ms

540mV 60mV
7V /ms
554ns 487ms
As expected the measured slew rates are both smaller with respect to the results obtained in the
overestimated hand calculations. The two measured slew rates are quite different from each other
because the OTA itself has intrinsically a non symmetrical structure. The Ids current seen by the M2
transistor is not equal to the Ids current of M1.
SRLH =

Conclusion

The design of the OTA

Simulation Sweep Results

Simulation Sweep Results

The results of the simulation in SPECTRE are shown in the figures below. Here we can see in Figure
7 that increasing Ibias Itail results in little or no change in the gain AV as expected. Also we can
see from Figure 8b that Ibias affects the bandwidth linearly whereas changing the channel length has
very little effect.
Conversely, modifying the channel length affects both the gain and bandwidth in opposing fashion as
shown in Figures 8a and 8c which is also expected from the hand-calculations.
Due to the selective nature of the parametric sweeps, we optimised our design by the following steps.
1. Setting the channel lengths required for M1/2/3/4. We used Figure 8a to set the gain AV to
approx. 21dB. The dashed line indicates this optimal channel length for both M1 and M3 (and
M2/4 by symmetry).
2. We then used Figure 8c to determine whether the bandwidth BW > 0.6M Hz. If BW < 0.6M Hz
then Ibias was increased according to Figure 8b. Since AV is predominantly set by the channel
lengths, this automatically implied BW 0.9M Hz > 0.6M Hz which meant Ibias 260A.
3. The channel lengths and bias current are set and the GBW and AV are also set with the
minimum possible current.

24
40 nm
105 nm
170 nm
235 nm
300 nm

23

Gain [dB]

22

21

20

19

18

17
50

100

150

200

250
Ib [uA]

300

350

Figure 7: Gain vs. Ibias for different values of L1

400

450

Simulation Sweep Results

10

23
45 nm
184 nm
122 nm
161 nm
200 nm

22

Gain [dB]

21

20

19

18

17

16
40

60

80

100
120
140
M3/M4 Channel Length [nm]

160

180

200

(a) Gain vs. L3 for different values of L1

1.8
45 nm
100 nm
170 nm
235 nm
300 nm

1.6

Bandwidth [MHz]

1.4

1.2

0.8

0.6

0.4

0.2
50

100

150

200

250
Ib [uA]

300

350

400

450

(b) Bandwidth vs. Ibias for different values of L1

1.35
45 nm
84 nm
122 nm
161 nm
200 nm

1.3
1.25

Bandwidth [MHz]

1.2
1.15
1.1
1.05
1
0.95
0.9
0.85

40

60

80

100
120
140
M3/M4 Channel Length [nm]

160

(c) Bandwidth vs. L3 for different values of L1

Figure 8

180

200

DRC and LVS Results

11

DRC and LVS Results

Herewith the screenshots of the results obtained from the DRC and LVS checks. Checks were performed with gpdk045 specifications.

(a) Screenshot of LVS results in Layout GXL.

(b) Confirmation of LVS results in Layout GXL.

Figure 9

DRC and LVS Results

12

Figure 10: Screenshot of DRC results in Layout L.