POLITEKNIK SULTAN HAJI AHMAD SHAH KUANTAN

DEPARTMENT OF ELECTRICAL ENGINEERING

DEE6113 CMOS IC DESIGN

Practical Work 6

Layout Design and Simulation of

a Boolean Equation
Registration
No.

No

Name

Practical
Work Report
(Cognitive)

Practical Skill
Marks
(Psychomotor)

Total
Marks

1.

/ 30

/ 70

/ 100

2.

/ 30

/ 70

/ 100

CLASS

LECTURER NAME

: PN. NOORFOZILA BINTI BAHARI

DATE SUBMITTED

(Note: Submit this page along with the practical skill rubric after each Practical Work is completed)

Practical Work Report Marks Distribution

Report format:
1.

Title and Outcomes

/4

2.

Result

/ 12

3.

Discussion

/ 10

4.

Conclusion

/4
TOTAL :

/ 30

DEE6113 CMOS IC Design

PRACTICAL WORK 6
6.1 TITLE: Layout Design and Simulation of Boolean Equation
6.2 LEARNING OUTCOMES
At the end of this practical work session, the student should be able to:
a. design the layout of a Boolean equation.
b. simulate the layout of a Boolean equation.

6.3 EQUIPMENT/TOOLS
PC Set & Microwind 2.6a software

6.4 PROCEDURE
Part A : Designing the layout of a Boolean equation.
1. Produce the truth table for the complex Boolean equation that has been assigned to your
group.
Boolean Function assigned : ________________________
2. Construct the CMOS logic diagram for the assigned Boolean Function.
3. Produce the stick diagram for the Boolean Function based on the CMOS logic diagram
constructed in step 2.
4. Draw the layout design based on the stick diagram in step 3, using Microwind software.
5. Use 0.12 micron technology.
6. Use the transistor size as below:
PMOS : W=12, L=2
NMOS : W=6, L=2
7. Use metal2 layer for VDD and GND, and for horizontal connection. Use metal1 for vertical
connection.
8. Do the DRC. (Make sure that your design has no error).

Part B : Simulating the layout of a Boolean equation.

1. Simulate the Boolean equation layout. Get the the timing diagram of the circuit.
2. Determine the propagation delay of the output.
3. Specify the size of your designed circuit : _________ x _________
Area = ____________2

Page | 1

DEE6113 CMOS IC Design

6.5 RESULTS
In your report, include the results for the following :
1. CMOS static logic diagram of the Boolean equation that has been assigned (show all
the steps how to get the logic diagram)
(3 marks)
2. truth table of the Boolean equation
(2 marks)
3. stick diagram of the Boolean equation using Eulers path (show all the steps how to get
the stick diagram)
(3 marks)
4. layout of the Boolean equation (without any DC error)
(1 mark)
5. timing diagram of the Boolean equation
(1 mark)
6. propagation delay of the output
(1 mark)
2
7. optimized area of the layout (the unit is )
(1 mark)

6.6 DISCUSSION
1. Determine the Boolean equation F, that fulfills the CMOS logic diagram below.

(4 marks)
2.

Draw the stick diagram for the CMOS logic diagram shown above.
(6 marks)

6.7 CONCLUSION
Write FOUR(4) steps in designing the layout of a Boolean equation based on this practical work.
(4 marks)

Page | 2

DEE6113 CMOS IC Design

PRACTICAL SKILL ASSESSMENT RUBRIC

DEE6113 CMOS IC DESIGN
PRACTICAL WORK 6
Student Name :

Class :

Student ID# :

Date :

ASPECTS

A.

Technology feature

B.

Design rule

C.

Transistor size

D.

Metal layers

E.
F.

No DRC error
display
Layout Design
input / output /
floorplan

EXCELLENT
4-5
Use correct technology feature
for ALL parts of the layout.
Follow lambda design rule for
minimum width and spacing for
ALL polygons.
Use correct PMOS and NMOS
transistor size.
Use correct number of metal
layers and width.
Able to produce No DRC error
display for ALL layouts.

SCORE DESCRIPTION
MODERATE
2-3
Use correct technology feature
for parts of the layout.

POOR
1

SCALE

Use other technology feature.

x1

Follow lambda design rule for

MANY of the polygons.

Follow lambda design rule for

ONLY a few of the polygons.

x1

Use acceptable PMOS and NMOS

transistor size.
Use correct metal layers but
incorrect width.
Able to produce No DRC error
display for some of the layouts.

Use incorrect PMOS and

NMOS transistor size.
Use incorrect metal layers and
width.
Not able to produce No DRC
error display at ALL.
Produce acceptable floorplan
and input / output layout
design.
Not able to produce any
simulation for ALL of the
layouts.
Produce large layout size (end
product).

Produce good floorplan and

input / output layout design.

Produce appropriate floorplan

and input / output layout design.

Layout simulation

Able to produce the simulation

of ALL layouts correctly.

Able to produce the simulation

for some of the layouts correctly.

H.

Layout size (end

product)

Produce small layout size (end

product).

Produce acceptable layout size

(end product).

TOTAL

SCORE

x2
x2
x2
x2

x2
x2
/ 70

..
Supervisor Name & Signature