MODE 1 Strobed

Input

Mode 1 Strobed
Output

Mode 2 Bidirectional
Operation

8254 Modes Of Operation

1.Mode 0 (Interrupt On Terminal Count )
2.Mode 1 (Programmable Monoshot )
3.Mode 2 (Rate Generator )
4.Mode 3 (Square Wave Generator )
5.Mode 4 (Software Triggered Strobe )
6.Mode 5 (Hardware Triggered Strobe )

Mode 2: Rate Generator

Mode 3: Square Wave

Generator

Mode 5: Hardware triggered Strobe

Interrupt Vector Table

in the Real Mode
First 32 Interrupt Vectors:
Reserved for system use

Page Fault
(Page required is not in
Physical memory)

Starting address
of interrupt vector = 4 n
Where n is the vector type
For debugging
If Trap flag (TF) F is set

Top 224 Interrupt Vectors:

For user, Hardware and Software

256 Interrupt Vectors

Interrupt type number 00H-FFH

NMI is internally decoded as

Type 2 interrupt. Does not need to provide
an external vector like other hardware
interrupts

4 bytes Far address for each vector

16-bit Segment
address
16-bit Offset
address

Interrupt Processing

At the end of
every normal instruction,
P checks for
interrupts- in this order:
1. Internal Interrupts from
results of execution,
e.g. overflow, divide by 0
2. Single step
3. NMI
4. INTR
5. INT n instructions
Higher
Priority

IRET
Normal Processing

ISR

8
6
7

Restores original
Interrupt status

Hardware Interrupts
Interrupt Pins
Internally
decoded as
type 2 interrupt

Usually uses
interrupt types
numbers
20H to FFH

The INTR bus cycle

Cleared by interrupting device
hardware) or by ISR

Upon acceptance,
P disables further INTRs (Clears IF to 0) (by

By processor
By interrupting
device

At end of ISR, INTR

Is re-enabled (IF = 1)
(as Flags are Restored
by IRET)

Device puts the interrupt vector type, n,

(1 byte) on the data bus
for processor to read