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SAURAV SAH CLASSES

e-Research Lab
ENGINEERING STUDENT
MATLAB
VHDL/Verilog
Robotics & Automata
C/C++/Data Structure

6000/= FOR 30 Days


6000/= FOR 30 Days
6000/= FOR 30 Days
6000/= FOR 30 Days

***B.TECH FINAL YEAR SIMULATION/MODEL BASED PROJECTS ARE ALSO DESIGNED.

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