wait statements cannot be used in functions body: functions execute in zero

simulation time.
Functions cannot call a procedure that has a wait statement in it.
For loop indices must be statically determinable: in order to generate fixed amount
of logic.
Buffer ports are used when a particular port need to be read and written. This mode is different
from inout mode. The source of buffer port can only be internal. For example if you need a signal to be
declared as output, but at the same time read it in the design, then declare it as buffer type.
But buffer types are not recommended by Xilinx and they say if it possible try to reduce the
amount of buffer usage. According to Xilinx, buffers may give some problems during synthesis. If a
signal is used internally and as an output port then in every level in your hierarchical design, it must be
declared as a buffer. So let me show how to reduce the amount of buffer usage with an example.
The following code uses a buffer. I am not going through the functionality of the code since it is very
simple.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity with_buffer is
port(
A : in unsigned(3 downto 0);
B : in unsigned(3 downto 0);
Clk : in std_logic;
C : buffer unsigned(3 downto 0) );
end with_buffer;
architecture BEHAVIORAL of with_buffer is
begin
process(Clk)
begin
if ( rising_edge(Clk) ) then
C <= A + B + C;
end if;
end process;
end BEHAVIORAL;
As you can see the signal C is used repetitively in the addition, and also its an output of the module. So
we declared it as a buffer. Another way to code this same functionality without a buffer is given below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity without_buffer is
port(
A : in unsigned(3 downto 0);
B : in unsigned(3 downto 0);
Clk : in std_logic;
C : out unsigned(3 downto 0) );
end without_buffer;
architecture BEHAVIORAL of without_buffer is
--intermediate signal to avoid the use of buffer.s
signal C_dummy : unsigned(3 downto 0);
begin
C <= C_dummy;

--Assign the intermediate signal to output port.

process(Clk)
begin
if ( rising_edge(Clk) ) then
C_dummy <= A + B + C_dummy; --Use the intermediate signal
in actual calculation.
end if;
end process;
end BEHAVIORAL;
What I have done is, I used an intermediate or dummy signal inside the process statement. The value of
C is read from this dummy signal named C_dummy. And outside the process we assign the value of
C_dummy to the output port C. This is how we reduce the buffer usage in vhdl. Avoiding buffer usage is
very useful particularly in case of hierarchical designs.

pre-layout simulation
Pre-layout simulation is the one you use to check if your gate-level netlist (right after
Synthesis) is functionally correct.but the post layout simulation "no longer in use" was to
check that the gate-level netlist is still functionally equivalent the pre-layout one because
you have added the clock tree, buffers,scan chains etc..
In today's physical design flow, designers use functional verification as a way to check that
the circuit function is right after synthesis.it uses mathematical formulations rather that
dynamic simulation.it is much faster and more mature now.
they also use the STA "statical timing analysis" to compensate the fact that functional
verification can't check timing of the circuit...

http://www1.pldworld.com/@xilinx/html/technote/TOOL/MANUAL/21i_doc/data/fndtn/
ver/ver8_1.htm