MAP notes

Chapter 2: 16 Bit Microprocessor: 8086 Part 2

MINIMUM MODE CONFIGURATION

In minimum mode configuration MN/MX = 1. It consists of 8284 clock generator and reset circuit.
Three octal latches (IC 8282) are used to demultiplex the address/data lines and 2 octal Transrecievers (IC
8286) are used as data amplifiers for the transmission of data to the memory or i/o from the
microprocessor and vice versa.
In this mode all the control signals are given out by the microprocessor itself. Only a single processor is
present on the system.
The latches gets activated when the ALE signal from the microprocessor goes high, which is connected to
STB pin of the Octal latch. This allows address to be available on the output of latch after T1 state.

The Transrecievers have two pins OE and T. The Transrecievers gets activated when it receives a low
signal on the OE pin from the microprocessor pin DEN.
To select the direction of data DT/R is connected to T pin of the Transrecievers. When DT/R = 1,
direction of data is from the microprocessor and when DT/R = 0, direction of data is towards the
microprocessor.
IC 8284 clock generator is used to provide clock signals (timing signals) to the processor so that all the
operations of the processor are properly synchronized and work according to proper timing signals.
The wait state generator is used to add wait states when a slow peripheral is connected to the processor.

TIMING DIAGRAM OF MINIMUM MODE

Memory read machine cycle

During T1 or the 1st clock pulse. The read bus cycle starts and valid address is latched together with
setting minimum and maximum mode = 1, input output or memory interface = 1, data transmit and
receive = 0, i.e. mode of buffer IC. During T2, the Read control signals are issued and data enable signal
= 0 is asserted. Note that during this state the READY signal is also checked to insert wait status, if
needed. During T3, the data from the memory is read by sampling the data bus at the end of T1. During
T4, all bus signals are deactivated in preparation for the next clock cycle.

Memory write machine cycle

During T1 state or the 1st clock pulse, the write bus cycle starts and valid address is latched together with
setting minimum and maximum mode = 1, input output or memory interface = 1, data transmit and
receive mode = 1 of buffer IC. During T2, the write control signals are issued and data enable signal is
asserted. Note that during this state the READY signal is also checked to insert wait status, if needed.
During T3, the data from the memory is written by sampling the data bus at the end of T1. During T4, all
bus signals are deactivated in preparation for the next clock cycle.

IC 8284 (CLOCK GENERATOR)

The 8284 clock generator consist of a reset circuitry which is used to reset the microprocessor.
When a low signal is applied to the RES pin of the clock generator, it sends a high signal to the RESET
pin of the processor thereby restarting the processor (reboot the processor).
Once booted a logic 1 appears on the RES pin as the capacitor gets charged to +5V.
PCLK i.e. peripheral clock is a timing signal to the peripherals to synchronize their operations with the
processor.
The EFI i.e. external frequency input is used to determine the oscillator frequency.
RDY1 and RDY2 are input signals from the peripherals to the clock generator with RDY1 having higher
priority.

74LS373 (Octal LATCH)

An octal latch has 8 D-latches and 8 tri-state buffers.

The 74LS373 octal latch has two control inputs Enable (G) and Output Control (OC).
The Enable control is active high and is connected to CLK inputs of all 8 latches. Logic I in CLK input
will store the logic levels present at D inputs in respective latches.
The Output Control signal is active-low and is connected to control inputs of all 8 tri-state buffers.
Logic O will enable the buffers to output data from respective latches.
The latch Intel 8282 provides the same functionality of 74LS373

74LS245 (Bidirectional Buffer)

We know that 74LS245 is a bi-directional 8-bit buffer.

It has DIR signal to control the direction of data flow.
When DIR signal is low, data flow is from B to A and when it is high data flow is from A to B.
It also has G signal which when activated enables the buffer.

8288 Bus controller

The input to the bus controller are the status signals from the microprocessor in maximum mode.
The output of the bus controller are the control signals which are required to drive the latches and
Transrecievers.
Also control signals such as MEMR, MEMW, IORD, IOWR are also generated from the bus controller.
Which signals should be generated depends on the status of the status signals to the bus controller.
Refer S2,S1,S0 status signals section.

Maximum mode operation

As we can see in the block diagram, maximum mode is the mode in which more than one processor is
present on the system.
Therefore the control signals required to drive the latches and Transrecievers are generated by the bus
controller.
Also control signals required for memory selection and io selection are generated by the bus controller.
The bus controller gets status signals from the microprocessor which gives the status of the operation to
be performed.
The remaining pins which were used in minimum mode but now their functionality changed in maximum
mode are used for request and grant signals to other processors on the system.

TIMING DIAGRAM OF MAXIMUM MODE

Memory read machine cycle

The timing diagram for 8086 maximum mode memory read operation is shown in Figure. In
maximum mode, status codes need to be active to generate control signals from bus controller. Here
MRDC-signal is used instead of RD as in case of minimum mode S2, S1 and S0 are active and are used to
generate control signal through the bus controller.
During T1 or the 1st clock pulse. The read bus cycle starts and valid address is latched together with
setting minimum and maximum mode = 1, input output or memory interface = 1, data transmit and
receive = 0, i.e. mode of buffer IC. During T2, the Read control signals are issued and data enable signal
is asserted = 1. Note that during this state the READY signal is also checked to insert wait status, if
needed. During T3, the data from the memory is read by sampling the data bus at the end of T1. During
T4, all bus signals are deactivated in preparation for the next clock cycle.

Memory write machine cycle

The timing diagram for 8086 maximum mode memory write operation is
shown in Figure. The control signal logic levels and timing diagram are similar to
that of read operation, except for data transmit and receive, memory read and write
signals. Here the T-states correspond to the time during which DEN is low, WRITE
control goes low, DT/R is high and data output is available from the processor on the
data bus.
During T1 state or the 1st clock pulse, the write bus cycle starts and valid address is latched together with
setting minimum and maximum mode = 1, input output or memory interface = 1, data transmit and
receive mode = 1 of buffer IC. During T2, the write control signals are issued and data enable signal =
1 is asserted. Note that during this state the READY signal is also checked to insert wait status, if

needed. During T3, the data from the memory is written by sampling the data bus at the end of T1. During
T4, all bus signals are deactivated in preparation for the next clock cycle.