5

Petra
UMA Schematics Document
Ivy Bridge
Intel PCH

DY :None Installed
DIS:DIS installed
DIS_Muxless :BOTH DIS or Muxless installed
DIS_PX:BOTH DIS or PX installed
DIS_PX_Muxless:DIS or PX or Muxless installed.
Muxless: Muxless installed.(PX4.0)
PX:MUX installed.(PX3.0)
PX_Muxless:BOTH PX or Muxless installed.
UMA:UMA installed
UMA_Muxless:BOTH UMA or Muxless installed
UMA_PX_Muxless:UMA or PX or Muxless installed

ANNIE: ONLY FOR ANNIE solution.

PSL: KBC795 PSL circuit for 10mW solution installed.
10mW: External circuit for 10mW solution installed.
65W: for 65W adaptor installed.
90W: for 90W adaptor installed.

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Cover Page
Size
A3
Date:
5

Document Number

Rev

-1

Petra Uma

W ednesday, February 22, 2012

Sheet
1

of

103

CHARGER

Project code
PCB P/N
PCB No.
Revision

:
:
:
:

40

BQ24727

91.4VM01.001
48.4VM02.001
11324
-1

INPUTS

OUTPUTS

DCBATOUT

BT+

SYSTEM DC/DC
41

RT8223MGQW
INPUTS

OUTPUTS

DCBATOUT

Intel CPU
17W/GT2

5V_AUX_S5
3D3V_AUX_S5
5V_S5
3D3V_S5

CPU DC/DC
DDRIII 1333/1600 Channel A

Ivy Bridge
Sandy Bridge

ISL95836HRTZ

DDRIII
Slot 0
14
1600/1333

42~43

INPUTS

OUTPUTS

DCBATOUT

VCC_CORE

SYSTEM DC/DC
DDRIII 1333/1600 Channel A

44

ISL95836HRTZ

DDRIII
Slot 1
15
1600/1333

INPUTS

OUTPUTS

DCBATOUT

VCC_GFXCORE

4,5,6,7,8,9,10,11,12,13

SYSTEM DC/DC
45

TPS51218DSCR
FDIx4x2
(UMA only)

PCIE x 1
USB x 1

DMIx4

Mini-Card and BT

INPUTS

OUTPUTS

DCBATOUT

1D05V_VTT

LCD

SYSTEM DC/DC

co-lay

49

65

802.11a/b/g

eDP
LVDS

Intel
HDMI

HDMI 51

(RGB CRT)

Feature Port(CRT+LAN)50

PCIE x 1

Feature Port
(CRT+LAN)

LAN

LAN

PCH:HM70/77
Panther Point

50

OUTPUTS

DCBATOUT

RTL8411
26

SD/MMC
31

LDO

INPUTS

ETHERNET (10/100/1000Mb)
USB2.0 x 2

Left Side:
62
USB3.0 x 1

(USB2.0 and USB3.0)co-lay x 1

47

OUTPUTS

3D3V_S0

High Definition Audio

Left Side:
61
USB2.0 x 2

1D5V_S3
0D75V_S0
DDR_VREF_S3

RT9025-25ZSP

74

4 USB 3.0 / 14 USB 2.0/1.1 ports

46

RT8207LGQW
INPUTS

1D8V_S0

LDO

SATA ports (6)

48

G978

PCIE ports (8)

LPC I/F

INPUTS

OUTPUTS

1D05V_VTT

0D85V_S0

ACPI 1.1

USB2.0 x 1
17,18,19,20,21,22,23,24,25,26

49

Internal Analog MIC

COMBO

Azalia
CODEC

Flash ROM
8MB 60

ALC271X

SATA

LPC Bus

AZALIA

SPI

CAMERA

LPC debug port

71

HDD 56 (SATA3_6Gb/s)

26

ODD 56

PCB LAYER
L1:Top
L4:Signal
L2:VCC
L5:GND
L3:Signal L6:Bottom

KBC
SMBus

29

NPCE885P

<Core Design>

27

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

SPEAKER

Title

Touch
PAD 69

Int.
KB69

Thermal
NCT 7718W

28

Block Diagram

Fan 28

Size
A3

25

Date:
5

Document Number

Rev

-1

Petra Uma

Monday, January 07, 2013

Sheet
1

of

103

PCH Strapping
Name
SPKR

Processor Strapping

Huron River Schematic Checklist Rev.0_7

Schematics Notes

Reboot option at power-up

Default Mode: Internal weak Pull-down.
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k
- 10-k weak pull-up resistor.

INIT3_3V#

Weak internal pull-up. Leave as "No Connect".

GNT3#/GPIO55
GNT2#/GPIO53
GNT1#/GPIO51

GNT[3:0]# functionality is not available on Mobile.

Mobile: Used as GPIO only
Pull-up resistors are not required on these signals.
If pull-ups are used, they should be tied to the Vcc3_3power rail.

Strap Description

Configuration (Default value for each bit is

1 unless specified otherwise)

CFG[2]

PCI-Express Static
Lane Reversal

1:
0:

CFG[7]

PEG DEFER TRAINING

1: PEG Train immediately following xxRESETB de assertion

1
0: PEG Wait for BIOS for training

POWER PLANE

VOLTAGE

5V_S0
3D3V_S0
1D8V_S0
1D5V_S0
1D05V_VTT
0D85V_S0
0D75V_S0
VCC_CORE
VCC_GFXCORE
1D8V_VGA_S0
3D3V_VGA_S0
1V_VGA_S0

5V
3.3V
1.8V
1.5V
1.05V
0.95 - 0.85V
0.75V
0.35V to 1.5V
0.4 to 1.25V
1.8V
3.3V
1V

5V_USBX_S3
1D5V_S3
DDR_VREF_S3

5V
1.5V
0.75V

BT+
DCBATOUT
5V_S5
5V_AUX_S5
3D3V_S5
3D3V_AUX_S5

6V-14.1V
6V-14.1V
5V
5V
3.3V
3.3V

3D3V_LAN_S5

3.3V

WOL_EN

Legacy WOL

3D3V_AUX_KBC

3.3V

DSW, Sx

ON for supporting Deep Sleep states

3D3V_AUX_S5

3.3V

G3, Sx

Powered by Li Coin Cell in G3

and +V3ALW in Sx

Disable Danbury:Leave floating (internal pull-down)

HDA_SYNC
GPIO15

GPIO8

2
GPIO27

11

DMI termination voltage. Weak internal pull-up. Do not pull low.

HAD_DOCK_EN#
/GPIO[33]

HDA_SDO

11 : x16 - Device 1 functions 1 and 2 disabled

10 : x8, x8 - Device 1 function 1 enabled ;
function 2 disabled
01 : Reserved - (Device 1 function 1 disabled ;
function 2 enabled)
00 : x8, x4, x4 - Device 1 functions 1 and 2
enabled

Disable Danbury:Left floating, no pull-down required.

15 -> 0, 14 -> 1, ...

PCI-Express
Port Bifurcation
Straps

CFG[6:5]
Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.

NC_CLE

Normal Operation.
Lane Numbers Reversed

Default
Value

Disabled - No Physical Display Port attached to

1: Embedded DisplayPort.
Enabled - An external Display Port device is
0: connectd to the EMBEDDED display Port

SPI_MOSI

NV_ALE

Pin Name

CFG[4]

Enable Danbury: Connect to +NVRAM_VCCQ with 8.2-kohm

weak pull-up resistor [CRB has it pulled up
with 1-kohm no-stuff resistor]

D
Huron River Schematic Checklist Rev.0_7

Low (0) - Flash Descriptor Security will be overridden. Also,

when this signals is sampled on the rising edge of PWROK
then it will also disable Intel ME and its features.
High (1) - Security measure defined in the Flash Descriptor will be enabled.
Platform design should provide appropriate pull-up or pull-down depending on
the desired settings. If a jumper option is used to tie this signal to GND as
required by the functional strap, the signal should be pulled low through a weak
pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently.
Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal
pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for
strapping functions.
Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.

Voltage Rails
DESCRIPTION
ACTIVE IN

S0
CPU Core Rail
Graphics Core Rail

Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no
confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher
suite with confidentiality
Note : This is an un-muxed signal.
This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low.
Sampled at rising edge of RSMRST#.
CRB has a 1-kohm pull-up on this signal to +3.3VA rail.
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down
using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of
RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is
enabled.
Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails.

S3

AC Brick Mode only

All S states

USB Table
PCIE Routing

LANE1

Mini Card2(WWAN)

LANE2

Mini Card1(WLAN) SATA

LANE3

Card Reader

LANE4

Onboard LAN

LANE5

USB3.0

LANE6

Intel GBE LAN

LANE7

Dock

LANE8

New Card

Table
SATA

Pair

Device

Pair

Device

Touch Panel / 3G SIM

USB Ext. port 1 (HS)

I 2 C / SMBus Addresses

Fingerprint

Device

BLUETOOTH

Mini Card2 (WWAN)

CARD READER

X
USB Ext. port 4 / E-SATA /USB CHARGER

HDD1

HDD2

USB Ext. port 2

N/A

10

EDP CAMERA

N/A

11

Mini Card1 (WLAN)

ODD

12

CAMERA

ESATA

13

New Card

SMBus ADDRESSES
Ref Des

HURON RIVER ORB

Address
Hex
Bus

EC SMBus 1
Battery
CHARGER

BAT_SCL/BAT_SDA
BAT_SCL/BAT_SDA
BAT_SCL/BAT_SDA

EC SMBus 2
PCH
eDP

SML1_CLK/SML1_DATA
SML1_CLK/SML1_DATA
SML1_CLK/SML1_DATA

PCH SMBus
SO-DIMMA (SPD)
SO-DIMMB (SPD)
Digital Pot
G-Sensor
MINI

<Core Design>

Wistron Corporation
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK Title
PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK
Size
A3
Date:

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Table of Content
Document Number

Rev

-1

Petra Uma

W ednesday, February 22, 2012

Sheet

of

103

SSID = CPU

1D05V_VTT_CPU
1 OF 9

CPU1A

19 DMI_TXP[3:0]

19 DMI_RXP[3:0]

19 FDI_TXN[7:0]

19 FDI_TXP[7:0]

DMI_RX#0
DMI_RX#1
DMI_RX#2
DMI_RX#3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

N3
P7
P3
P11

DMI_RX0
DMI_RX1
DMI_RX2
DMI_RX3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

K1
M8
N4
R2

DMI_TX#0
DMI_TX#1
DMI_TX#2
DMI_TX#3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

K3
M7
P4
T3

DMI_TX0
DMI_TX1
DMI_TX2
DMI_TX3

FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7

U7
W11
W1
AA6
W6
V4
Y2
AC9

FDI0_TX#0
FDI0_TX#1
FDI0_TX#2
FDI0_TX#3
FDI1_TX#0
FDI1_TX#1
FDI1_TX#2
FDI1_TX#3

FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7

U6
W10
W3
AA7
W7
T4
AA3
AC8

FDI0_TX0
FDI0_TX1
FDI0_TX2
FDI0_TX3
FDI1_TX0
FDI1_TX1
FDI1_TX2
FDI1_TX3

AA11
AC12

19 FDI_FSYNC0
19 FDI_FSYNC1

U11

19 FDI_INT
19 FDI_LSYNC0
19 FDI_LSYNC1

DP_HPD#

1D05V_VTT_CPU

1 R402

2 24D9R2F-L-GP

DP_COMP

FDI_INT

AA10
AG8

FDI0_LSYNC
FDI1_LSYNC

AF3
AD2
AG11

EDP_COMPIO
EDP_ICOMPO
EDP_HPD#

49 DP_HPD#

FDI0_FSYNC
FDI1_FSYNC

Intel(R) FDI

M2
P6
P1
P10

DMI

19 DMI_RXN[3:0]

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

R403
100KR2J-4-GP

AG4
AF4

EDP_AUX#
EDP_AUX

49 DP_TXN0_CPU
49 DP_TXN1_CPU

AC3
AC4
AE11
AE7

EDP_TX#0
EDP_TX#1
EDP_TX#2
EDP_TX#3

49 DP_TXP0_CPU
49 DP_TXP1_CPU

AC1
AA4
AE10
AE6

EDP_TX0
EDP_TX1
EDP_TX2
EDP_TX3

49 DP_AUXN_CPU
49 DP_AUXP_CPU

eDP

DY

PCI EXPRESS -- GRAPHICS

19 DMI_TXN[3:0]

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

G3
G1
G4

PEG_RX#0
PEG_RX#1
PEG_RX#2
PEG_RX#3
PEG_RX#4
PEG_RX#5
PEG_RX#6
PEG_RX#7
PEG_RX#8
PEG_RX#9
PEG_RX#10
PEG_RX#11
PEG_RX#12
PEG_RX#13
PEG_RX#14
PEG_RX#15

H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7

PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8
PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15

K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6

PEG_TX#0
PEG_TX#1
PEG_TX#2
PEG_TX#3
PEG_TX#4
PEG_TX#5
PEG_TX#6
PEG_TX#7
PEG_TX#8
PEG_TX#9
PEG_TX#10
PEG_TX#11
PEG_TX#12
PEG_TX#13
PEG_TX#14
PEG_TX#15

G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4

PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15

F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4

PEG_IRCOMP_R

R401 1
24D9R2F-L-GP

IVY-BRIDGE-GP-NF

71.00IVY.A0U

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU (PCIE/DMI/FDI)
Size
A3

Document Number

Date:

Tuesday, July 10, 2012

Rev

-1

Petra Uma
Sheet

of

103

SSID = CPU

C502
SC47P50V2JN-3GP

C49

CATERR#

27,42 H_PROCHOT#

H_PECI

A48

PECI

1 R513
2 H_PROCHOT#_R
56R2J-L1-GP

C45

PROCHOT#

22,36 H_THERMTRIP#

D45

THERMTRIP#

THERMAL

22,27

CLOCKS

PROC_DETECT#

H_PROCHOT#

C57

R501
62R2J-GP

PROC_SELECT#

DDR3
MISC

1D05V_VTT_CPU

F49

2 OF

MISC

22 H_SNB_IVB#

D
1

3
CPU1B

J3
H2

CLK_EXP_P
CLK_EXP_N

20
20

DPLL_REF_CLK
DPLL_REF_CLK#

AG3
AG1

CLK_DP_P
CLK_DP_N

20
20

SM_DRAMRST#

AT30

1 R502
2
4K99R2F-L-GP

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

BF44
BE43
BG43

SM_RCOMP_0 R506 1
SM_RCOMP_1 R507 1
SM_RCOMP_2 R508 1

BCLK
BCLK#

R503 2
1
10KR2J-L-GP

B46

22,36,97 H_CPUPW RGD

BE45

37 VDDPW RGOOD

UNCOREPWRGOOD

SM_DRAMPWROK

B
BUF_CPU_RST#

XDP_DBRESET#

18,27,31,36,65,71,97

PLT_RST#

3D3V_S0
RN503
SRN1K5J-1-GP
1
8
2
7
3
6
BUF_CPU_RST#
4
5

D44

RESET#

JTAG & BPM

PM_SYNC

PWR MANAGEMENT

C48

SM_DRAMRST# 37

2 140R2F-GP
2 25D5R2F-GP
2 200R2F-L-GP

Signal Routing Guideline:

SM_RCOMP keep routing length less than 500 mils.

19 H_PM_SYNC

PRDY#
PREQ#

N53
N55

TCK
TMS
TRST#

L56
L55
J58

TDI
TDO

M60
L59

DBR#

K58

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7

G58
E55
E59
G55
G59
H60
J59
J61

1D05V_VTT_CPU

XDP_TRST#
XDP_TDO
XDP_TDO
XDP_TRST#

RN501
SRN51J-GP
2
3
1
4

XDP_DBRESET#

IVY-BRIDGE-GP-NF

71.00IVY.A0U
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

A
Title

CPU (THERMAL/CLOCK/PM )

Size
Custom
Date:

Document Number

Rev

-1

Petra Uma

Tuesday, July 10, 2012

Sheet

of

103

SSID = CPU
3 OF 9

CPU1C

4 OF 9

AG6
AJ6
AP11
AL6
AJ10
AJ8
AL8
AL7
AR11
AP6
AU6
AV9
AR6
AP8
AT13
AU13
BC7
BB7
BA13
BB11
BA7
BA9
BB9
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

14
14
14

M_A_BS0
M_A_BS1
M_A_BS2

BD37
BF36
BA28

SA_BS0
SA_BS1
SA_BS2

14
14
14

M_A_CAS#
M_A_RAS#
M_A_W E#

BE39
BD39
AT41

SA_CAS#
SA_RAS#
SA_WE#

15 M_B_DQ[63:0]

SA_CK0
SA_CK#0
SA_CKE0

AU36
AV36
AY26

M_A_DIM0_CLK_DDR0 14
M_A_DIM0_CLK_DDR#0 14
M_A_DIM0_CKE0 14

SA_CK1
SA_CK#1
SA_CKE1

AT40
AU40
BB26

M_A_DIM0_CLK_DDR1 14
M_A_DIM0_CLK_DDR#1 14
M_A_DIM0_CKE1 14

SA_CS#0
SA_CS#1

BB40
BC41

M_A_DIM0_CS#0 14
M_A_DIM0_CS#1 14

SA_ODT0
SA_ODT1

AY40
BA41

M_A_DIM0_ODT0 14
M_A_DIM0_ODT1 14

SA_DQS#0
SA_DQS#1
SA_DQS#2
SA_DQS#3
SA_DQS#4
SA_DQS#5
SA_DQS#6
SA_DQS#7

AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_DQS#[7:0] 14

M_A_DQS[7:0] 14

M_A_A[15:0] 14

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

AL4
AL1
AN3
AR4
AK4
AK3
AN4
AR1
AU4
AT2
AV4
BA4
AU3
AR3
AY2
BA3
BE9
BD9
BD13
BF12
BF8
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58
AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59
AM60
AL59
AF61
AH60

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

15
15
15

M_B_BS0
M_B_BS1
M_B_BS2

BG39
BD42
AT22

SB_BS0
SB_BS1
SB_BS2

15
15
15

M_B_CAS#
M_B_RAS#
M_B_W E#

AV43
BF40
BD45

SB_CAS#
SB_RAS#
SB_WE#

SB_CK0
SB_CK#0
SB_CKE0

BA34
AY34
AR22

M_B_DIM0_CLK_DDR0 15
M_B_DIM0_CLK_DDR#0 15
M_B_DIM0_CKE0 15

SB_CK1
SB_CK#1
SB_CKE1

BA36
BB36
BF27

M_B_DIM0_CLK_DDR1 15
M_B_DIM0_CLK_DDR#1 15
M_B_DIM0_CKE1 15

SB_CS#0
SB_CS#1

BE41
BE47

M_B_DIM0_CS#0 15
M_B_DIM0_CS#1 15

SB_ODT0
SB_ODT1

AT43
BG47

M_B_DIM0_ODT0 15
M_B_DIM0_ODT1 15

SB_DQS#0
SB_DQS#1
SB_DQS#2
SB_DQS#3
SB_DQS#4
SB_DQS#5
SB_DQS#6
SB_DQS#7

AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

DDR SYSTEM MEMORY B

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

DDR SYSTEM MEMORY A

CPU1D
14 M_A_DQ[63:0]

M_B_DQS#[7:0] 15

M_B_DQS[7:0] 15

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22

M_B_A[15:0] 15

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

IVY-BRIDGE-GP-NF
IVY-BRIDGE-GP-NF

71.00IVY.A0U

71.00IVY.A0U
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU (DDR)
5

Size
A3

Document Number

Date:

Tuesday, July 10, 2012

Rev

-1

Petra Uma
Sheet
1

of

103

SSID = CPU
TPAD14-OP-GP
TPAD14-OP-GP

TP701
TP702

1
1

TPAD14-OP-GP

TP703

0:Lane Reversed
D

CFG2
R702
1KR2J-L2-GP

DY

CFG0_TP
CFG1_TP
CFG2
CFG3_TP
CFG4
CFG5
CFG6
CFG7

B50
C51
B54
D53
A51
C53
C55
H49
A55
H51
K49
K53
F53
G53
L51
F51
D52
L53

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

H43
K43

VCC_VAL_SENSE
VSS_VAL_SENSE

H45
K45

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE

F48
G48

VCC_DIE_SENSE
RSVD47

H48
K48

RSVD6
RSVD7

Enabl EDP function

1:Disable
CFG4
0:Enable

CFG4

BA19
AV19
AT21
BB21
BB19
AY21
BA22
AY22
AU19
AU21
BD21
BD22
BD25
BD26
BG22
BE22
BG26
BE26
BF23
BE24

R703
1KR2J-L2-GP

EDP

PCIE Port Bifurcation Straps

CFG[6:5] 11: x16 - Device 1 functions 1 and 2 disabled

RESERVED

1: Normal Operation; Lane #

definition matches socket pin map definition

5 OF 9

CPU1E

PEG Static Lane Reversal

CFG2

BCLK_ITP
BCLK_ITP#

N59
N58

RSVD30
RSVD31
RSVD32
RSVD33

N42
L42
L45
L47

RSVD34
RSVD35
RSVD36
RSVD37
RSVD38

M13
M14
U14
W14
P13

RSVD39
RSVD40

AT49
K24

RSVD41
RSVD42
RSVD43
RSVD44

AH2
AG13
AM14
AM15

RSVD45

N50

DC_TEST_A4
DC_TEST_C4
DC_TEST_D3
DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58
DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1

RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

A4
C4
D3
D1
A58
A59
C59
A61
C61
D61
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled

01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
IVY-BRIDGE-GP-NF

71.00IVY.A0U

R705
1KR2J-L2-GP

R706
1KR2J-L2-GP

DY

DY

DY

R704
1KR2J-L2-GP

CFG7

CFG6

CFG5

PEG DEFER TRAINING

CFG7

1: PEG Train immediately following xxRESETB de assertion

0: PEG Wait for BIOS for training

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU (RESERVED)
Size
A3
Date:
5

Document Number

Rev

-1

Petra Uma

W ednesday, February 29, 2012

Sheet
1

of

103

SSID = CPU

PEG IO AND DDR IO

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

GAP-CLOSE-PWR
PG805
1
2
GAP-CLOSE-PWR
PG806
1
2
GAP-CLOSE-PWR

1
2

R810
100KR2J-4-GP

VCCIO_SEL

BC22

H_VCCP_SEL_L
B

1D05V_VTT_CPU
1D05V_VTT_CPU

+V1.05S_VCCPQE

1 R808
2
0R2J-L-GP
C853
SC1U6D3V2KX-L-1-GP

A44
B43
C44

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

R805
75R3J-L-GP

R804
130R2F-1-GP
R803
1 43R2J-GP2

VR_SVID_ALERT# 42
H_CPU_SVIDCLK 42
H_CPU_SVIDDAT 42

Place near processor

VCC_CORE

SVID

VIDALERT#
VIDSCLK
VIDSOUT

1D05V_VTT_CPU

AM25
AN22

VCCPQE1
VCCPQE2

CORE SUPPLY

1
2
1
2

1
2
1
1
2

3D3V_S5

QUIET
RAILS

1
2

1
2

1
2
1
2

1
1
2

1
2

1
2

1
2

1
2
1
2

2
1
2
1

GAP-CLOSE-PWR
PG804
1
2

SC1U6D3V2KX-L-1-GP
C824

DY

SC1U6D3V2KX-L-1-GP
C823

DY

SC1U6D3V2KX-L-1-GP
C822

SC1U6D3V2KX-L-1-GP
C821

SC1U6D3V2KX-L-1-GP
C814

GAP-CLOSE-PWR
PG803
1
2

1D05V_VTT_CPU

SC1U6D3V2KX-L-1-GP
C813

SC1U6D3V2KX-L-1-GP
C812

1D05V_VTT_CPU
PG801
2

GAP-CLOSE-PWR
PG802
1
2

SC1U6D3V2KX-L-1-GP
C809

1D05V_VTT

SC1U6D3V2KX-L-1-GP
C807

DY

SC10U6D3V5KX-1GP
C845

SC10U6D3V5KX-1GP
C844

SC10U6D3V5KX-1GP
C843

W16
W17

DY

1D05V_VTT_CPU

SC10U6D3V5KX-1GP
C830

VCCIO50
VCCIO51

DY

SC10U6D3V5KX-1GP
C829

AA14
AA15
AB17
AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15

DY

SC10U6D3V5KX-1GP
C840

VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VCCIO41
VCCIO42
VCCIO43
VCCIO44
VCCIO45
VCCIO46
VCCIO47
VCCIO48
VCCIO49

DY

SC10U6D3V5KX-1GP
C839

AF46
AG48
AG50
AG51
AJ17
AJ21
AJ25
AJ43
AJ47
AK50
AK51
AL14
AL15
AL16
AL20
AL22
AL26
AL45
AL48
AM16
AM17
AM21
AM43
AM47
AN20
AN42
AN45
AN48

SC10U6D3V5KX-1GP
C838

VCCIO1
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29

SC1U6D3V2KX-L-1-GP
C806

SC10U6D3V5KX-1GP
C836

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76

Iccmax:8.5A
ICC_TDC:8.5A
SC10U6D3V5KX-1GP
C810

SC2D2U6D3V2KX-GP
C820

DY

SC10U6D3V5KX-1GP
C831

SC10U6D3V5KX-1GP
C834

SC10U6D3V5KX-1GP
C833

SC10U6D3V5KX-1GP
C832

SC10U6D3V5KX-1GP
C835

A26
A29
A31
A34
A35
A38
A39
A42
C26
C27
C32
C34
C37
C39
C42
D27
D32
D34
D37
D39
D42
E26
E28
E32
E34
E37
E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38

SC2D2U6D3V2KX-GP
C811

DY

SC10U6D3V5KX-1GP
C828

SC10U6D3V5KX-1GP
C827

SC10U6D3V5KX-1GP
C826

SC10U6D3V5KX-1GP
C825

DY

SC2D2U6D3V2KX-GP
C819

DY

SC2D2U6D3V2KX-GP
C808

SC2D2U6D3V2KX-GP
C818

SC2D2U6D3V2KX-GP
C817

DY

VCC_CORE

SC2D2U6D3V2KX-GP
C804

SC2D2U6D3V2KX-GP
C803

SC2D2U6D3V2KX-GP
C816

SC2D2U6D3V2KX-GP
C815

DY

SC2D2U6D3V2KX-GP
C802

SC2D2U6D3V2KX-GP
C801

DY

VCC_CORE
D

6 OF 9

SC10U6D3V5KX-1GP
C805

ULV:17W
Iccmax:33A
ICC_TDC:25A

POWER

CPU1F

F43
G43
1D05V_VTT_CPU

AN16
AN17

Place near processor

R802
100R2F-L1-GP-U

DY
VCCIO_SENSE
VSS_SENSE_VCCIO

42
42

VCCSENSE
VSSSENSE

1 R806
2
10R1F-GP

VCCIO_SENSE 45
VSSIO_SENSE 45

VCC_SENSE
VSS_SENSE

SENSE LINES

R801
100R2F-L1-GP-U

R807
10R1F-GP
IVY-BRIDGE-GP-NF

<Core Design>

DY
1

Wistron Corporation

71.00IVY.A0U

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU (VCC_CORE)
Size
Custom
Date:
5

Document Number

Rev

-1

Petra Uma

Tuesday, July 10, 2012

Sheet
1

of

103

SSID = CPU

3
4
2
1

1
2

1
2

1
2

1
2

DY

QUIET RAILS

+1.5S_VCCD_Q

1 R909
2
0R2J-L-GP
1

C923
SC1U6D3V2KX-L-1-GP

0D85V_S0
BC43 TP_VDDQ_SENSE
BA43 TP_VDDQ_VSS

1
1

TP901 TPAD14-OP-GP
TP902 TPAD14-OP-GP
1

VDDQ_SENSE
VSS_SENSE_VDDQ

R902
100R2F-L1-GP-U

R902 need be close to pin U10.

VCCSA_SENSE

VCCSA_VID0
VCCSA_VID1

D48
D49

VCCSA_VID0
VCCSA_VID1

1D05V_VTT_CPU

1D05V_VTT_CPU

U10

VCCSA_SENSE

R908
10KR2J-L-GP

R912
10KR2J-L-GP

VCCSA_VID0
VCCSA_VID1

DY
1

DY
1

VCCSA_VID0
VCCSA_VID1

48
48

C915
SC10U6D3V5KX-1GP

AM28
AN26

ICC_MAX:6A

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
VCCSA9
VCCSA10
VCCSA11
VCCSA12
VCCSA13
VCCSA14
VCCSA15
VCCSA16

VCCDQ1
VCCDQ2

L17
L21
N16
N20
N22
P17
P20
R16
R18
R21
U15
V16
V17
V18
V21
W20

0D85V_S0

1.8V RAIL

VCCPLL1
VCCPLL2
VCCPLL3

SA RAIL

BB3
BC1
BC4
C922
SC1U10V2KX-1GP

SENSE LINES

VAXG_SENSE
VSSAXG_SENSE

VCCSA VID
lines

F45
G45

ICC_MAX:1.2A

DY

PROCESSOR DDR 1.5V QUIET RAIL (BGA only)

SENSE
LINES

2
1

DY

+V1.5S_VCCD_Q should be short to +V1.5S_VCCDDQ on board

1D8V_S0
2

1
2

1
2

1
2

1
2

1
2

VREF
- 1.5V RAILS
DDR3

GRAPHICS

1
2

1
2

1
2
1
2

1
2
1

1D5V_S0

Iccmax:5A

SC1U6D3V2KX-L-1-GP
C926

AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33

SC1U6D3V2KX-L-1-GP
C917

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
VDDQ26

SC1U6D3V2KX-L-1-GP
C918

DY

1D5V_S0

42 VCC_AXG_SENSE
42 VSS_AXG_SENSE

BE7 and BG7 is NC ball in HR

D

SC1U6D3V2KX-L-1-GP
C925

R907
100R2F-L1-GP-U

37
37

RN902
SRN1KJ-7-GP

SC1U6D3V2KX-L-1-GP
C924

1
2

M_VREF_DQ_DIMM0_C
M_VREF_DQ_DIMM1_C

R906,R907 close to CPU

VCC_AXG_SENSE
VSS_AXG_SENSE

37

SC10U6D3V5KX-1GP
C913

R906
100R2F-L1-GP-U

+V_SM_VREF_CNT
M_VREF_DQ_DIMM0_C
M_VREF_DQ_DIMM1_C

BE7
BG7

SC10U6D3V5KX-1GP
C912

VCC_GFXCORE

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

AY43

SC10U6D3V5KX-1GP
C911

SM_VREF
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
VAXG55
VAXG56

Routing Guideline:
Power from DDR_VREF_S3 and +V_SM_VREF_CNT
should have 10 mils trace width.

7 OF 9

SC10U6D3V5KX-1GP
C910

DY

SC1U6D3V2KX-L-1-GP
C916

SC1U6D3V2KX-L-1-GP
C914

SC1U6D3V2KX-L-1-GP
C909

SC1U6D3V2KX-L-1-GP
C907

SC10U6D3V5KX-1GP
C921

SC10U6D3V5KX-1GP
C920

SC10U6D3V5KX-1GP
C919

SC10U6D3V5KX-1GP
C908

DY

SC10U6D3V5KX-1GP
C905

SC10U6D3V5KX-1GP
C904

SC10U6D3V5KX-1GP
C903

SC10U6D3V5KX-1GP
C902

AA46
AB47
AB50
AB51
AB52
AB53
AB55
AB56
AB58
AB59
AC61
AD47
AD48
AD50
AD51
AD52
AD53
AD55
AD56
AD58
AD59
AE46
N45
P47
P48
P50
P51
P52
P53
P55
P56
P61
T48
T58
T59
T61
U46
V47
V48
V50
V51
V52
V53
V55
V56
V58
V59
W50
W51
W52
W53
W55
W56
W61
Y48
Y61

POWER

CPU1G

Iccmax:18A(GT1)
ICC_TDC:12A(GT1)

VCC_GFXCORE

R913
10KR2J-L-GP

R914
10KR2J-L-GP
1

IVY-BRIDGE-GP-NF

71.00IVY.A0U

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU (VCC_GFXCORE)
Size
Custom
Date:
5

Document Number

Rev

-1

Petra Uma

Tuesday, July 10, 2012

Sheet
1

of

103

SSID = CPU

8 OF 9

CPU1H

9 OF 9

CPU1I

VSS

VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180

BG17
BG21
BG24
BG28
BG37
BG41
BG45
BG49
BG53
BG9
C29
C35
C40
D10
D14
D18
D22
D26
D29
D35
D4
D40
D43
D46
D50
D54
D58
D6
E25
E29
E3
E35
E40
F13
F15
F19
F29
F35
F40
F55
G51
G6
G61
H10
H14
H17
H21
H4
H53
H58
J1
J49
J55
K11
K21
K51
K8
L16
L20
L22
L26
L30
L34
L38
L43
L48
L61
M11
M15

VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249

VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300

VSS

NCTF TEST PIN

A5,A57,BC61,BG5
BG57,C3,E1,E61

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90

AM38
AM4
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP10
AP51
AP55
AP7
AR13
AR17
AR21
AR41
AR48
AR61
AR7
AT14
AT19
AT36
AT4
AT45
AT52
AT58
AU1
AU11
AU28
AU32
AU51
AU7
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW13
AW43
AW61
AW7
AY14
AY19
AY30
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC13
BC5
BC57
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BD8
BE5
BG13

NCTF

A13
A17
A21
A25
A28
A33
A37
A40
A45
A49
A53
A9
AA1
AA13
AA50
AA51
AA52
AA53
AA55
AA56
AA8
AB16
AB18
AB21
AB48
AB61
AC10
AC14
AC46
AC6
AD17
AD20
AD4
AD61
AE13
AE8
AF1
AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59
AG10
AG14
AG18
AG47
AG52
AG61
AG7
AH4
AH58
AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48
AJ7
AK1
AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61
AM13
AM20
AM22
AM26
AM30
AM34

M4
M58
M6
N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61
P14
P16
P18
P21
P58
P59
P9
R17
R20
R4
R46
T1
T47
T50
T51
T52
T53
T55
T56
U13
U8
V20
V61
W13
W15
W18
W21
W46
W8
Y4
Y47
Y58
Y59

VSS_NCTF_1#A5
VSS_NCTF_2#A57
VSS_NCTF_3#BC61
VSS_NCTF_8#BG5
VSS_NCTF_9#BG57
VSS_NCTF_10#C3
VSS_NCTF_13#E1
VSS_NCTF_14#E61

A5
A57
BC61
BG5
BG57
C3
E1
E61

VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_11
VSS_NCTF_12

BD3
BD59
BE4
BE58
C58
D59

IVY-BRIDGE-GP-NF

71.00IVY.A0U

<Core Design>

IVY-BRIDGE-GP-NF

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

71.00IVY.A0U
Title

CPU (VSS)
Size
A3
Date:
5

Document Number

Rev

-1

Petra Uma

W ednesday, February 22, 2012

Sheet
1

10

of

103

203
204

ODT0
ODT1
VREF_CA
VREF_DQ
RESET#
VTT1
VTT2

1
2
1D5V_S3

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206

1
2

1
2

DY

0D75V_S0

DDR_VREF_S3

M_VREF_DQ_DIMM0

2 R1404 1
0R3J-4-GP

2 R1405 1
0R3J-4-GP

C1411
SCD1U10V2KX-L1-GP

DDR_WR_VREF01_B4

37

IVB
1

SNB

C1413
SCD1U10V2KX-L1-GP

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

1D5V_S3

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

C1401
SCD1U10V2KX-L1-GP

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

77
122
125

197
201

3D3V_S0

TS#_DIMM0_1 15

SA0
SA1
NC#1
NC#2
NC#/TEST

10KR2J-L-GP

PCH_SMBDATA 15,20,69
PCH_SMBCLK 15,20,69

199

SCD1U10V2KX-L1-GP
C1417

0D75V_S0

EVENT#
VDDSPD

3D3V_S0
R1403
TS#_DIMM0_1

SCD1U10V2KX-L1-GP
C1416

30

15,37 DDR3_DRAMRST#

200
202
198

DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#

Thermal EVENT

11
28
46
63
136
153
170
187

SDA
SCL

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SC10U6D3V5KX-1GP
C1407

126
1

DDR_VREF_S3
M_VREF_DQ_DIMM0

M_A_DIM0_CLK_DDR1 6
M_A_DIM0_CLK_DDR#1 6

SC10U6D3V5KX-1GP
C1406

116
120

6 M_A_DIM0_ODT0
6 M_A_DIM0_ODT1

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

M_A_DIM0_CLK_DDR0 6
M_A_DIM0_CLK_DDR#0 6

102
104

SC10U10V5ZY-1GP
C1405

12
29
47
64
137
154
171
188

BA0
BA1

M_A_DIM0_CKE0 6
M_A_DIM0_CKE1 6

101
103

SC1U6D3V2KX-L-1-GP
C1421

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

CK1
CK1#

M_A_DIM0_CS#0 6
M_A_DIM0_CS#1 6

73
74

SC10U6D3V5KX-1GP
C1404

M_A_DQS[7:0] 6

10
27
45
62
135
152
169
186

CK0
CK0#

114
121

SC1U6D3V2KX-L-1-GP
C1419

M_A_DQS#[7:0] 6

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

CKE0
CKE1

M_A_RAS# 6
M_A_WE# 6
M_A_CAS# 6

SC10U6D3V5KX-1GP
C1403

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

CS0#
CS1#

110
113
115

109
108
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

RAS#
WE#
CAS#

NP1
NP2

M_A_BS0
M_A_BS1
M_A_DQ[63:0]

NP1
NP2

6
6
6

M_A_BS2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_A[15:0] 6

SSID = MEMORY

Tracew should be at least 20 mils wide

DM1
DDR3-204P-122-GP

<Core Design>

62.10017.Z51
2nd = 62.10017.M51
3rd = 62.10024.G21

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DDR3-SODIMM1
Size
Custom
Date:
5

Document Number

Rev

-1

Petra Uma

Tuesday, July 10, 2012

Sheet
1

14

of

103

SSID = MEMORY

203
204

198

TS#_DIMM0_1 14

VDDSPD

199

3D3V_S0

PCH_SMBDATA 14,20,69
PCH_SMBCLK 14,20,69

EVENT#

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF_CA
VREF_DQ
RESET#
VTT1
VTT2

1D5V_S3

1D5V_S3

SA_20111229A

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206

1
2

1
2

1
2

1
2

DY

DY

0D75V_S0

DDR_VREF_S3

M_VREF_DQ_DIMM1
R1503
2 R1502 1
0R3J-4-GP

1
0R3J-4-GP

DDR_WR_VREF01_D1

37

IVB
1

SNB
C1515
SCD1U10V2KX-L1-GP

C1517
SCD1U10V2KX-L1-GP

DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

C1501
SCD1U10V2KX-L1-GP

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

2 R1501 1
10KR2J-L-GP

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

SA1_DIM1

77
122
125

197
201

SA0
SA1
NC#1
NC#2
NC#/TEST

SCD1U10V2KX-L1-GP
C1514

0D75V_S0

200
202

SCD1U10V2KX-L1-GP
C1513

30

14,37 DDR3_DRAMRST#

SDA
SCL

SC10U6D3V5KX-1GP
C1509

126
1

DDR_VREF_S3
M_VREF_DQ_DIMM1

11
28
46
63
136
153
170
187

SC10U6D3V5KX-1GP
C1507

116
120

6 M_B_DIM0_ODT0
6 M_B_DIM0_ODT1

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

SC10U6D3V5KX-1GP
C1506

12
29
47
64
137
154
171
188

M_B_DIM0_CLK_DDR1 6
M_B_DIM0_CLK_DDR#1 6

SC10U6D3V5KX-1GP
C1505

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

M_B_DIM0_CLK_DDR0 6
M_B_DIM0_CLK_DDR#0 6

102
104

SC1U6D3V2KX-L-1-GP
C1521

10
27
45
62
135
152
169
186

M_B_DIM0_CKE0 6
M_B_DIM0_CKE1 6

101
103

SC56P50V2JN-2GP
C1504

M_B_DQS[7:0] 6

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

M_B_DIM0_CS#0 6
M_B_DIM0_CS#1 6

SC1U6D3V2KX-L-1-GP
C1519

M_B_DQS#[7:0] 6

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

CK1
CK1#

BA0
BA1

114
121
73
74

SC5D6P50V2CN-1GP
C1503

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

CK0
CK0#

M_B_RAS# 6
M_B_WE# 6
M_B_CAS# 6

109
108

CS0#
CS1#
CKE0
CKE1

110
113
115

M_B_BS0
M_B_BS1
M_B_DQ[63:0]

RAS#
WE#
CAS#

NP1
NP2

M_B_BS2

NP1
NP2

6
6
6

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_A[15:0] 6

<Core Design>

DM2
DDR3-204P-122-GP

Wistron Corporation

62.10017.Z51
2nd = 62.10017.M51
3rd = 62.10024.G21

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

DDR3-SODIMM2
Size
Custom
Date:
5

Document Number

Rev

-1

Petra Uma

Tuesday, July 10, 2012

Sheet
1

15

of

102

3D3V_S0

RN1702
SRN100KJ-6-GP
1
4
2
3

49 L_BKLT_CTRL
49 LVDS_DDC_CLK_R
49 LVDS_DDC_DATA_R

L_BKLT_EN
LVDS_VDD_EN

L_CTRL_CLK
L_CTRL_DATA

Place near PCH

3D3V_S0

LVDS_IBG

L_BKLTEN
L_VDD_EN

P45

L_BKLTCTL

T40
K47

L_DDC_CLK
L_DDC_DATA

T45
P39

L_CTRL_CLK
L_CTRL_DATA

AF37
AF36

LVD_IBG
LVD_VBG

AE48
AE47

LVD_VREFH
LVD_VREFL

49 LVDSA_CLK#
49 LVDSA_CLK

AK39
AK40

LVDSA_CLK#
LVDSA_CLK

49 LVDSA_DATA0#
49 LVDSA_DATA1#
49 LVDSA_DATA2#

AN48
AM47
AK47
AJ48

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

49 LVDSA_DATA0
49 LVDSA_DATA1
49 LVDSA_DATA2

AN47
AM49
AK49
AJ47

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

AF40
AF39

LVDSB_CLK#
LVDSB_CLK

AH45
AH47
AF49
AF45

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

AH43
AH49
AF47
AF43

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

RN1704
SRN0J-6-GP
2
3
1
4

LVDS_VREFH
LVDS_VREFL

LVDS_DDC_CLK_R
LVDS_DDC_DATA_R

CRT_BLUE
CRT_GREEN
CRT_RED

50 CRT_BLUE
50 CRT_GREEN
50 CRT_RED

N48
P49
T49

CRT_BLUE
CRT_GREEN
CRT_RED

T39
M40

CRT_DDC_CLK
CRT_DDC_DATA

M47
M49

CRT_HSYNC
CRT_VSYNC

T43
T42

DAC_IREF
CRT_IRTN

Digital Display Interface

4
3

LVDS

RN1703
SRN2K2J-1-GP

SDVO_TVCLKINN
SDVO_TVCLKINP

AP43
AP45

SDVO_STALLN
SDVO_STALLP

AM42
AM40

SDVO_INTN
SDVO_INTP

AP39
AP40

SDVO_CTRLCLK
SDVO_CTRLDATA

1
2

R1701
2K37R2F-GP

J47
M45

AT49
AT47
AT40

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

DDPC_CTRLCLK
DDPC_CTRLDATA

50 CRT_HSYNC
50 CRT_VSYNC

4
3
2
1

DAC_IREF_R
R1702
1KR2D-1-GP

PCH_HDMI_CLK 51
PCH_HDMI_DATA 51

HDMI_PCH_DET
DDBP_DATA2#
DDBP_DATA2
DDBP_DATA1#
DDBP_DATA1
DDBP_DATA0#
DDBP_DATA0
DDBP_CLK#
DDBP_CLK

C1701
C1702
C1703
C1704
C1705
C1706
C1707
C1708

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

SCD1U10V2KX-L1-GP
SCD1U10V2KX-L1-GP
SCD1U10V2KX-L1-GP
SCD1U10V2KX-L1-GP
SCD1U10V2KX-L1-GP
SCD1U10V2KX-L1-GP
SCD1U10V2KX-L1-GP
SCD1U10V2KX-L1-GP

51

HDMI_DATA2_R# 51
HDMI_DATA2_R 51
HDMI_DATA1_R# 51
HDMI_DATA1_R 51
HDMI_DATA0_R# 51
HDMI_DATA0_R 51
HDMI_CLK_R# 51
HDMI_CLK_R 51

P46
P42

DDPC_AUXN
DDPC_AUXP
DDPC_HPD

AP47
AP49
AT38

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

DDPD_CTRLCLK
DDPD_CTRLDATA

CRT

5
6
7
8
RN1705
SRN150F-1-GP

RN1706
SRN2K2J-1-GP

P38
M39

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

50 CRT_DDC_CLK
50 CRT_DDC_DATA

3D3V_S0

4 OF 10

PCH1D
27 L_BKLT_EN
49 LVDS_VDD_EN

4
3

L_CTRL_DATA
L_CTRL_CLK

1
2

RN1701
SRN2K2J-1-GP
2
3
1
4

M43
M36

DDPD_AUXN
DDPD_AUXP
DDPD_HPD

AT45
AT43
BH41

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

PANTHER-GP-NF

71.PANTH.00U

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

PCH (LVDS/CRT/DDI)
5

Size
A3

Document Number

Date:

Tuesday, July 10, 2012

Rev

-1

Petra Uma
Sheet
1

17

of

103

SSID = PCH
5 OF 10

INT_PIRQE#
INT_PIRQA#
INT_PIRQC#
INT_PIRQG#

3D3V_S0

62

USB30_RN2

62

USB30_RP2

62

RN1803
DGPU_HOLD_RST#
DGPU_PWR_EN#

2
1

USB30_TN2

3
4
62

SRN10KJ-L-GP

USB30_TP2

INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#

BOOT BIOS Strap

GNT1#/GPIO51

SATA1GP/GPIO19

BOOT BIOS Location

LPC
TPAD14-OP-GP

Reserved

TP1806

TP21
TP22
TP23
TP24

BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30

3D3V_S0

B21
M20
AY16
BG46

DGPU_HOLD_RST#
DGPU_SELECT#
DGPU_PWR_EN#

K40
K38
H38
G38
C46
C44
E40

Reserved
TPAD14-OP-GP

SPI(Default)

TP1804

DGPU_PWM_SELECT#

1 R1813 2
0R0402-PAD

56 SATA_ODD_DA#
69

TP_IN#

5,27,31,36,65,71,97
71
20
27

INT_PIRQE#
INT_PIRQF#
INT_PIRQG#

R1804
R1805
R1806

CLK_PCI_LPC
CLK_PCI_FB
CLK_PCI_KBC

1
1
1

2 22R2J-2-GP
2 22R2J-2-GP
2 22R2J-2-GP

PLT_RST#
CLK_PCI_LPC_R
CLK_PCI_FB_R
CLK_PCI_KBC_R

D47
E42
F46

USB3RN1
USB3RN2
USB3RN3
USB3RN4
USB3RP1
USB3RP2
USB3RP3
USB3RP4
USB3TN1
USB3TN2
USB3TN3
USB3TN4
USB3TP1
USB3TP2
USB3TP3
USB3TP4

PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ1#/GPIO50
REQ2#/GPIO52
REQ3#/GPIO54
GNT1#/GPIO51
GNT2#/GPIO53
GNT3#/GPIO55
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

K10

PME#

H49
H43
J48
K42
H40

RSVD5
RSVD6

AT10
BC8

RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

RSVD23
RSVD24

AV5
AV10

RSVD25

AT8

RSVD26
RSVD27

AY5
BA2

RSVD28
RSVD29

AT12
BF3

G42
G40
C42
D44

C6

AY7
AV7
AU3
BG4

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS

PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
C33

USB_PN0
USB_PP0
USB_PN1
USB_PP1

61
61
62
62

USB Table
Pair

Device

USB2.0 Ext. port 1

USB3.0/USB2.0 Ext. port 2

USB_PN3 49
USB_PP3 49

2
CCD

3
4
5
USB_PN9 61
USB_PP9 61

may not be available

may not be available

8
USB_PN11 65
USB_PP11 65

USB2.0 Ext. port 3

9
10
11

USB_RBIAS

Mini Card1 (WLAN+BT)

12
1
2
R1811
22D6R2F-L1-GP

13

B33
3D3V_S5
A14
K20
B17
C16
L16
A16
D14
C14

3D3V_S0

10
9
8
7
6

RSVD1
RSVD2
RSVD3
RSVD4

R1820
10KR2J-L-GP
1

1
2
3
4
5

USB

TP_IN#
INT_PIRQF#
INT_PIRQB#
INT_PIRQD#

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

PCI

RN1801
SRN8K2J-2-GP-U

BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45

RSVD

PCH1E

OC_PWR

PANTHER-GP-NF

71.PANTH.00U
CLK_PCI_LPC
1

<Core Design>

Wistron Corporation

DY

EC1801
SC33P50V2JN-3GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

PCH (PCI/USB/NVRAM)
Size
Custom
Date:
5

Document Number

Rev

Petra Uma
Tuesday, July 10, 2012

Sheet

-1
18

of

103

SSID = PCH

4 DMI_RXN[3:0]
4 DMI_RXP[3:0]

FDI_TXN[7:0] 4
FDI_TXP[7:0] 4

4 DMI_TXN[3:0]
4 DMI_TXP[3:0]
3 OF 10

PCH1C

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

Signal Routing Guideline:

DMI_ZCOMP keep W=4 mils and
routing length less than 500
mils.
DMI_IRCOMP keep W=4 mils and
routing length less than 500
mils.

4
4
4
4

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

BE24
BC20
BJ18
BJ20

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

4
4
4
4

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

AW24
AW20
BB18
AV18

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

4
4
4
4

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

AY24
AY20
AY18
AU18

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

BJ24

DMI_ZCOMP

FDI_FSYNC0

FDI

BC24
BE20
BG18
BG20

DMI

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

4
4
4
4

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7

4
4
4
4
4
4
4
4

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7

4
4
4
4
4
4
4
4

AW16

FDI_INT

AV12

FDI_FSYNC0

FDI_INT
1D05V_VTT

2 49D9R2F-GP DMI_COMP_R

BG25

DMI_IRCOMP

FDI_FSYNC1

BC10

FDI_FSYNC1

R1902

2 750R2F-GP

BH21

DMI2RBIAS

FDI_LSYNC0

AV14

FDI_LSYNC0

FDI_LSYNC1

BB10

FDI_LSYNC1

DSWVRMEN

A18

RBIAS_CPY

1 R1904 2
100KR2J-4-GP

C12

System Power Management

SUS_PW R_ACK#

DY

R1901

1 R1926 2
10KR2J-L-GP

SUSACK#

SYS_PW ROK
3D3V_S0

1 R1905 2
10KR2J-L-GP

SYS_RESET#

PW ROK

36
27 S0_PW R_GOOD

1
R1924
0R0402-PAD

K3

SYS_PW ROK
PW ROK

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

PM_RSMRST#

C21

RSMRST#

SUS_PW R_ACK_R

K16

37 PM_DRAM_PW RGD

E20

27,97 PM_PW RBTN#

DPWROK
WAKE#

SUS_STAT#/GPIO61

G8

SUSCLK/GPIO62

N14

SLP_S5#/GPIO63

D10

RTC_AUX_S5

DSWODVREN - On Die DSW VR Enable

HIGH

Enabled (DEFAULT)

LOW

Disabled

PM_CLKRUN# 27
RTC_AUX_S5

PCH_SUSCLK_KBC

27
DSW ODVREN

SLP_S4#

H4

PM_SLP_S4# 27,46

SLP_S3#

F4

PM_SLP_S3# 27,29,36,37,47

SLP_A#

G10

ACPRESENT/GPIO31

SLP_SUS#

G16

BATLOW#/GPIO72

PMSYNCH

AP14

PWRBTN#

PM_RSMRST#

DY

PCIE_W AKE#

B9
N3

R1910
1 0R0402-PAD
2
1 R1911 2
10KR2J-L-GP

PCH_DPW ROK

E22

CLKRUN#/GPIO32

SUSWARN#/SUSPWRDNACK/GPIO30

DSW ODVREN

R1917

R1918

2 330KR2J-L1-GP

DY

2 330KR2J-L1-GP

3D3V_S0

H20

27 AC_PRESENT
BATLOW #

E10

PM_RI#

A10

RI#

SLP_LAN#/GPIO29

SLLP_SUS#_TP

TP1904 TPAD14-OP-GP
PM_CLKRUN#

H_PM_SYNC

1 R1919 2
8K2R2J-3-GP

K14

PANTHER-GP-NF

S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

71.PANTH.00U
3D3V_S5

BATLOW #
PM_RI#
AC_PRESENT
SUS_PW R_ACK_R

2 R1921 1
10KR2J-L-GP

PCIE_W AKE#

2 R1922 1
10KR2J-L-GP

SUS_PW R_ACK#

3D3V_AUX_S5

2 R1909 1
100KR2J-4-GP
R1916
10KR2J-L-GP

RN1901
SRN10KJ-6-GP
1
2
3
4

8
7
6
5

3V_5V_POK_#

2 R1908 1
100KR2J-4-GP

<Core Design>

PM_RSMRST# 1 R1912 2
1KR2J-L2-GP

Wistron Corporation

3V_5V_POK 41

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Q1901
2N7002KDW -GP
Title

84.2N702.A3F
2nd = 84.DM601.03F

PM_RSMRST#

RSMRST#_KBC 27

PCH (DM I/FDI/PM)

2

Size
A3

Document Number

Date:

Tuesday, July 10, 2012

Rev

-1

Petra Uma
Sheet
1

19

of

103

SSID = PCH

3D3V_S5

2 OF 10

PCH1B

65 PCIE_RXN4
65 PCIE_RXP4
65 PCIE_TXN4
65 PCIE_TXP4

C2005
C2006

1
1

2 SCD1U10V2KX-L1-GP
2 SCD1U10V2KX-L1-GP

PCIE_TXN3_C
PCIE_TXP3_C

BG36
BJ36
AV34
AU34

1
1

2 SCD1U10V2KX-L1-GP
2 SCD1U10V2KX-L1-GP

PCIE_TXN4_C
PCIE_TXP4_C

BF36
BE36
AY34
BB34
BG37
BH37
AY36
BB36
BJ38
BG38
AU36
AV36
BG40
BJ40
AY40
BB40

3D3V_S0

BE38
BC38
AW38
AY38

PCIE_CLK_REQ0#

R2001
0R2J-L-GP

R2002
10KR2J-L-GP

Y40
Y39

DY

PCIE_CLK_LAN_REQ#

PCIE_CLK_REQ0#

J2

PCIE_CLK_LAN_REQ#
AB49
AB47

PCIE_CLK_REQ1#

AA48
AA47

31 PCIE_CLK_LAN#
31 PCIE_CLK_LAN

Lan

M1

V10

31 PCIE_CLK_LAN_REQ#

H14

SMB_CLK

C9

SMB_DATA

PERN3
PERP3
PETN3
PETP3

LAN

PERN4
PERP4
PETN4
PETP4

WLAN

PERN5
PERP5
PETN5
PETP5
PERN6
PERP6
PETN6
PETP6

SML0ALERT#/GPIO60
SML0CLK
SML0DATA

SML1ALERT#/PCHHOT#/GPIO74
SML1CLK/GPIO58
SML1DATA/GPIO75

PERN7
PERP7
PETN7
PETP7
PERN8
PERP8
PETN8
PETP8

CL_CLK1

CL_RST1#

DRAMRST_CNTRL_PCH

C8

SML0_CLK

G12

SML0_DATA

C13

PCH_GPIO74

1 RN2003
2 SRN2K2J-1-GP

SML0_DATA
SML0_CLK

3
4

2 RN2004
1 SRN2K2J-1-GP

SML1_CLK
SML1_DATA

2
1

3 RN2005
4 SRN2K2J-1-GP

PCH_GPIO74

1
2

4 RN2006
3 SRN10KJ-L-GP

37

3D3V_S0

E14

SML1_CLK 27,28,49

M16

R2009
DRAMRST_CNTRL_PCH 1

SML1_DATA 27,28,49

2
1KR2J-L2-GP

RN2007
SRN2K2J-1-GP
4
3

1
2

M7
T11

3D3V_S0

P10

Q2001
2N7002KDW-GP
R2014
10KR2J-L-GP

PCH_SMBDATA 14,15,69

84.2N702.A3F
2nd = 84.DM601.03F
PCH_SMBCLK 14,15,69

PEG_A_CLKRQ#/GPIO47

CLKOUT_PCIE1N
CLKOUT_PCIE1P

A12

4
3

SMB_DATA
CL_DATA1

CLKOUT_PCIE0N
CLKOUT_PCIE0P
PCIECLKRQ0#/GPIO73

EC_SWI# 27

C2011
C2012

E12

SMBCLK

31 PCIE_RXN3
31 PCIE_RXP3
31 PCIE_TXN3
31 PCIE_TXP3

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLOCKS

SMBALERT#/GPIO11

SMBDATA

SMBUS

PERN2
PERP2
PETN2
PETP2

Link

BE34
BF34
BB32
AY32

Controller

PERN1
PERP1
PETN1
PETP1

PCI-E*

BG34
BJ34
AV32
AU32

SMB_CLK
SMB_DATA

CLKOUT_DMI_N
CLKOUT_DMI_P

PCIECLKRQ1#/GPIO18
CLKOUT_DP_N
CLKOUT_DP_P
CLKOUT_PCIE2N
CLKOUT_PCIE2P
CLKIN_DMI_N
CLKIN_DMI_P

PCIECLKRQ2#/GPIO20

SMB_CLK

PEG_CLKREQ#

M10
AB37
AB38
AV22
AU22

CLK_EXP_N 5
CLK_EXP_P 5

AM12
AM13

CLKOUT_DP_N_C
CLKOUT_DP_P_C

BF18
BE18

CLK_BUF_EXP_N
CLK_BUF_EXP_P

BJ30
BG30

CLK_BUF_CPYCLK_N
CLK_BUF_CPYCLK_P

SRN0J-6-GP RN2017
2
3
1
EDP 4

CLK_DP_N 5
CLK_DP_P 5

RN2008

AB42
AB40
PEG_B_CLKRQ#

E6

REFCLK14IN

PCIECLKRQ5#/GPIO44

CLKIN_PCILOOPBACK

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

XTAL25_IN
XTAL25_OUT

4
3

PCIE_CLK_REQ1#
PCIE_CLK_REQ6#

T13

SRN10KJ-L-GP
V38
V37
PCIE_CLK_REQ7#

PCIECLKRQ1# and PCIECLKRQ2#

Support S0 power only

K12
AK14
AK13

XCLK_RCOMP

CLK_BUF_REF14

H45
V47
V49

Y47

CLKOUT_PCIE6N
CLKOUT_PCIE6P

-1_20120302A
CLK_PCI_FB 18

C2008
SC15P50V2JN-2-GP
2
1

XTAL25_IN

XTAL25_IN
XTAL25_OUT

X2001
XTAL-25MHZ-102-GP

R2006
1MR2J-1-GP

XCLK_RCOMP 1 R2007 2
90D9R2F-1-GP

XTAL25_OUT

1D05V_VTT

82.30020.851
2nd = 82.30020.791
2

C2007
SC15P50V2JN-2-GP

PCIECLKRQ6#/GPIO45
CLKOUT_PCIE7N
CLKOUT_PCIE7P
PCIECLKRQ7#/GPIO46
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

FLEX CLOCKS

1
2

V40
V42

K45

PEG_B_CLKRQ#/GPIO56

3D3V_S0
RN2018

CLK_BUF_CKSSCD_N
CLK_BUF_CKSSCD_P

CLKOUT_PCIE5N
CLKOUT_PCIE5P

CLK_BUF_DOT96_N
CLK_BUF_DOT96_P

L14

CLKIN_SATA_N
CLKIN_SATA_P

PCIECLKRQ4#/GPIO26

G24
E24
AK7
AK5

V45
V46
PCIE_CLK_REQ5#

CLKIN_DOT_96N
CLKIN_DOT_96P
CLKOUT_PCIE4N
CLKOUT_PCIE4P

L12

3
4
SRN10KJ-L-GP

PCIECLKRQ3#/GPIO25

CLKOUTFLEX0/GPIO64
CLKOUTFLEX1/GPIO65

K43

3D3V_S0

3D3V_S0

F47

CLKOUTFLEX2/GPIO66
CLKOUTFLEX3/GPIO67

PCIE_CLK_REQ4#

2
1

H47
R2012
10KR2J-L-GP

K49 DGPU_PRSNT#

PANTHER-GP-NF

R2013
10KR2J-L-GP

UMA_DISCRETE#
UMA: 1 1
DIS :0 1
Optimus(Muxless) : 1 0

Y43
Y45

CLKIN_GND1_N
CLKIN_GND1_P

A8

65 CLK_PCIE_WLAN_REQ#

CLKOUT_PCIE3N
CLKOUT_PCIE3P

Y37
Y36

65 PCIE_CLK_WLAN#
65 PCIE_CLK_WLAN

WLAN

UMA_DIS# 22

DGPU_PRSNT#
1

71.PANTH.00U
R2010
10KR2J-L-GP

R2011
10KR2J-L-GP
2

DY
2

DY

3D3V_S5
1
2
3
4

RN2001
SRN10KJ-6-GP
8 CLK_PCIE_WLAN_REQ#
7 PCIE_CLK_REQ6#
6 PCIE_CLK_REQ5#
5 PCIE_CLK_REQ4#

1
2
3
4

RN2002
SRN10KJ-6-GP
8 PCIE_CLK_REQ0#
7 PCIE_CLK_REQ7#
6 PEG_B_CLKRQ#
5 EC_SWI#

RN2009
SRN10KJ-L3-GP
CLK_BUF_REF14
CLK_BUF_CKSSCD_P
CLK_BUF_CKSSCD_N

1
2
3
4
5

10
9
8
7
6

CLK_BUF_EXP_P
CLK_BUF_EXP_N
CLK_BUF_DOT96_N
CLK_BUF_DOT96_P

need very close to PCH

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

PCH (PCI-E/SMBUS/CLOCK/CL)
Size
Custom

Document Number

Rev

-1

Petra Uma

Date: Tuesday, July 10, 2012

Sheet
1

20

of

103

SSID = PCH

RTC_AUX_S5

RTC_X2

1 R2101 2
10MR2J-L-GP

INTVRMEN- Integrated SUS

1.05V VRM Enable
High - Enable internal VRs
Low - Enable external VRs

C2103
SC1U16V3KX-5GP

X2101
X-32D768KHZ-34GPU

20KR2F-L-GP
1 R2115 2
1
2
R2116
20KR2F-L-GP

RTC_X1

-1_20120223

PCH1A

2
1
2

C2104
SC1U16V3KX-5GP

G2101
GAP-OPEN

RTCRST_ON

RTC_RST#

C20

RTCX2

RTC_RST#

D20

RTCRST#

SRTC_RST#

G22

SRTCRST#

Q2102
R2111
2N7002K-2-GP
2KR2F-3-GP 84.2N702.J31

INTRUDER#

C17

INTVRMEN

HDA_BITCLK

N34

HDA_BCLK

HDA_SYNC

L34

HDA_SYNC

T10

SPKR

HDA_RST#

K34

HDA_RST#

29 HDA_SDIN0

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

PCH_JTAG_TCK_BUF

2 R2121 1
4K7R2J-L-GP

DY
2
R2122
2

29 HDA_CODEC_SDOUT

R2123

29 HDA_CODEC_RST#
29 HDA_CODEC_BITCLK

1
2

HDA_SYNC
1
33R2J-L1-GP
HDA_SDOUT
1
33R2J-L1-GP

4
3

HDA_DOCK_EN#/GPIO33

N32

HDA_DOCK_RST#/GPIO13

27,60 SPI_CLK_R
27,60 SPI_CS0#_R

PCH_SPI_CLK
1 R2108 2
33R2J-L1-GP
1
2 PCH_SPI_CS0#
R2109
33R2J-L1-GP

Low = Default
High = Enable

27,60 SPI_SI_R

1 R2110 2
33R2J-L1-GP

PCH_SPI_SI

27,60 SPI_SO_R

V5

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

AM3
AM1
AP7
AP5

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

AM10
AM8
AP11
AP10

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

AD7
AD5
AH5
AH4

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

AB8
AB10
AF3
AF1

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

Y7
Y5
AD3
AD1

J3

JTAG_TCK

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

H7

JTAG_TMS

SATAICOMPO

Y11

K5

JTAG_TDI

SATAICOMPI

Y10

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

Flash Descriptor Security Overide

HDA_SDOUT

SERIRQ

Y3
Y1
AB3
AB1

HDA_RST#
HDA_BITCLK

RN2102
SRN33J-5-GP-U

E36
K36

SATA

C36

JTAG

HDA_SDOUT

1 R2107 2
1KR2J-L2-GP

27 ME_UNLOCK

29 HDA_CODEC_SYNC

D36

LDRQ0#
LDRQ1#/GPIO23

IHDA

LPC_AD[0..3]
C38
A38
B37
C37

FWH4/LFRAME#

2ND = 84.2N702.031

K22

1 OF 10
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

LPC

RTC_X2

29 HDA_SPKR

RTC_RST#_SS

R2106
100KR2F-L1-GP

RTCX1

SM_INTRUDER#
2 R2104 1
1MR2J-1-GP
PCH_INTVRMEN
1
2
R2105
330KR2F-L-GP

RTC Reset

A20

27,71
D

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME# 27,71

INT_SERIRQ

27

SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0

56
56
56
56

SATA_RXN4
SATA_RXP4
SATA_TXN4
SATA_TXP4

56
56
56
56

HDD1

ODD

1D05V_VTT
SATA_COMP

R2112

2 37D4R2F-GP

1D05V_VTT
SATA3RCOMPO

AB12

SATA3COMPI

AB13

SATA3_COMP

R2113

2 49D9R2F-GP

AH1

RBIAS_SATA3

R2114

2 750R2F-GP

SATA3RBIAS

SPI

27

RTC_AUX_S5

-1_20120301

RTC_X1

SATA 6G

1
C2102
SC6P50V2CN-1GP

3
2

2
2

C2101
SC6P50V2CN-1GP

RTC

82.30001.661
2nd = 82.30001.B21
D

P3

SATA_LED#

SATA0GP/GPIO21

V14

SATA_DET#0

SATA1GP/GPIO19

P1

SATALED#

PANTHER-GP-NF

+3VS_+1.5VS_HDA_IO

71.PANTH.00U

HDA_SDOUT

1 R2102 2
1KR2J-L2-GP

DY
22

PSW _CLR#

SATA_LED#
INT_SERIRQ
SATA_DET#0

1
2
3
4

3D3V_S0
RN2103
SRN10KJ-6-GP
8
7
6
5

PLL ODVR VOLTAGE

R2103
1
2
1KR2J-L2-GP

SPI_CS0#_R

EC2103
SC4D7P50V2CN-1GP

2
EC2102
SC4D7P50V2CN-1GP

DY

+3VS_+1.5VS_HDA_IO

HDA_CODEC_SDOUT
2

HDA_CODEC_BITCLK

Low = 1.8V (Default)

High = 1.5V

HDA_SYNC

DY

EC2101
SC4D7P50V2CN-1GP

DY

HDA_SYNC

5V_S0
A

<Core Design>

R2124
D
HDA_CODEC_SYNC

HDA_SYNC_R

1
2 HDA_SYNC
33R2J-L1-GP

HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to

sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this
signal on the board. Signal may have leakage paths via powered off devices (Audio
Codec) and hence contend with the external pull-up. A blocking FET is
recommended in such a case to isolate HDA_SYNC from the Audio Codec device
until after the Strap sampling is complete.

S
Q2101
2N7002K-2-GP

84.2N702.J31
2ND = 84.2N702.031

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

PCH (SPI/RTC/LPC/SATA/IHDA)
Size
Custom
Date:

Document Number

Rev

-1

Petra Uma

Tuesday, July 10, 2012

Sheet
1

21

of

103

SSID = PCH
6 OF 10

PCH1F

EC_SMI#

A42

DGPU_HPD_INTR#

H36

3D3V_S0
RN2203
H_RCIN#
H_A20GATE

27

E38

EC_SCI#
ICC_EN#

C10

SRN10KJ-L-GP
56 SATA_ODD_PRSNT#
3D3V_S0
PCH_GPIO24

PCH_GPIO12

C4

PCH_GPIO15

G2

1
R2220
10KR2J-L-GP

U2

E16

2
G2201
GAP-OPEN
1

Pass Word Clear

RN2202
SRN10KJ-6-GP
8
7
6
5

49

K4

DMI_OVRVLTG

V8

FDI_OVRVLTG

M5

SPK_HPD_C

N2

PCH_GPIO48

V13

PCH_GPIO49

V3

USB3_SUPPORT

D6

M3

EDP#_LVDS

A20GATE
PECI

SATA4GP/GPIO16

TPAD14-OP-GP

TP2206

PCH_NCTF_1

A4
A44
A45

PCH_NCTF_3

A46
A5

B3
B47

BD1
BD49
BE1
BE49
TPAD14-OP-GP

TP2207

PCH_NCTF_2

BF1

TPAD14-OP-GP

TP2209

PCH_NCTF_4

BF49

GPIO28

INIT3_3V#
DF_TVS

2
0R2J-L-GP

P5

H_RCIN#

AY11
AY10

H_CPUPWRGD
PCH_THERMTRIP_R

H_PECI

R2221
10KR2J-L-GP

DY

USB30

5,36,97

1 R2204 2
390R2J-1-GP

H_THERMTRIP#

AY1

NV_CLE
1D8V_S0

TS_VSS1
STP_PCI#/GPIO34

AH8

TS_VSS2
GPIO35
TS_VSS3
SATA2GP/GPIO36
TS_VSS4

AK11
R2209
2K2R2J-2-GP

AH10
AK10

SATA3GP/GPIO37

NV_CLE

SLOAD/GPIO38

NC_1

1 R2205 2
1KR2J-L2-GP

P37

SDATAOUT0/GPIO39
SDATAOUT1/GPIO48

VSS_NCTF_15#BG2

SATA5GP/GPIO49/TEMP_ALERT#
GPIO57

VSS_NCTF_16#BG48
VSS_NCTF_17#BH3

VSS_NCTF_1#A4
VSS_NCTF_2#A44
VSS_NCTF_3#A45

VSS_NCTF_19#BJ4

BG2
BG48
FDI_OVRVLTG
BH3

FDI TERMINATION VOLTAGE OVERRIDE

R2208
10KR2J-L-GP

BH47
BJ4

VSS_NCTF_20#BJ44
VSS_NCTF_21#BJ45

GPIO37
(FDI_OVRVLTG)

VSS_NCTF_4#A46

VSS_NCTF_22#BJ46

VSS_NCTF_5#A5

VSS_NCTF_23#BJ5

BJ44

VSS_NCTF_6#A6
VSS_NCTF_7#B3
VSS_NCTF_8#B47
VSS_NCTF_9#BD1
VSS_NCTF_10#BD49
VSS_NCTF_11#BE1
VSS_NCTF_12#BE49

VSS_NCTF_24#BJ6
VSS_NCTF_25#C2
VSS_NCTF_26#C48
VSS_NCTF_27#D1
VSS_NCTF_28#D49
VSS_NCTF_29#E1
VSS_NCTF_30#E49

VSS_NCTF_13#BF1

VSS_NCTF_31#F1

VSS_NCTF_14#BF49

VSS_NCTF_32#F49

LOW - Tx, Rx terminated to same voltage

(DC Coupling Model DEFAULT)

BJ45
DMI_OVRVLTG

BJ46

DMI TERMINATION VOLTAGE OVERRIDE

BJ5
R2210
10KR2J-L-GP

BJ6
C2

GPIO36
(DMI_OVRVLTG)

LOW - Tx, Rx terminated to same voltage

(DC Coupling Model DEFAULT)

C48

D1
D49
ICC_EN#

E1

Integrated Clock Chip Enable

E49
R2211
1KR2J-L2-GP

F1

ICC_EN#

HIGH (R2211 DY)- DISABLED [DEFAULT]

DY
F49

LOW (R2211)-

ENABLED

PANTHER-GP-NF

GPIO8 has a weak[20K] internal pull up.

71.PANTH.00U

Integrated Clock Enable functionality is achieved

via soft-strap. The default is integrated clock
enable.
PLL_ODVR_EN

PLL ON DIE VR ENABLE

R2212
1KR2J-L2-GP

USB3_SUPPORT

NOTE:This signal has a weak internal pull-up 20K

ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT
DISABLED -- LOW (R2212 STUFFED)

R2217
10KR2J-L-GP

R2222
10KR2J-L-GP

<Core Design>

DY

No-USB30

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

DY

H_SNB_IVB#

R2215
10KR2J-L-GP

5,36

T14

DY

VRAM_SIZE1
VRAM_SIZE2

PCH_GPIO22

5,27

27

R2216
10KR2J-L-GP
2

DY

GPIO27

THRMTRIP#

27

DY 1 R2203

R2214
10KR2J-L-GP

DY

GPIO24

PROCPWRGD

H_A20GATE
H_PECI_R

3D3V_S5

3D3V_S0

3D3V_S0

R2219
10KR2J-L-GP

SCLOCK/GPIO22

AU16

TP2208

1 R2201 2
1KR2J-L2-GP

R2218
10KR2J-L-GP

TACH0/GPIO17

P4

3D3V_S5
RN2204
SRN10KJ-6-GP
8
7
6
5

A6

GPIO15

VSS_NCTF_18#BH47

TPAD14-OP-GP
PCH_GPIO15

FP_DET#

A40 VRAM_SIZE2

1
2
3
4

PSW_CLR#

C41 VRAM_SIZE1

1
2
3
4

RN2201
SRN10KJ-6-GP
8
7
6
5

K1

56

20

PCH_GPIO12

1
2
3
4

P8

UMA_DIS#

E8

PCH_GPIO27

SATA_ODD_PWRGT

B41

LAN_PHY_PWR_CTRL/GPIO12

CPU/MISC

21

T5

PCH_GPIO24

C40

GPIO8

GPIO

D40

3D3V_S0

PCH_GPIO27

TACH7/GPIO71

RCIN#

PCH_GPIO22

SPK_HPD_C
FP_DET#
S_GPIO
PCH_GPIO49

TACH6/GPIO70

TACH3/GPIO7

10KR2J-L-GP

PLL_ODVR_EN

TACH2/GPIO6

R2202
1

EC_SMI#
DGPU_HPD_INTR#
EC_SCI#
PCH_GPIO48

TACH5/GPIO69

4
3

TACH1/GPIO1

NCTF

1
2

TACH4/GPIO68

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,
BD1,BD49,BE1,BE49,BF1,BF49,
BG2,BG48,BH3,BH47,BJ4,BJ44,
BJ45,BJ46,BJ5,BJ6,C2,C48,D1,
D49,E1,E49,F1,F49

BMBUSY#/GPIO0

T7

S_GPIO

Title

PCH (GPIO/CPU)
Size
Custom
Date:
5

Document Number

Rev

-1

Petra Uma

Tuesday, July 10, 2012

Sheet
1

22

of

103

SSID = PCH
7 OF 10
3D3V_DAC_S0

AN27

VCCIO19

AP21

VCCIO20

AP23

VCCIO21

AP24

VCCIO22

AP26

VCCIO23

AT24

VCCIO24

AP37

V33

VCC3_3_7

V34

VCCVRM3

AT16

VCCDMI1

AT20

VCCCLKDMI

AG16

VCC3_3_3

VCCDFTERM2

AG17

VCCDFTERM3

AJ16

VCCDFTERM4

AJ17

2
AP17

VCCIO27

1D05V_VTT

AU20

VCCDMI2

FDI

1
2

74.70233.03F
2nd = 74.08818.B3F

VCCVRM_S0

2 R2302 1
0R0603-PAD

L2303
IND-10UH-218-GP
1
2

DY

1D05V_VTT
1D5V_S0

70mA

68.10050.10Y
2nd = 68.10090.10B

1D5V_S0_PCH

1
1D8V_S0

1
2

1
VCCSPI

PG4318
2

GAP-CLOSE-PW R

C2326
SCD1U10V2KX-L1-GP

PG4317
2

GAP-CLOSE-PW R

2mA

VCCAFDIPLL

1D05V_VTT

TLV70233DBVR-GP

PG4319
2
B

GAP-CLOSE-PW R
C2322
SCD1U10V2KX-L1-GP

V1

10mA

3D3V_S5

DFT / SPI

1
2

47mA(Total)

VCCVRM2

VCCDFTERM1

VCCIO26

VCCIO25

BG6

1D5V_S0_PCH

C2320
SC1U6D3V2KX-L-1-GP

SC10U6D3V5KX-1GP
C2325

AB36

AN34

AP16

40mA

1D05V_VTT

SC1U6D3V2KX-L-1-GP
C2321

167mA(Total) VCCVRM_S0

C2311

OUT
NC#4

IN
GND
EN

AN33

BH29

DY

PANTHER-GP-NF

71.PANTH.00U

C2323
SC1U6D3V2KX-L-1-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

PCH (POWER1)
5

VCCVRM_S0

228mA(Total)

C2310
SCD1U10V2KX-L1-GP

1
2

C2319
SCD1U10V2KX-L1-GP

+1.05VS_VCC_DMI_CCI

3D3V_S0

1mA

VCC3_3_6

1 R2305 2
0R0603-PAD
2

VCCTX_LVDS4

+1.8VS_VCCTX_LVDS

AP36

AM38

VCCTX_LVDS3

VCCTX_LVDS2

1 R2304 2
0R0603-PAD

1
2
3

1D8V_S0

AM37

VCCIO18

HVCMOS

VCCIO17

AN26

VCCIO

1
2

1
2

1
2

AN21

1
2

CRT
LVDS

VCC CORE

1
2

1
2

1
2

1
2
1
2

SC1U6D3V2KX-L-1-GP
C2309

SC1U6D3V2KX-L-1-GP
C2308

SC1U6D3V2KX-L-1-GP
C2307

SC1U6D3V2KX-L-1-GP
C2306

DMI

VCCIO16

VCCTX_LVDS1

3D3V_S0

SC10U6D3V3MX-L-GP
C2327

AN17

AK37

3D3V_S0

3.711A(Total)

DY

VSSALVDS

+3VS_VCCA_LVDS

3D3V_DAC_S0
U2301

SC1U6D3V2KX-L-1-GP
C2312

VCCIO15

AK36

5V_S0

SC1U10V2KX-1GP

AN16

VCCALVDS

DY

SC1U25V3KX-1-GP
C2318

VCCAPLLEXP

U47

SCD01U16V2KX-L1-GP
C2317

BJ22

VSSADAC

63mA

1 R2315 2
0R0402-PAD

SCD01U16V2KX-L1-GP
C2316

1D05V_VTT

VCCIO28

U48 +VCCA_DAC_1_2
SC10U6D3V5KX-1GP
C2315

1D05V_VTT

AN19

VCCADAC

SCD1U10V2KX-L1-GP
C2314

VCCCORE1
VCCCORE2
VCCCORE3
VCCCORE4
VCCCORE5
VCCCORE6
VCCCORE7
VCCCORE8
VCCCORE9
VCCCORE10
VCCCORE11
VCCCORE12
VCCCORE13
VCCCORE14
VCCCORE15
VCCCORE16
VCCCORE17

SCD01U16V2KX-L1-GP
C2313

SC1U6D3V2KX-L-1-GP
C2304

SC1U6D3V2KX-L-1-GP
C2303

SC1U6D3V2KX-L-1-GP
C2302

SC10U6D3V5KX-1GP
C2301

AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31

POWER

1.7A

PCH1G

1D05V_VTT

Size
A3

Document Number

Date:

Tuesday, July 10, 2012

Rev

-1

Petra Uma
Sheet
1

23

of

103

SSID = PCH
PCH1J

V12

3D3V_S0

DCPSUSBYP

VCCIO32

DY

T29

3D3V_S5

T23

VCCSUS3_3_8
VCCIO14
DCPSUS3

VCCSUS3_3_9
VCCSUS3_3_10

V23

C2424
SCD1U10V2KX-L1-GP

95mA

VCCASW8

AC27

VCCASW9

AC29

VCCASW10

AC31

VCCASW11

1D05V_VTT

AD31

VCCASW13

W21

VCCASW14

W23

VCCASW15

W24

VCCASW16

C2409
SC1U6D3V2KX-L-1-GP

W26
W29

L2403

2
VCCSUS3_3_2

N20

VCCSUS3_3_3

N22

VCCSUS3_3_4

P20

VCCSUS3_3_5

P22

2
3D3V_S5

W33

VCCASW20

AA16

VCC3_3_8

W16

VCC3_3_4

C2430
T34
SCD1U10V2KX-L1-GP

VCC3_3_2

AJ2
1

DCPRTC
VCCIO12
VCCIO13

1D05V_VTT

AH13
AH14

BF47

VCCADPLLB

AF17
AF33
AF34
AG34

SC1U6D3V2KX-L-1-GP

VCCIO7
VCCDIFFCLKN1
VCCDIFFCLKN2
VCCDIFFCLKN3

VCCAPLLSATA
VCCVRM1
VCCIO2

C2413
1
2

VCCIO4

+VCCSST

V16

1D05V_VTT

CPU

1
2

1
2

1
2

1
2
3

DY
T19

VCCSUSHDA

P32

VIN
GND
EN

VOUT

DY

NC#4

DY

G9090-150T11U-GP

74.09090.A3F

DY

10mA
C2433
SCD1U10V2KX-L1-GP
+3VS_+1.5VS_HDA_IO

PANTHER-GP-NF

V21

+3VS_+1.5VS_HDA_IO

HDA

VCCRTC

VCCASW23
VCCASW21

RTC

A22

V_PROC_IO

T21

C2435
SC1U6D3V2KX-L-1-GP

SC10U6D3V5KX-1GP
C2416

SCD1U10V2KX-L1-GP
C2419

SCD1U10V2KX-L1-GP
C2418

SC4D7U6D3V3KX-L-GP
C2417

DY

BJ8

VCCASW22

U2401

SC1U10V3ZY-6GP
C2421

DCPSUS1
DCPSUS2

1D5V_S5

3D3V_S5

AD17

SC1U10V3ZY-6GP
C2437

T17
V19

1mA

C2420
SC1U6D3V2KX-L-1-GP

1D05V_VTT

AC17

DCPSST

1D05V_VTT

6uA

VCCVRM_S0

AC16

C2415
SCD1U10V2KX-L1-GP

RTC_AUX_S5

AF11

C2432
SC1U6D3V2KX-L-1-GP

AK1

VCCSSC

MISC

SC1U6D3V2KX-L-1-GP

AG33

AF14

+1.05VS_VCCA_B_DPL

VCCIO6
VCCADPLLA

BD47

SATA

+1.05VS_VCCA_A_DPL

VCCIO3

C2429
SCD1U10V2KX-L1-GP

1D05V_VTT

C2431
SCD1U10V2KX-L1-GP

VCCVRM4

1
1D05V_VTT

55mA

C2414
SC1U6D3V2KX-L-1-GP

AF13

Y49

C2412

N16

VCCVRM_S0

1D05V_VTT

C2428
SC1U6D3V2KX-L-1-GP

+VCCRTCEXT

C2411
SCD1U10V2KX-L1-GP

1
2
R2407
10R2J-2-GP
C2427
SC1U10V2KX-1GP

3D3V_S0

VCC3_3_1

VCCIO5

C2410
SC1U6D3V2KX-L-1-GP

1mA

+5VS_PCH_VCC5REF

3D3V_S0

P34

VCCASW18
VCCASW19

+1.05VS_VCCA_B_DPL

68.10050.10Y
2nd = 68.10090.10B

V5REF

VCCASW17

W31

83.R0304.A8F
2nd = 83.R0304.D8F

5V_S0

80mA IND-10UH-218-GP

3D3V_S5

+1.05VS_VCCA_A_DPL

68.10050.10Y
2nd = 68.10090.10B

VCCASW12

AN24

D2402
CH751H-40PT-GP

AC26

VCCSUS3_3_1

3D3V_S0

VCCASW7

AN23

AA31

DCPSUS4

1mA

VCCASW6

C2425
SCD1U10V2KX-L1-GP

1D05V_VTT
+5VA_PCH_VCC5REFSUS

AA29

AD29
C

V5REF_SUS

M26

1
2

1
2

1
2

1
2

1
2

SC1U6D3V2KX-L-1-GP
C2408

SC1U6D3V2KX-L-1-GP
C2407

SC1U6D3V2KX-L-1-GP
C2406

SC10U6D3V5KX-1GP
C2404

SC10U6D3V5KX-1GP
C2403

DY

T26

VCCASW5

903mA

VCCIO34

VCCASW4

AA27

C2426
SCD1U10V2KX-L1-GP

P24

VCCASW3

AA26

2
R2408
10R2J-2-GP

3D3V_S5

V24

VCCASW2

AA24

PCI/GPIO/LPC

1D05V_VTT

VCCASW1

Clock and Miscellaneous

AA21

T24

VCCSUS3_3_6
AA19

5V_S5

VCCSUS3_3_7
VCCAPLLDMI2

USB

AL29
AL24

80mA

83.R0304.A8F
2nd = 83.R0304.D8F

BH23
1D05V_VTT

L2402
IND-10UH-218-GP
1
2

D2401
CH751H-40PT-GP

VCC3_3_5

C2402
SC1U10V2KX-1GP

3D3V_S5

T27

VCCIO33

P28

T38

C2423
SC1U6D3V2KX-L-1-GP

P26

VCCIO30
VCCDSW3_3

T16

VCCIO31

2 R2403 1
0R2J-L-GP

N26

3D3V_AUX_S5

1mA

VCCDSW3_3

1D05V_VTT

10 OF 10
VCCIO29

1 R2402 2
0R0402-PAD

3D3V_S5

POWER

VCCACLK

AD49

71.PANTH.00U
1 R2410 2
0R3J-4-GP

DY

DY
1D5V_S5

1 R2409 2
0R0603-PAD
1 R2415 2
0R3J-4-GP

3D3V_S5

DY
1D5V_S0_PCH
A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

PCH (POWER2)
Size
Custom
Date:
5

Document Number

Rev

-1

Petra Uma

Tuesday, July 10, 2012

Sheet
1

24

of

103

SSID = PCH
9 OF 10

PCH1I

PCH1H

H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3

8 OF 10

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79

VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

PANTHER-GP-NF
A

71.PANTH.00U

AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3

VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258

VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS328
VSS329
VSS330
VSS331
VSS333
VSS334
VSS335
VSS337
VSS338
VSS340
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

PANTHER-GP-NF

PCH (VSS)
Size
A3

71.PANTH.00U

Date:
5

Document Number

Rev

-1

Petra Uma

W ednesday, February 22, 2012

Sheet
1

25

of

103

SSID = KBC

31 LAN_WAKE#
38
AD_OFF
41 3D3V_SRC_EN
36,97 S5_ENABLE

3D3V_SRC_EN

39
BAT_IN#
70
LID_CLOSE#
19 RSMRST#_KBC
19,46 PM_SLP_S4#

AD_OFF

ECSWI#_KBC
65 WIFI_RF_EN
65 BLUETOOTH_EN
19 S0_PWR_GOOD

21,60 SPI_CS0#_R
21,60 SPI_CLK_R
21,60
SPI_SO_R
21,60
SPI_SI_R

1
1
1
1

R2701
R2702
R2703
R2704

1
RTC_AUX_S5

R2779
10KR2J-L-GP

104

VREF

97
98
99
100
108
96
95
94

GPIO90/AD0
GPIO91/AD1
GPIO92/AD2
GPIO93/AD3
GPIO5/AD4
GPIO4/AD5
GPIO3/AD6
GPIO7/AD7

101
105
106
107

GPIO94/DA0
GPIO95/DA1
GPIO96/DA2
GPIO97/DA3

79
6
109
14
15
80
17
20
21
26
123
82
83
84

GPIO02
GPIO24
GPIO30/F_WP#
GPIO34/CIRRXL
GPIO36
GPIO41/F_WP#
GPIO42/TCK
GPIO43/TMS
GPIO44/TDI
GPIO51/N2TCK
GPIO67N2TMS
GPIO75
GPIO76
GPIO77

2 EC_SPI_CS#_C
2 EC_SPI_CLK_C
EC_SPI_DI_C
2
2 EC_SPI_DO_C

90
92
86
87
91

114

75
VSBY

2 0F 2

U2701B

7
2
3
1
128
127
126
125
8
9
29
124
121
122

LRESET#/GPIOF7
LCLK/GPIOF5
LFRAME#/GPIOF6
LAD3/GPIOF4
LAD2/GPIOF3
LAD1/GPIOF2
LAD0/GPIOF1
SERIRQ/GPIOF0
GPIO11/CLKRUN#
GPIO65/SMI#
ECSCI#/GPIO54
GPIO10/LPCPD#
GPIO85/GA20
KBRST#/GPIO86

F_CS0#
F_SCK
F_SDI&F_SDIO1
F_SDIO&F_SDIO0
GPIO81/F_WP#

WLAN_WAKE#

1 0F 2

VBKUP

4
VDD

AVCC

19
46
76
88
115

102

EC_VBKUP

U2701A

GPIO52/PSDAT3/RDY#
GPIO50/PSCLK3/TDO
GPIO27/PSDAT2
GPIO26/PSCLK2
GPIO35/PSDAT1
GPIO37/PSCLK1

27
25
11
10
71
72

GPIO17/SCL1/N2TCK
GPIO22/SDA1/N2TMS
GPIO73/SCL2
GPIO74/SDA2
GPIO23/SCL3
GPIO31/SDA3
GPIO47/SCL4
GPIO53/SDA4

70
69
67
68
119
120
24
28

LPC_AD[0..3]

68 CHARGE_LED
29
KBC_BEEP

21,71
40
68

STOP_CHG#
STDBY_LED
28
FAN1_PWM
69 KB_BL_PWM
68
PWRLED

INT_SERIRQ 21
PM_CLKRUN# 19
L_BKLT_EN 17

ECSCI#_KBC

H_A20GATE 22
H_RCIN# 22

BLON_OUT

49
65

ECRST#

69
69

74
93
73

VCORF

44

BAT_SCL 39,40
BAT_SDA 39,40
SML1_CLK 20,28,49
SML1_DATA 20,28,49
AP_DET# 65
DC_BATFULL 68

AP_DET#
PROCHOT_EC

21 ME_UNLOCK
E51_RxD
E51_TxD

19 PCH_SUSCLK_KBC
29
AMP_MUTE#

WLAN_PWR_EN#
TPDATA
TPCLK

65
65

5,22

PSL_OUT_GPIO71#
PSL_IN2_GPI06#
PSL_IN1_GPI70#

31
63
64

28 FAN_TACH1
65 WLAN_WAKE#
19,29,36,37,47 PM_SLP_S3#

PLT_RST# 5,18,31,36,65,71,97
CLK_PCI_KBC 18
LPC_FRAME# 21,71

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

H_PECI

1 R2715 2
43R2J-GP

PECI

CHG_ON#

23
113
111

GPIO46/CIRRXM/TRIST#
GPIO87/CIRRXM/SIN_CR
GP/I/O83/SOUT_CR/TRIST#

77
30

GPIO0/EXTCLK
GPIO55/CLKOUT/IOX_DIN_DIO

85

VCC_POR#

13
12

KBSOUT0/GPOB0/JENK#
KBSOUT1/GPIOB1/TCK
KBSOUT2/GPIOB2/TMS
KBSOUT3/GPIOB3/TDI
KBSOUT4/GPOB4/JEN0#
KBSOUT5/GPIOB5/TDO
KBSOUT6/GPIOB6/RDY#
KBSOUT7/GPIOB7
KBSOUT8/GPIOC0
KBSOUT9/GPOC1/SDP_VIS#
KBSOUT10&P80_CLK/GPIOC2
KBSOUT11&P80_DAT/GPIOC3
KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62
KBSOUT15/GPIO61/XOR_OUT
GPIO60/KBSOUT16
GPIO57/KBSOUT17

53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33

KCOL0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KCOL17

KBSIN0/GPIOA0/N2TCK
KBSIN1/GPIOA1/N2TMS
KBSIN2/GPIOA2
KBSIN3/GPIOA3
KBSIN4/GPIOA4
KBSIN5/GPIOA5
KBSIN6/GPIOA6
KBSIN7/GPIOA7

54
55
56
57
58
59
60
61

KROW0
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7

PECI
VTT

69

KROW[0..7]

69

NPCE885PA0DX-GP

PSL
AC_IN#

GPIO15/A_PWM
GPIO21/B_PWM
GPIO13/C_PWM
GPIO32/D_PWM
GPIO45/E_PWM
GPIO66/G_PWM
GPIO33/H_PWM
GPIO40/F_PWM

1D05V_VTT

40

EC_ENABLE#
KBC_PWRBTN#_R

GPIO56/TA1
GPIO14/TB1
GPIO1/TB2

32
118
62
65
22
81
66
16

KCOL[0..17]

C2712
SCD1U10V2KX-L1-GP

40

3D3V_IOAC

VDD33

33R2J-L1-GP
33R2J-L1-GP
0R2J-L-GP
33R2J-L1-GP

1 R2706 2
0R0402-PAD

DISCRETE#

EC_VBKUP

3D3V_IOAC

31 LAN_PWR_EN

-1_20120223

1 R2705 2
0R0402-PAD

2
ALL_POWER_OK

1
MODEL_ID

3D3V_AUX_KBC

EC_VSBY

EC_VSBY

VCC1
VCC2
VCC3
VCC4
VCC5

2
1

1
2

2
1

2
1

2
1

1
2
2
1

PCB_VER_AD
ADT_TYPE

65 WLAN_PERST#

DY

1 R2770 2
1KR2J-L2-GP

DY

SCD1U10V2KX-L1-GP
C2709

AD_IA
C2701
SCD1U10V2KX-L1-GP

DY

SC2D2U10V3KX-L-GP
C2708

AD_IA

69 KB_BL_DET
21 RTCRST_ON
37,42,48

SCD1U10V2KX-L1-GP
C2707

SCD1U10V2KX-L1-GP
C2706

SCD1U10V2KX-L1-GP
C2705

40

SCD1U10V2KX-L1-GP
C2704

DY

SCD1U10V2KX-L1-GP
C2703

SC2D2U10V3KX-L-GP
C2702

DY

DY

SC2D2U10V3KX-L-GP
C2711

SCD1U10V2KX-L1-GP
C2710

3D3V_AUX_KBC

3D3V_S0

PCH_SUSCLK_KBC

103

C
R2781
10KR2J-L-GP

R2727
100KR2F-L1-GP

R2780
10KR2J-L-GP

3D3V_SRC

AP_DET#

R2777
10KR2J-L-GP

-1_20120221

3D3V_AUX_KBC

AGND

GND1
GND2
GND3
GND4
GND5
GND6
18
45
78
89
116
5

NPCE885PA0DX-GP

71.00885.A0G

C2713
SC1U10V3KX-L1-GP

SC20P50V2JN-1GP
C2736

LAN_WAKE#

FAE suggest

KBC_VCORF

GPIO20/TA2/IOX_DIN_DIO
GP/I/O84/IOX_SCLK/XORTR#
GPO82/IOX_LDSH/TEST#

117
112
110

19,97 PM_PWRBTN#
19 AC_PRESENT
61,62 USB_PWR_EN#

R2778
10KR2J-L-GP

3D3V_SRC_EN

41 3D3V_SRC_EN

DY

R2782
10KR2J-L-GP

2
3D3V_S0

WLAN_PWR_EN#

PSL Function
RN2708
1
2

4
3

FAN_TACH1

3D3V_AUX_S5

3D3V_AUX_KBC

3D3V_AUX_S5

3D3V_AUX_KBC
R2772
1
2
0R2J-L-GP

EC_SCI#

1
2
0R2J-L-GP

ECSWI#_KBC

29,68,82

1 R2759 2 ECSCI#_KBC
0R0402-PAD

G2701
GAP-OPEN

R2774
1
2
10KR2J-L-GP

EC_SPI_DI_C
1

84.T3906.A11
2nd = 84.03906.F11

R2773

2 R2757 1
470R2J-2-GP

KBC_PWRBTN#

DY

Q2701
MMBT3906-4-GP

PROCHOT_EC

ECRST#
S5_ENABLE

4
3

EC_ENABLE#

R2775 1
BAT_IN#
100KR2J-4-GP
RN2705

1
2

Q2703
DMP2305U-7-GP
D

DY

100KR2J-4-GP
BAT_SCL
BAT_SDA

KBC_PWRBTN#

EC_ENABLE#

G
D

C2717
SC220P50V2KX-3GP

10mW

BLUETOOTH_EN

AC_IN#

KBC_PWRBTN#_R

DY

C2715
SC1U6D3V2KX-L-1-GP

Non-10mW

PURE_HW_SHUTDOWN#
ECRST#_B

4
3
SRN10KJ-L-GP

3D3V_AUX_KBC
RN2701
SRN4K7J-8-GP
2
3
1
4

EC_SWI#

22

1
2

28,36 PURE_HW_SHUTDOWN#

20

R2713
330KR2J-L1-GP
1

ECRST#

RN2709
PURE_HW_SHUTDOWN#_R

CHG_ON#
STOP_CHG#

R2714
10KR2J-L-GP

RN2707
SRN100KJ-6-GP
4
3

1
2

DY R2758

SRN10KJ-L-GP

3D3V_AUX_KBC

H_PROCHOT#_EC

1 R2733 2
0R0402-PAD

H_PROCHOT#

5,42

S
R2732
100KR2J-4-GP
2

SRN10KJ-L-GP

Q2702
2N7002K-2-GP

84.2N702.J31
2ND = 84.2N702.031

2.75V

100.0K

33.0K

2.48V

100.0K

47.0K

2.24V

100.0K

64.9K

2.0V

-2

100.0K

76.8

1.87V

100.0K

100K

1.65V

100.0K

143.0K

1.358V

100.0K

174.0K

1.204V

R2776
47KR2F-GP

PCB_VER_AD

ADT_TYPE

30W

10.0K

100.0K

0.3V

DISCRETE#

40W

20.0K

100.0K

0.55V

120W

33.0K

100.0K

0.82V

Reserved

47.0K

100.0K

1.06V

Reserved

64.9K

100.0K

1.3V

90W

215.0K

DY

DISCRETE# will change to internal pull up

3D3V_SRC

R2711
100KR2F-L1-GP

1.047V

A
R2717

100.0K

R2710
10KR2J-L-GP

MODEL_ID

MODEL_ID_R

49

1
R2712
30KR2F-GP

40K2R2F-GP

DY

<Core Design>

-4

DY

R2726
100KR2F-L1-GP

64.17435.6DL

R2709
10KR2J-L-GP

-3
-3M
-1M For PCH B3

-1_20120221

0V

100KR2F-L1-GP
R2708

SC
-1
-1M

3D3V_SRC

65W

3.3V

N/A

20.0K

VOLTAGE

100.0K

100.0K

PULL-HIGH RESISTOR

N/A
100.0K

SB

PULL-LOW RESISTOR

65W
90W

3.0V

VOLTAGE

10.0K

PULL-HIGH RESISTOR

100.0K

PULL-LOW RESISTOR

SA

100KR2F-L1-GP
R2707

ADT_TYPE A/D(PIN99)
PCB VERSION A/D(PIN98)

3D3V_AUX_KBC

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

KBC NPCE885
Size
Custom
Date:

Document Number

Rev

-1

Petra Uma

Tuesday, July 10, 2012

Sheet

27

of

103

SSID = Thermal

3D3V_S0

1
2

Thermal sensor NCT 7718W

4
3

RN2801
Q2803
SRN2K2J-1-GP 2N7002KDW -GP

84.2N702.A3F
2nd = 84.DM601.03F

5V_S0

*Layout* 15 mil

3D3V_S0

D2802
CH551H-30PT-GP

83.R5003.C8F
2ND = 83.R5003.H8H
3rd = 83.5R003.08F

1
NCT_DATA

1
2

1
2

SML1_CLK 20,27,49

SCD1U10V2KX-L1-GP
C2808

SC4D7U10V3KX-GP
C2809

C2802
SCD1U10V2KX-L1-GP

NCT_CLK

SML1_DATA 20,27,49

Layout notice :
Both DXN and DXP routing 10 mil
trace width and 10 mil spacing.

1 R2802 2
0R2J-L-GP DY

Q2801
PMBS3904-1-GP

1
C2806
SC470P50V3JN-2GP

ACES-CON4-29-GP
27

3D3V_S0

P2800_DXP

1
3

DY

R2808
NTC-100K-8-GP

DY
2

1 R2803 2
0R2J-L-GP DY

P2800_DXN

2.System Sensor, Put on palm rest

1
2
R2806
0R0402-PAD

FAN1_PW M

U2801
SC2200P50V2KX-2GP
C2807

84.03904.L06
2nd = 84.03904.T11

THERM_SYS_SHDN#

1
2
3
4

VDD
D+
DT_CRIT#

SCL
SDA
ALERT#
GND

8
7
6
5

FAN1_PW M_R
FAN_TACH1_C

NCT_CLK
NCT_DATA
ALERT#

5V_S0

4
3
2
C

1
5
FAN1

27

NCT7718W -GP

FAN_TACH1

1.H/W T8 Shutdown

FAN_TACH1_C

20.F1639.004
2nd = 20.F1804.004
3rd = 20.F1352.004

D2801
CH551H-30PT-GP

83.R5003.C8F
2ND = 83.R5003.H8H

3rd = 83.5R003.08F

3D3V_S0

3D3V_S0

R2813
18K7R2D-GP

R5
ALERT#

R2809
2KR2F-3-GP

R7

THERM_SYS_SHDN#

DY

DY

SCD1U10V2KX-L1-GP
C2811

R2812
10KR2J-L-GP

27,36 PURE_HW _SHUTDOW N#

DY 1 R2810 2

G
Q2802
2N7002K-2-GP

0R2J-L-GP
1
2
R2811
0R0402-PAD

IMVP_PW RGD_R

84.2N702.J31
2ND = 84.2N702.031

3D3V_S0
IMVP_PW RGD 36,42

SB T8=85 degree
<Core Design>
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Thermal 7718/Fan Controllor P2793

Size
Custom
Date:
5

Document Number

Rev

-1

Petra Uma
Tuesday, July 10, 2012

Sheet
1

28

of

103

5V_S0

5VA_S0

GAP-CLOSE
AUD_AGND

DY

1
2
3

PM_SLP_S3#

EN
GND
VIN

NC#5

VOUT

DY

C2935
SC1U10V2KX-1GP

G9090-475T12U-GP

74.09090.F3F
2nd = 74.70247.03F

DY

C2934
SC10U25V5KX-GP

5V_S5

1
19,27,36,37,47

C2927
SC1U10V3KX-L1-GP

0R0603-PAD U2902

Due to layout concern,

change to DGND

G2903

HDA_CODEC_BITCLK

GAP-CLOSE

1
2

1
2

1
2

SCD1U10V2KX-L1-GP
FC2902

G2901

SCD1U10V2KX-L1-GP
C2907

SC10U10V3MX-GP
C2906

SCD1U10V2KX-L1-GP
C2904

SC10U6D3V3MX-L-GP
C2903

1 R2922 2
0R3J-4-GP

5V_S0

SCD1U10V2KX-L1-GP
FC2901

HDA_CODEC_SDOUT

1 R2923
3D3V_S0

CLOSE TO PIN39 and 46

DY

3D3V_S5

1D5V_S0

1 R2902 2
0R2J-L-GP

DY

281

RN2901
SRN47K-2-GP-U
KBC_BEEP_1
1
SPKR_SB_1
2

R2904
1 0R0402-PAD
2
1
2
R2905
0R0402-PAD

KBC_BEEP 27
HDA_SPKR 21

R2906
4K7R2J-L-GP
COMBO_MIC_JD#

21 HDA_CODEC_SDOUT

4
3

1 R2914 2
33R2J-L1-GP

21 HDA_CODEC_BITCLK

1 R2925 2
0R2J-L-GP

1 R2915 2
22R2J-2-GP

3D3V_S0

DY
21 HDA_SDIN0

AUDIO_PC_BEEP 2
AUDIO_BEEP
1
C2921
SC1U6D3V2KX-L-1-GP

SC100P50V2JN-L-GP
C2922

1 R2908 2
0R2J-L-GP

HDA_CODEC_SYNC
PD#

CLOSE TO PIN35

2
1
1
C2926
TVL-0402-01-AB1-GP

C2901
SC1000P50V3JN-GP-U

R2927
22K1R2F-L-GP

AUD_AGND

AUD_AGND

AUD_AGND
C2913
SCD1U10V2KX-L1-GP
D2901
BAW56-5-GP

C2911
SC2D2U10V3KX-L-GP

PM_SLP_S3# 19,27,36,37,47

AMP_MUTE# 27

83.00056.Q11
2nd = 83.00056.K11

PD#
C2916 1
SCD1U10V2KX-L1-GP

AUD_AGND

INT_MIC_L_R

KBC_PWRBTN# 27,68,82

3
R2910
4K7R2J-L-GP

AUD_AGND

C2914
SC10U6D3V5KX-1GP

1 C2912
SC2D2U10V3KX-L-GP

2
3

AUD_AGND

RN2904
SRN47J-7-GP
2
3
1
4

DY

HDA_CODEC_RST#

21

D2902
BAW56-5-GP

83.00056.Q11
2nd = 83.00056.K11

MIC2V

83.02025.0A1

COMBO_MIC 58

DY
DY

INT_MIC_L_R 49

2
D2903
AZ2025-02S-GP

AUD_MIC_L
AUD_MIC_R

RN2902
SRN1KJ-4-GP
5
6
7
8

2 SC2D2U10V3KX-L-GP
2 SC2D2U10V3KX-L-GP

4
3
2
1

R2917
2K2R2J-2-GP

MIC1-L_PORT-B C2918 1
MIC1-R_PORT-B C2917 1

INT_MIC1_R
COMBO_MIC_R

CLOSE TO PIN19

5VA_S0

CLOSE TO PIN34
AUD_AGND

271

2 R2926 1
10KR2J-L-GP

58 AUD_HP1_JACK_R2
58 AUD_HP1_JACK_L2

MIC2V
C2925 1
2 SC1U16V3KX-5GP
C2924 1
2 SC1U16V3KX-5GP
C2920 1
2 SC2D2U10V3KX-L-GP
C2919 1
2 SC2D2U10V3KX-L-GP
R2920
1
2COMBO_MIC_JD#
20KR2F-L-GP
CLOSE TO PIN18

71.00271.B03

DY

R2909
20KR2F-L-GP

VREF
LDO_CAP_AUDIO
MIC2V

CLOSE TO PIN38

EC2901
SCD1U16V2KX-3GP

AUD_AGND

ALC268_SENSE_A
LIN2-L_PORT-B
LIN2-R_PORT-B
MIC2-L_PORT-B
MIC2-R_PORT-B
ALC268_SENSE_B

ANALOG

AUD_AGND

ALC271X-VB6-CG-GP

13
14
15
16
17
18
19
20
21
22
23
24

SENSE_A
LINE2-L/PORT-E-L
LINE2-R/PORT-E-R
MIC2-L/PORT-F-L
MIC2-R/PORT-F-R
SENSE_B
JDREF
MONO-OUT
MIC1-L/PORT-B-L
MIC1-R/PORT-B-R
LINE1-L/PORT-C-L
LINE1-R/PORT-C-R

83.02025.0A1
3

AUD_AGND

58

Spilt by DGND

36
35
34
33
32
31
30
29
28
27
26
25

D2905
AZ2025-02S-GP

SCD1U10V2KX-L1-GP
C2910

5VA_S0

AUD_HP1_JD#

5V_S0

5V_S5

C2930
SC10U6D3V3MX-L-GP

58 AUD_SPK_L-_R
58 AUD_SPK_L+_R

2 39K2R2F-L-GP

83.02025.0A1

COMBO_MIC_Q

1 R2919 2
22K1R2F-L-GP

AZ2025-02S-GP

GND
SPDIFO
EAPD
PVDD2
SPK-OUT-R+
SPK-OUT-RPVSS2
PVSS1
SPK-OUT-LSPK-OUT-L+
PVDD1
AVDD2
AVSS2

CBP
CBN
CPVEE
HPOUT-R/PORT-I-R
HPOUT-L/PORT-I-L
MIC1-VREFO-L
MIC1-VREFO-R
MIC2-VREFO
LDO-CAP
VREF
AVSS1
AVDD1

5V_S0

R2907 1

JDREF

49
48
47
46
45
44
43
42
41
40
39
38
37

EAPD

AUD_CBP
AUD_CBN
CPVEE
HP_OUT_R_AUD
HP_OUT_L_AUD

84.00138.H31
2nd = 84.05067.031

AUD_AGND

DVDD
GPIO0/DMIC-DATA
GPIO1/DMIC-CLK
PD#
SDATA-OUT
BCLK
DVSS
SDATA-IN
DVDD-IO
SYNC
RESET#
PCBEEP

DIGITAL

(include thermal pad)

Q2901
BSS138-8-GP

DY

2 R2903 1
0R2J-L-GP

COMBO_MIC

1
2
3
4
5
6
7
8
9
10
11
12

U2901

EAPD

C2909
SC22P50V2JN-4GP

58 AUD_SPK_R+_R
58 AUD_SPK_R-_R
D2906

21
21

AUDIO_PC_BEEP

3D3V_S0

DY
AUD_3VD_R
AC97_DATIN

ACZ_BITCLK_AUDIO_+

HDA_CODEC_RST#

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Audio Codec 271X

Size
Custom
Date:
5

Document Number

Rev

-1

Petra Uma

Tuesday, July 10, 2012

Sheet
1

29

of

103

SY6288CAAC-GP

3D3V_SRC
1

IN

3
2
1

OC#
GND
OUT

EVDD10

VDD10

1
2

1
1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

SCD1U10V2KX-L-GP
C3119

DY

DY

SCD1U10V2KX-L-GP
C3118

DY

SC4D7U6D3V3KX-L-GP
C3109

SCD1U10V2KX-L-GP
C3108

DY

SCD1U10V2KX-L-GP
C3107

SCD1U10V2KX-L-GP
C3106

DY

SCD1U10V2KX-L-GP
C3105

SCD1U10V2KX-L-GP
C3104

SCD1U10V2KX-L-GP
C3103

SCD1U10V2KX-L-GP
C3102

SCD1U10V2KX-L-GP
C3101

DY

DY

SWR
VDD33

SCD1U10V2KX-L-GP
C3117

the Caps close to VDD33 pin

VDD33

1
0R5J-5-GP

Non_LAN_IOAC

SCD1U10V2KX-L-GP
C3116

DY

SCD1U10V2KX-L-GP
C3115

R3101

SCD1U10V2KX-L-GP
C3114

VDD33

SC4D7U6D3V3KX-L-GP
C3113

L3101
1
2
IND-4D7UH-192-GP

REGOUT
3D3V_S5

2 R3104 1
0R2J-L-GP

0R2J-L-GP

LDO

2 R3120

2 R3105 1
0R2J-L-GP

LAN_IOAC

74.06288.07F

U3102

SC1U6D3V2KX-L-1-GP
C3127

LAN_IOAC

SCD1U10V2KX-L-GP
C3120

5
C3136
SC4D7U6D3V3KX-L-GP

10KR2J-L-GP

LAN_IOAC

EN/EN#

R3119

27 LAN_PWR_EN

SWR

DY

ENSWREG 2 R3102 1
0R2J-L-GP
ENSWREG 2 R3103 1
0R2J-L-GP

C3125
XTAL1

SD_CD#

PCIE_CLK_LAN
PCIE_CLK_LAN#

SD_CD# 74

PLT_RST#
LAN_WAKE#_R 2 R3118 1 LAN_WAKE#
0R2J-L-GP
LAN_ACT_LED#
10M/100M/1G_LED#

PCIE_CLK_LAN_REQ# 20
PCIE_CLK_LAN 20

PCIE_TXP3

PCIE_TXP3

20

PCIE_TXN3

PCIE_TXN3

20

PCIE_RXP3

PCIE_CLK_LAN# 20
PLT_RST#

1
SD_WP 74

PCIE_RXN3

5,18,27,36,65,71,97

1
1

1
2

1
1
2

1
2

DY

DY
2

DY

SP10

DY

SP9

DY

SP8

2
PCIE_CLK_LAN_REQ#

SD_WP

SD_DATA2 74

DY

SP7

2 R3116 1
0R2J-L-GP

PCIE_TXP3
PCIE_TXN3

SP10

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SP5
SP6
SP7
SP8
SP9
SP10

SD_DATA3 74

SP6

SC5P50V2CN-2GP
C3133

2 R3115 1
0R2J-L-GP

close the Pin 18~pin 23

SP5

SC5P50V2CN-2GP
C3132

SD_CMD 74

SP9

pin33

SC5P50V2CN-2GP
C3131

2 R3114 1
0R2J-L-GP

74

the Caps close to

DY

SC5P50V2CN-2GP
C3130

SP8

DY

SC5P50V2CN-2GP
C3129

SD_CLK

VDD33/18
SC4D7U6D3V3KX-L-GP
C3135

2 R3113 1
0R2J-L-GP

R3108
15K4R2F-GP

DY

SDA

SC4D7U6D3V3KX-L-GP
C3134

SD_DATA0 74

SP7

ISOLATEB

DY

10M/100M/1G_LED#

SC5P50V2CN-2GP
C3128

SD_DATA1 74

2 R3112 1
0R2J-L-GP

VDD10
LAN_WAKE#_R
VDD33
ISOLATEB
PLT_RST#
PCIE_CLK_LAN_REQ#
SD_WP

R3107
1KR2J-L2-GP
R3110
1K54R2F-GP

DY

SCD1U10V2KX-L-GP
C3122

2 R3111 1
0R2J-L-GP

SP6

SCD1U10V2KX-L-GP
C3121

SP5

3D3V_S0

R3109
10KR2J-L-GP

SCD1U10V2KX-L-GP
C3124

RTL8411AA-CG-GP

71.08411.A03

REGOUT
VDD33
VDD33
ENSWREG
SDA

SCD1U10V2KX-L-GP
C3123

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

VDD33
VDD33
CARD_3V3

REGOUT
VDDREG
VDDREG
ENSWREG_H
SDA
LED3
SCL/LED_CR
DVDD10
LANWAKE#
DVDD33
ISOLATE#
PERST#
CLKREQ#
SD_WP/MS_D1/XD_WP#
MS_BS/XD_CLE
VDD33/18

VDD10

MDIP0
MDIN0
AVDD10
MDIP1
MDIN1
MDIP2
MDIN2
AVDD10
MDIP3
MDIN3
AVDD33
DVDD33
CARD_3V3
SD_D7/XD_RDY
SD_D6/MS_INS#/XD_RE#
SD_D5/XD_CE#

MDI3+
MDI3-

1 SC15P50V2JN-2-GP

VDD33

59
59

C3126 2

PCIE_CLK_LAN
PCIE_CLK_LAN#
EVDD10
PCIE_RXP3_C
PCIE_RXN3_C

MDI1+
MDI1MDI2+
MDI2-

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

1
1

59
59
59
59

VDD10

GND

2
2

MDI0+
MDI0-

82.30020.851
2nd = 82.30020.791

-1_20120302A

SD_D4/XD_WE#
SD_D1/MS_CLK/XD_D6
SD_D0/MS_D7/XD_D5
SD_CLK/MS_D3/XD_D4
SD_CMD/MS_D6/XD_D3
SD_D3/MS_D2/XD_D2
SD_D2/XD_D7
GND
HSIP
HSIN
REFCLK_P
REFCLK_N
EVDD10
HSOP
HSON
GND

59
59

XTAL2

AVDD33
AVDD33
RSET
AVDD10
CKXTAL2
CKXTAL1
AVDD33
XD_CD#
MS_D0/XD_D1
MS_D4/XD_D0
SD_CD#/MS_D5/XD_ALE
VDD33/18
DVDD10
LED0
GPO
LED1

U3101
65

R3106
1MR2J-1-GP

X3101
XTAL-25MHZ-102-GP

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49

VDD33
VDD33
RSET
VDD10
XTAL2
XTAL1
VDD33

R3117
2K49R2F-GP

PCIE_RXP3
PCIE_RXN3

DY

10M/100M/1G_LED#

SD_CD#
VDD33/18
VDD10
LAN_ACT_LED#

RSET
1

1
2

SC4D7U6D3V3KX-L-GP
C3111

SCD1U10V2KX-L-GP
C3110

DY

SC12P50V2JN-3GP
1

2
2

LDO
CARD_3V3

PCIE_RXP3 20
PCIE_RXN3 20

<Core Design>

LAN_WAKE# 27

Wistron Corporation

LAN_ACT_LED# 59

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

10M/100M/1G_LED# 59
Title

LAN(RTL8411)
Size
Custom
Date:
5

Document Number

Rev

Husk/Petra
Tuesday, July 10, 2012

Sheet

-1
31

of

103

Power Sequence
1 R3622 2
1KR2J-L2-GP

H_THERMTRIP# 5,22

1D05V_VTT

DY

1 R3601 2 H_PW RGD_R

1KR2J-L2-GP

1 R3614 2
0R0402-PAD

2
1

84.02222.V11

C3612
SCD01U50V2KX-L-GP

DY

R3632
2K2R2J-2-GP

SYS_PW ROK 19

28,42 IMVP_PW RGD

2 R3616 1
4K7R2J-L-GP

PLT_RST#

SCD1U10V2KX-L1-GP
C3602

5,18,27,31,65,71,97

Q3601
MMBT2222A-3-GP

B
1

5,22,97 H_CPUPW RGD

19,27,29,37,47 PM_SLP_S3#

3
2
D3603
BAS16-6-GP

27,28

83.00016.K11

2ND = 83.00016.F11

DY

2ND = 83.00016.F11

200KR2J-L1-GP
R3602

83.00016.K11

PURE_HW _SHUTDOW N#

D3601
BAS16-6-GP

41 5V_S5_EN

2 R3603 1
2KR2F-3-GP

S5_ENABLE 27,97

U3604
AO4468-GP

ANNIE Run Power

5V_S0

1
2
3
4

5V_S5

1
1

RUN_ENABLE

DY 2

C3607
SCD1U25V3KX-L-GP

D
D
D
D

S
S
S
G

84.04468.037
= 84.08882.037

6
5
4

19,27,29,37,47 PM_SLP_S3#
3D3V_S0
5V_S0

EN
DC2
DC1

VCC
GND
HV

RUN_ENABLE

1
2
3

Q3606
2N7002K-2-GP

3D3V_SRC

84.2N702.J31
2ND = 84.2N702.031

8
7
6
5

19,27,29,37,47 PM_SLP_S3#
B

U3605
AO4468-GP
1D5V_S0

84.04468.037
2nd = 84.08882.037
1
2
3
4

D
D
D
D

S
S
S
G

1D5V_S3

8
7
6
5

EC change

D
D
D
D

S
S
S
G

1
2
3
4

RUN_ENABLE_R

5V_S5

74.05938.09P

PS_S3CNTRL 37

U3607
AO4468-GP
3D3V_S0 2nd

U3610
G5938TL1U-GP

3D3V_S5

1 R3626 2
0R0402-PAD

DY

5V_S5

8
7
6
5

1 R3608 2
100KR2J-4-GP

C3603
SCD1U16V2KX-L-GP

84.04468.037
2nd = 84.08882.037

C3611
SCD01U50V2KX-L-GP

SY6288CAAC-GP

3D3V_S5_EN

DY

10KR2J-L-GP

3D3V_SRC

EN/EN#
IN

OC#
GND
OUT

U3611

3D3V_S5

DY

-1_20120221

DY

C3615
SC10U10V3MX-GP

3D3V_SRC
3D3V_S5

DY
R3629

74.06288.07F

C3614
SCD22U10V2KX-1GP

3
2
1

R3628
5V_S5_EN

<Core Design>

Wistron Corporation

0R5J-5-GP

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Option for non-IOAC

Title

EC change
5

Power Plane Enable

2

Size
A3

Document Number

Date:

Tuesday, July 10, 2012

Rev

-1

Petra Uma
Sheet
1

36

of

103

Close to CPU
S3 Power Reduction Circuit Processor VREF_DQ Implementation
1 R3707 2
0R2J-L-GP

DDR_VREF_S3

DY

1 R3708 2
0R2J-L-GP

DY
S

+V_SM_VREF_CNT 9

Q3709
AO3418-GP

D
R3705
100KR2J-4-GP

14 DDR_W R_VREF01_B4

M_VREF_DQ_DIMM0_C

IVB
84.03418.031
2nd = 84.03404.C31
G

Q3708
2N7002K-2-GP

84.2N702.J31
2ND = 84.2N702.031
PM_SLP_S3# 19,27,29,36,47

DRAMRST_CNTRL_PCH

Close to DIMM
S3 Power Reduction Circuit SM_DRAMPWROK

20

DY

1 R3714 2
0R2J-L-GP
Q3710
AO3418-GP

0D75V_S0

15 DDR_W R_VREF01_D1

R3703
22R2J-2-GP

M_VREF_DQ_DIMM1_C

IVB

84.03418.031
2nd = 84.03404.C31

2
1

R3710
0R0402-PAD

DRAMRST_CNTRL_PCH

20

0D75V_EN 46

Q3701
2N7002K-2-GP

C3705
SCD1U10V2KX-L1-GP

84.2N702.J31
2ND = 84.2N702.031

DY
G

DY

36

1 R3716 2
0R2J-L-GP

19,27,29,36,47 PM_SLP_S3#

PS_S3CNTRL_D

1D05VTT_PW RGD 45,48

Close to CPU
S3 Power Reduction Circuit SM_DRAMPWROK

PS_S3CNTRL

1D5V_S3

IN A
GND OUT Y

U3701
74VHC1G09DFT2G-GP

1
VDDPW RGOOD

84.2N702.J31
2ND = 84.2N702.031

14,15

DY

DRAMRST_CNTRL_PCH

DY

R3720
0R2J-L-GP

20

2
1DRAMRST_CNTRL_PCH
C3703
SCD047U16V2KX-1-GP

73.01G09.AAH
2nd = 73.01G09.0AB

DDR3_DRAMRST#

C3702
SC100P50V2JN-L-GP

DY

Q3703
2N7002K-2-GP

VDDPW RGOOD_R 1 R3719 2

130R2F-1-GP

IN B

SM_DRAMRST#_D 1 R3718 2
0R0402-PAD

VCC

0D75V_EN_1

3
C3701
SCD1U10V2KX-L1-GP

D
R3702
200R2F-L-GP

2
1 R3701 2
0R0402-PAD

SM_DRAMRST#

R3721

S3 Power Reduction Circuit

SM_DRAMRST#

1D5V_S0
5

DY 200R2F-L-GP

19 PM_DRAM_PW RGD

DY
3D3V_S5

R3713
200R2F-L-GP

27,42,48 ALL_POW ER_OK

1 R3709 2
0R2J-L-GP

1D5V_S3

3D3V_S5

R3706
1KR2J-L2-GP

Close to CPU
S3 Power Reduction Circuit SM_DRAMPWROK

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ADAPTER
5

Size
A3

Document Number

Date:

Tuesday, July 10, 2012

Rev

-1

Petra Uma
Sheet
1

37

of

103

ANNIE solution

Adaptor in to generate DCBATOUT

D

1Pin=3A

DCIN1
6
NP1
1

AD_JK

20.F2182.005

PC3802
SC1U50V5ZY-1-GP

2
1

ACES-CON5-27-GP

SCD1U50V3KX-GP
PC3801

2
3
4
5
NP2
7

D3801
P6SBMJ27APT-GP

2nd = 20.F2198.005

83.P6SBM.DAG
2nd = 83.P6SMB.JAG
3rd = 83.P6SMB.CAG

AD_JK

AD+

PWR_AD+_2

1
2
3
4

2
PWR_ADJK_EN

R1

8
7
6
5

PC3805
SC1U50V5ZY-1-GP

PQ3802
PDTA124EU-1-GP

84.00024.A1K
2ND = 84.00124.H1K
3rd = 84.05124.011

84.00124.K1K
2nd = 84.00024.01K
3rd = 84.05124.A11

2
R2
PQ3801
LTC024EUB-FS8-GP

PR3808
100KR2J-4-GP
2

AD_OFF

R2
27

R1

D
D
D
D

QM3005S-GP
200KR2F-L-GP
PR3807

PU3802
S
S
S
G

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

DCIN JACK
Size
A4

Document Number

Date:
5

Rev

Petra Uma
Tuesday, July 10, 2012

Sheet

-1
38

of
1

103

BATTERY CONNECTOR
TPAD14-OP-GP TP3901

TPAD14-OP-GP TP3902

TPAD14-OP-GP TP3903

BAT_IN#_1

TPAD14-OP-GP TP3904

BI

TPAD14-OP-GP TP3905

BATA_SDA_1

TPAD14-OP-GP TP3906

BATA_SCL_1

TPAD14-OP-GP TP3907

BT+
BT+

BI

4
3
2
1

27 BAT_IN#
27,40 BAT_SCL
27,40 BAT_SDA

5
6
7
8

1
3
5
7
4
6
8

BAT_IN#_1
BATA_SCL_1
BATA_SDA_1

1
2

PC3901
SCD1U50V3KX-GP

BT+

R3902
0R0402-PAD

PC3902
SC2200P50V2KX-2GP

BAT2
ACES-CONN8D-GP

PN3901
SRN33J-7-GP

20.81633.008
BAT_IN#_1

PD3901
MMPZ5232BPT-GP-U

83.5R603.D3F
2ND = 83.5R603.K3F
3rd = 83.5R603.Q3F

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

BATT CONN
Size
A4

Document Number

Date:
5

Rev

Petra Uma
Tuesday, July 10, 2012

Sheet

-1
39

of
1

103

SSID = Charger

S
S
S
G

Delete PR4016
PR4015 change to 10 ohm
84.2N702.A3F
Wayler , 2011-1208

PC4003
SCD1U25V2KX-GP
DCBATOUT

EC change

CHG_AGND

2
4
3
2
1

1
2

PR4030
100KR2J-4-GP

27

PWR_CHG_ACOK

AC_IN#

27 STOP_CHG#

PQ4006
2N7002A-7-GP

PQ4008
2N7002A-7-GP
STOP_CHG

AC_IN#

PWR_CHG_BAT_SDA
1
GAP-CLOSE-PWR-3-GP

CHG_AGND
PR4029
100KR2J-4-GP

2
PG4010

PWR_CHG_BAT_SCL
1
GAP-CLOSE-PWR-3-GP

27,39 BAT_SDA

2
PG4008

CHG_AGND

BAT_SCL

3D3V_AUX_S5

PWR_CHG_CSOP_1

PC4023

BATT_SENSE_G

3D3V_AUX_S5

27,39

PR4032 , PR4033 DY
Wayler , 12-06

DY DY10KR2F-L1-GP
2

10KR2F-L1-GP

PR4033

PR4032

27

PC4022

DY
2

3D3V_AUX_S5

PG4013
GAP-CLOSE-PWR-3-GP

AD_IA

PC4012
SCD1U25V2KX-GP

CHG_AGND

2
PR4013
0R0402-PAD

PC4021

GND

GND
14

1
2

PU4003 change to 74.24727.073

Wayler , 2011-1208

PC4020

CHG_AGND
PWR_CHG_IOUT

SC220P50V2JN-3GP
PC4011

PR4026

DY 100KR2J-4-GP

BQ24727RGRR-GP

IOUT

8K45R2F-2-GP
PR4028

CHG_ON#

ACOK#

PC4016
SCD1U25V2KX-GP

PWR_CHG_REGN

21

74.24727.073
PR4005

1
5
6
7
8

DY

D01R3721F-GP-U

SCD1U50V3KX-GP

NC#11

1
2
PR4024
7D5R2F-GP

84.08884.A37
2nd = 84.00412.037

SC10U25V5KX-GP

PWR_CHG_SRN

PU4005
2

SC10U25V5KX-GP

12

PR4025
10R2F-L-GP
1

BT+

PR4017

BT+_R

SC10U25V5KX-GP

PWR_CHG_SRP

S
S
S
G

11

13

FDMC8884-GP-U

SRP
ILIM

D
D
D
D

PL4001 change to 7*7*3

SDA

SRN

DY 10KR2F-L1-GP

PWR_CHG_LODRV

PC4019

10

PR4020
100KR2F-L2-GP
PWR_CHG_AD_OFF

15

SCD1U25V2KX-GP

PWR_CHG_ILIM

LODRV

PC4013
SC3300P50V2KX-1GP

PWR_CHG_BAT_SDA

CHG_AGND
3D3V_AUX_S5

SCL

PWR_CHG_PHASE

PG4004
GAP-CLOSE-PWR-3-GP

19

Charger Current=1.4~3.6A

PG4003
GAP-CLOSE-PWR-3-GP

PWR_CHG_BAT_SCL

DY

68.4R71C.10K
2nd = 68.4R710.20D

PHASE

PWR_CHG_CMPIN

CHG_AGND

CMPIN

PWR_CHG_HIDRV

PL4001
IND-4D7UH-173-GP
18

HIDRV

CMPOUT

3D3MR2J-GP

PR4002

MAG. 7*7*3
DCR: 37~40mOhm
Idc : 5.5 A , Isat : 10A

REGN

PR4001
100KR2F-L1-GP

R2

16

STOP_CHG

PC4010
SCD01U50V2KX-L-GP

PR4010
49K9R2F-L-GP

84.08884.A37
2nd = 84.00412.037

PWR_CHG_BTST

83.R0203.08F
2nd = 83.1R003.I8F

17

PU4004
2

SC1U16V3KX-2GP

5
6
7
8
BTST

PC4009
1

ACDET

CH520S-30PT-GP

PC4006

4
3
2
1

PD4003
2PWR_CHG_BTST_R
K

0R3J-4-GP

PR4008
1

PC4025

1
2

PWR_CHG_ACN

ACP

10KR2F-L1-GP PWR_CHG_ACDET6

VCC

CHG_AGND

R1

20
PR4031

DY

S
S
S
G

3D3V_AUX_S5
PR4007
12K4R2F-GP

PWR_CHG_IOUT

PU4003

PC4017
SCD047U25V2KX-GP

CHG_AGND

PC4005

FDMC8884-GP-U

316KR2F-L-GP

PWR_CHG_REGN

PC4004
SCD1U50V3KX-GP

ACN

CHG_AGND

D
D
D
D

PC4001
SCD47U25V3KX-1GP

PWR_CHG_ACP

PWR_CHG_VCC

2
10R5J-GP

SCD1U25V2ZY-1GP

PR4015

SC4D7U25V5KX-GP

PR4006

SC4D7U25V5KX-GP

27

2N7002KDW-GP

100K

PQ4007
2N7002A-7-GP

K
A

PD4002
P6SBMJ27APT-GP

83.P6SBM.DAG
2nd = 83.P6SMB.JAG
3rd = 83.P6SMB.CAG

PR4011
470KR2J-L1-GP

118k

Delete PC4008
Wayler , 2011-1208

PU4002
P1403EV8-GP

84.P1403.B37

PWR_CHG_ACOK

2nd = 84.DM601.03F
AD+

120w

8
7
6
5

100K

PR4009
1
DY 2
0R2J-L-GP

100K

60.4k

41.2k

90w

PQ4001
3

SCD1U50V3KX-GP
PC4002

80w

D
D
D
D

S
S
S
G

1
2
3
4

AD+

PG4002
GAP-CLOSE-PWR-3-GP

PG4001
GAP-CLOSE-PWR-3-GP

AD+_G_1

100K

AD+_G_2

10KR2F-L1-GP

DC_IN_D

12.4K

D01R3721F-GP-U

84.P1403.B37

PR4022

R2

1
PR4021
100KR2F-L2-GP

10KR2F-L1-GP

65w

PR4004

1
2
3
4

P1403EV8-GP

PR4023

PU4001
D
D
D
D

8
7
6
5

A8( ANNIE/ASTRO)
PR4007,PR4001
R1

DCBATOUT
BT+

AD+

AD+ total power

AD+_TO_SYS

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CHARGER BQ24707A
Size
Custom
Date:
5

Document Number

Rev

-1

Petra Uma

Tuesday, July 10, 2012

Sheet
1

40

of

108

DCBATOUT_2

PWR_3D3V_DCBATOUT

2
GAP-CLOSE-PWR
PG4102
2

PWR_5V3D3V__EN0

PWR_3D3V_EN

EC change

DCBATOUT_2

PWR_3D3V_DCBATOUT

1
2

16
VIN

PWR_5V_BOOT1

UGATE2

UGATE1

21

PWR_5V_UGATE1

PWR_3D3V_PHASE2

11

PHASE2

PHASE1

20

PWR_5V_PHASE1

PWR_3D3V_LGATE2

BOOT2

BOOT1

19

PWR_5V_LGATE1

VOUT1

24

PWR_5V_VOUT1

PWR_3D3V_FB2

PWR_5V_FB1

PU4105
FDMC8878-GP

ENC

Vout = 2 * ( 1 + R1/R2 )
= 2 * ( 1 + 6.8K / 10K)
= 3.36V
Modify Description

PWR_5V3D3V_VREF

3D3V_AUX_S5

2 PR4118 1
0R0402-PAD

5V_AUX_S5
1

4
3
2
1

1 PR4120 2
0R0402-PAD

PG4123
2

PR4114

GAP-CLOSE-PWR

-1_20120223

R1

0R2J-L-GP

DY

PR4115
33KR2F-2-GP

PWR_5V_FB1_R
2

PC4126

PC4128
SC18P50V2JN-1-GP

DY
1

Close to VFB Pin (pin5)

77.52271.09L
2ND = 77.52271.07L

SC10U10V3MX-GP

PC4125
SC4D7U6D3V5KX-3GP

PR4116
10KR2F-L1-GP

PT4102
SE220U6D3VM-30-GP

3D3V_AUX_S5

R2

Modify Description

PR4119
21K5R2F-GP
2

GAP-CLOSE-PWR

DY

PC4120

3V_5V_POK 19

PWR_5V3D3V_ENC

1 2

8
PG4122
2

1PWR_5V3D3V_VREG5 17

1PWR_5V3D3V_VREG3

3D3V_AUX_S5

PWR_3D3V_FB2_R
PC4124
SC18P50V2JN-1-GP

DY

25
18

PR4110
100KR2J-4-GP

VREG5

GND

SKIPSEL
VREG3

TONSEL

PWR_5V_ENTRIP1

15

PGND

PG4124

REF

DY

ENTRIP1

84.08878.A30
2nd = 84.08065.B37

23

PGOOD

ENTRIP2

1 2

EN

PWR_5V3D3V_TONSEL

PWR_5V3D3V_SKIPSEL14

0R2J-L-GP

R2

FB1

DY

PC4122

SCD22U10V2KX-1GP

PR4111
6K8R2F-2-GP

PR4112

D
D
D
D
S
S
S
G

PR4111 7.32K changee to 6.8K

R1

FB2

3D3V_S5
1
2
3
4

5
6
7
8

LGATE1

VOUT2

Iomax=6A
OCP>9A

5V_PWR

68.2R21B.10J
2nd = 68.2R210.20B

8
7
6
5

LGATE2

2 PWR_5V3D3V__EN0 13
820KR2F-GP
PWR_3D3V_ENTRIP2 6
PWR_5V3D3V_VREF
3
1
PR4109

GAP-CLOSE-PWR
PG4120
2

PL4102
IND-2D2UH-122-GP

S
S
S
G

77.52271.09L
2ND = 77.52271.07L

PU4102
FDMC8878-GP

PC4116

SCD1U50V3KX-GP

PT4101
SE220U6D3VM-30-GP

84.08878.A30
2nd = 84.08065.B37

GAP-CLOSE-PWR-3-GP

12

PWR_3D3V_VOUT2

D
D
D
D

PG4121

5
6
7
8

8
7
6
5
D
D
D
D
S
S
S
G
1
2
3
4

1
2

1
2

1
2
1

22

10

PC4118
SCD1U25V3KX-L-GP
2PWR_5V_BOOT1_1 1
2

PC4114

SCD1U25V3KX-L-GP

84.08884.A37
2nd = 84.08067.A37

PR4106
2D2R3-1-U-GP

PWR_3D3V_UGATE2

PU4104
FDMC8884-GP-U

SC4D7U25V5KX-GP

74.08223.B73

PR4105
PC4115
2D2R3-1-U-GP
SCD1U25V3KX-L-GP
1
2PWR_3D3V_BOOT1
1
2PWR_3D3V_BOOT2 9

PC4111

S
S
S
G

PC4113
SCD01U50V2KX-L-GP
D
D
D
D

PL4101
IND-2D2UH-122-GP

GAP-CLOSE-PWR-3-GP

SCD1U50V3KX-GP

PU4101
FDMC8884-GP-U

GAP-CLOSE-PWR
PG4119
2

PWR_5V_DCBATOUT

PU4103
RT8223MZQW-GP-U

84.08884.A37
2nd = 84.08067.A37

Iomax=5A
OCP>7.5A

SA_20111006

68.2R21B.10J
2nd = 68.2R210.20B

3D3V_PWR

PC4119

GAP-CLOSE-PWR

SC4D7U25V5KX-GP

PC4110
SC4D7U25V5KX-GP

DY

SC4D7U25V5KX-GP

SCD1U25V3KX-L-GP

PC4112

GAP-CLOSE-PWR
PG4118
2

Change power source

Wayler.2011.1209

Option for non-IOAC

PC4129

EC change

PU4103 change to cost down version

PWR_3D3V_EN

0R2J-L-GP

GAP-CLOSE-PWR
PG4117
2

DY

DY

PWR_5V_EN 1 PR4130 2

GAP-CLOSE-PWR
PG4108
2

PC4108
SCD33U6D3V2KX-1-GP

2N7002KDW-GP

GAP-CLOSE-PWR
PG4116
2

GAP-CLOSE-PWR

3D3V_SRC_EN 27

DY

10KR2J-L-GP

84.2N702.A3F
2nd = 84.DM601.03F

GAP-CLOSE-PWR
PG4107
2

PC4109
SC18P50V2JN-1-GP

PR4127
69K8R2F-GP

2 PWR_5V_EN
10KR2J-L-GP
PWR_3D3V_ENTRIP2_R

2N7002KDW-GP

PR4129
750KR2F-GP

PR4123
1

5V_S5_EN

PWR_5V3D3V__EN0_G5

DY

36

PWR_3D3V_ENTRIP2 1 PR4108 2
88K7R2F-GP

PC4127
SC18P50V2JN-1-GP

PWR_5V3D3V__EN0_G2

4
PR4122

GAP-CLOSE-PWR

PG4105
2
GAP-CLOSE-PWR
PG4106
2

PG4115
2

3D3V OCP setting

5V_S5
1

PQ4101

4
3
2
1

3rd = 84.2N702.F3F

GAP-CLOSE-PWR

PR4128
40K2R2F-GP

84.2N702.A3F
2nd = 84.DM601.03F

GAP-CLOSE-PWR
PG4114
2

GAP-CLOSE-PWR
PG4104
1
2

Vz=3.9V

PU4106
PWR_5V_ENTRIP1

1 PR4107 2
84K5R2F-GP

GAP-CLOSE-PWR
PG4113
2

PWR_5V_ENTRIP1_R

5V OCP setting

GAP-CLOSE-PWR
PG4103
1
2

GAP-CLOSE-PWR
PG4112
2

PWR_5V_DCBATOUT

GAP-CLOSE-PWR
PG4111
2

DCBATOUT_2

Change power source

5V_PWR

1DCBATOUT_PD1
A

PG4101
2

PD4105
MMPZ5228BPT-GP

PR4125
100KR2F-L1-GP

GAP-CLOSE-PWR
PG4110
2

DCBATOUT_2

DCBATOUT_2

PG4109
2

Change power source

3D3V_PWR

3D3V_SRC

Close to VFB Pin (pin2)

Vout = 2 * ( 1 + R1/R2 )
= 2 * ( 1 +33K / 21K)
= 5.14V

2 PR4121 1
0R0402-PAD

TONSEL

GND

CH1

CH2

200kHz

250kHz

<Core Design>

VREF
VREG3 or VREG5

300kHz

375kHz

400kHz

500kHz

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

SKIPSEL

VREG3 or VREG5

VREF(2V)

Operating
Mode

OOA Auto Skip

Auto Skip

GND

Title

5V/3D3V(RT8223M)

PWM only

Size
Custom

Document Number

Rev

-1

Petra Uma

Date: Tuesday, July 10, 2012

Sheet
E

41

of

103

SSID = CPU.Regulator

1
PR4245

VSSSENSE

VSSSENSE_R

2
0R0402-PAD

VSS_AXG_SENSE_R
PC4201
2

1
PR4243

2
0R0402-PAD

VSS_AXG_SENSE 9

2
0R0402-PAD

VCC_AXG_SENSE

PC4202
2

1
SCD01U50V2KX-L-GP

SCD01U50V2KX-L-GP
1
PC4203
8

VCCSENSE

PC4204
2
1

PWR_VCORE_FB_4

2
0R0402-PAD

PR4246

2 SC330P50V2KX-3GP

DY

SC330P50V2KX-3GP
PWR_VCORE_FBG_4

PWR_VCORE_FB_3

PC4205
1

PC4205 package change to 0402

1
PR4244

Setting LoadLine

1 PR4201 2
2KR2F-3-GP

PWR_VCORE_FBG_3

Setting GFX LoadLine

2 PR4202 1
2KR2F-3-GP

SC680P50V2KX-2GP
PC4207
1
2

PR4203
1
2
267KR2F-GP
PWR_VCORE_FB_2

SC150P50V2KX-GP

PR4204
1

SC33P50V2JN-3GP

DY

PR4206
1 267KR2F-GP
2

2
PWR_VCORE_FBG_1

PR4208
1 499R2F-2-GP
2

PC4208
2
1

PWR_VCORE_FBG_2

PC4211

SC470P50V2KX-3GP

PR4209
42K2R2F-L-GP

PC4206 DY

2K61R2F-1-GP

PWR_VCORE_FB_1
PR4207
1 499R2F-2-GP
2

PC4210

PC4209
1
2

PWR_VCORE_COMP

PR4205
2
1K91R2F-1-GP

PC4206
SC330P50V2KX-3GP
2
1

SC470P50V2KX-3GP

SC150P50V2KX-GP
PWR_VCORE_COMPG

PC4212
SC47P50V2JN-3GP

DY

PR4210
154KR2F-GP

PC42105V_S5
package change to 0402

2
1

PR4212
0R0402-PAD

PR4213
2K61R2F-1-GP

NTC Place near high side MOSFET of Phase1

PWR_VCORE_NTC_1

PR4224
1 3K83R2F-GP
2

PR4223
1 27K4R2F-GP
2

PWR_VCORE_NTC

PR4225
1 NTC-470K-9-GP
2

PWR_VCORE_NTCG

44

1
2
19
36

PWR_VCORE_GOODG

18
37

PWR_VCORE_COMP
PWR_VCORE_COMPG

21
29

PWR_VCORE_UGATE1

23
27

PWR_VCORE_LGATE1

34
32

PWR_VCORE_LGATEG
PWR_VCORE_UGATEG

24
35

PWR_VCORE_PWM3
PWR_VCORE_PWM2G

PR4217
1K91R2F-1-GP

IMVP_PWRGD

PWR_VCORE_UGATE1

43

PWR_VCORE_LGATE1

43

PWR_VCORE_LGATEG 44
PWR_VCORE_UGATEG 44

DY

5V_S5

2
20R0402-PAD
0R2J-L-GP

PR4240 DY
74.95836.B33
Wayler 12.06
PU4201 change to V1.7 (74.95836.B33)
ISL95836HRTZ-2-GP

1
PR4220 1
PR4240

28,36

PC4224
SC1U10V2KX-1GP

31

20
30
BOOT1
BOOT2

BOOT1G

FB
FBG

10
4

PR4222
1 NTC-470K-9-GP
2

PWR_VCORE_VR_HOT#

PR4221
1 3K83R2F-GP
2

16
39

17
38

PHASE1G

PWM3
PWM2G
GND

33

NTC
NTCG

44 PWR_VCORE_PHASEG

LGATE1G
UGATE1G
PHASE1
PHASE2

VR_ON

PWR_VCORE_PHASEG

ISEN1G
ISEN2G

41

PWR_VCORE_ISEN2G
0R0402-PAD

22
28

SDA

PWR_VCORE_PHASE1

LGATE1
LGATE2

PWR_VCORE_ISEN2G

43 PWR_VCORE_PHASE1

UGATE1
UGATE2

PWR_VCORE_ISEN2
0R0402-PAD

ISEN1
ISEN2
ISEN3/FB2

PWR_VCORE_VR_ON

1
PR4241

COMP
COMPG

SCLK

1
PR4239

2
3

PGOOD
PGOODG

ALERT#

13
12
11

PWR_VCORE_BOOTG

PR4216
1K91R2F-1-GP

ISUMPG
ISUMNG

PWR_VCORE_ISEN2
5V_S5

ISUMP
ISUMN

1
40

43

SA:change power plane

PWR_VCORE_SDA

14
15

PWR_VCORE_ISUMPG
PWR_VCORE_ISUMNG

PWR_VCORE_BOOT1

3D3V_S0

RTN
RTNG

25

26

VDD
PWR_VCORE_ISUMN

PWR_VCORE_BOOTG

PWR_VCORE_SCLK

44 PWR_VCORE_ISUMPG
44 PWR_VCORE_ISUMNG

VCCP

1
2

Setting OCP
PR4218 change to 453 ohm
Wayler 12.06

PC4217
SCD1U10V2KX-L-GP

VR_HOT#

2
2

2
1
2

PU4201

PWR_VCORE_FBG
PWR_VCORE_FB

PR4218
453R2F-1-GP
2

PC4215

PWR_VCORE_VCCP

PC4214

SC1U10V2KX-1GP

VSUM-

PC4213
SCD15U10V2KX-GP

PR4215
NTC-10K-27-GP

43

PC4216
SCD01U50V2KX-L-GP

Place near choke of Phase1

PR4214
11KR2F-L-GP

SC1U10V2KX-1GP

ISUMP_1

PWR_VCORE_VDD

PWR_VCORE_BOOT1

PR4211
1R2F-GP

VSUM+

43

PC4211 package change to 0402

Setting IMax

1D05V_VTT

NTC place near high side MOSFET of Phase1

PR4226
2 27K4R2F-GP
1

PWR_VCORE_NTCG_1

5,27 H_PROCHOT#

2 PC4226
SCD1U10V2KX-L-GP

2
0R0402-PAD

2
0R0402-PAD
2
0R0402-PAD
2
0R0402-PAD

PR4231

-1_20120223

PR4228
54D9R2F-L1-GP

PC4225
SCD1U10V2KX-L-GP

PR4230
130R2F-1-GP
2

PR4227
75R3J-L-GP

PR4229
1 499R2F-2-GP
2

1D05V_VTT

Close to VR

SA:change to be 0603

8 VR_SVID_ALERT#
8 H_CPU_SVIDCLK
8 H_CPU_SVIDDAT

27,37,48 ALL_POWER_OK

PR4232
1
PR4233
1
PR4234

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Custom
Date:
5

ISL95836_CPU_CORE(1/3)
Document Number

Rev

Petra Uma

Tuesday, July 10, 2012

Sheet

42

of

-1

102

BOM control
PW R_VCCCORE1_DCBATOUT

PW R_VCCCORE1_DCBATOUT

1
2

1
2

1
2
2

PG4301
2

GAP-CLOSE-PW R
PG4304
2

GAP-CLOSE-PW R
PG4307
2

GAP-CLOSE-PW R
PG4308
2

GAP-CLOSE-PW R
PG4309
2

GAP-CLOSE-PW R
PG4310
2

PR4307
1 1R2F-GP2
PR4311
2 3K65R2F-1-GP
1

PW R_VCCCORE1_DCBATOUT

VSUM-

42

VSUM+

42

PT4308
SE47U25VM-11-GP

DY

GAP-CLOSE-PW R

DY

PG4303

1
PWR_VCCCORE_VSUM+_1

84.03664.037
(FDMS3664S)

Mount

PG4302

PT4303
ST470U2VDM-5-GP-U1

PU4302

84.03664.037
(FDMS3664S)

PT4302
ST470U2VDM-5-GP-U1

PU4301

1
2

2
L-D36UH-1-GP

GAP-CLOSE-PWR-3-GP

2nd source

DCBATOUT

GAP-CLOSE-PWR-3-GP

BOM control
Main source

VCC_CORE

PL4301

68.R3610.20A
2nd = 68.R3610.20C

42 PW R_VCORE_LGATE1

DY

DY

Vcc_core
Iccmax=33A
Itdc=25A
OCP>40A

PC4305
SC10U25V5KX-GP

1st = 84.03664.037

DY

PC4306

FDMS3600-02-RJK0215-COLAY-GP

PC4304

FDMS3600-02-RJK0215-COLAY-GP

42 PW R_VCORE_UGATE1
42 PW R_VCORE_PHASE1

7
6
5

PWR_VCCCORE_VSUM-_1

1
2

9
7
6
5

PC4303

SC10U25V5KX-GP

PC4302

SC10U25V5KX-GP

PC4301
SCD22U25V3KX-GP

2
3
4
10

SC10U25V5KX-GP

PU4302

2
3
4
10

PU4301

1st = 84.03664.037
PW R_VCCCORE_BOOT1_1

SC10U25V5KX-GP

PR4301
1 2D2R3-1-U-GP
2

42 PW R_VCORE_BOOT1

PT4307
SE47U25VM-11-GP

EC change

DCBATOUT_2

PG4311
2

GAP-CLOSE-PW R
PG4312
2

GAP-CLOSE-PW R
PG4313
2

GAP-CLOSE-PW R
PG4314
2

GAP-CLOSE-PW R
PG4315
2

GAP-CLOSE-PW R
PG4316
2

GAP-CLOSE-PW R
PG4320
2

GAP-CLOSE-PW R
PG4321
2

Add Gaps

PT4309
SE47U25VM-11-GP

GAP-CLOSE-PW R

<Core Design>

DY

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ISL95836_CPU_CORE(2/3)

Size
A3

Document Number

Date:

Tuesday, July 10, 2012

Petra Uma

Rev
Sheet
1

43

of

-1

102

PU4401

1
PR4401
1 2D2R3-1-U-GP
2

9
PWR_GFXCORE_BOOT_1

1
2

1
2

9
7
6
5

7
6
5

DY
FDMS3600-02-RJK0215-COLAY-GP

FDMS3600-02-RJK0215-COLAY-GP

PC4401
SCD22U25V3KX-GP

DCBATOUT_2

2
3
4
10

1st = 84.03664.037

VCC_GFXCORE

1st = 84.03664.037 2nd = 68.R3610.20C

68.R3610.20A

PC4405
DY
SCD068U16V2KX-GP
PC4410_1
2
1

PC4406
SCD1U10V2KX-L-GP
PR4406
1 1R2F-GP2

GAP-CLOSE-PWR
PG4404
2

GAP-CLOSE-PWR
PG4405
2

GAP-CLOSE-PWR
PG4406
2

GAP-CLOSE-PWR
PG4407
2

GAP-CLOSE-PWR
PG4408
2

GAP-CLOSE-PWR
PG4409
2

GAP-CLOSE-PWR
PR4402
1 549R2F-GP
2

DY
PR4404
464R2F-GP
1
2

VSUMG-

PWR_VCORE_ISUMNG

42

DY

PWR_GFXCORE1_ISN_R

84.03664.037
(FDMS3664S)

2
1

PU4402

PWR_GFXCORE1_ISP_R

Mount

PT4402

ST330U2VDM-8-GP-U

84.03664.037
(FDMS3664S)

ST330U2VDM-8-GP-U

PU4401

PG4403
GAP-CLOSE-PWR-3-GP

2nd source

Main source

PG4402
GAP-CLOSE-PWR-3-GP

BOM control

PT4401
42 PWR_VCORE_LGATEG

PL4401
1
2
L-D36UH-1-GP

42 PWR_VCORE_PHASEG

Vcc_gfxcore
Iccmax=33 A
TDC = 21.5A
OCP>40A

PWR_GFXCORE1_DCBATOUT

PG4401
2

42 PWR_VCORE_BOOTG

PU4402

2
3
4
10

PC4404
SC10U25V5KX-GP

42 PWR_VCORE_UGATEG

PC4403
SC10U25V5KX-GP

BOM control

PC4402
SC10U25V5KX-GP

PWR_GFXCORE1_DCBATOUT

PR4405
NTC-10K-27-GP

VSUMG+

PC4408
SCD15U10V2KX-GP

PC4407
SCD022U16V2KX-3GP

PR4409
2K61R2F-1-GP
PR4408
2 3K65R2F-1-GP
1

1
2

PR4407
11KR2F-L-GP

VSUMG+_1

Setting GFX OCP

1
PR4410

2
0R0402-PAD

PWR_VCORE_ISUMPG

42

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Custom
Date:
5

ISL95836_CPU_CORE(3/3)
Document Number

Rev

Petra Uma

Tuesday, July 10, 2012

Sheet

44

of

-1

102

TPS51218D for 1D05V

1D05V_VTT

GAP-CLOSE-PW R
PG4502
2

GAP-CLOSE-PW R
PG4514
2
1

PG4506
2

GAP-CLOSE-PW R
PG4503
2

GAP-CLOSE-PW R
PG4515
2
1

GAP-CLOSE-PW R
PG4507
2

GAP-CLOSE-PW R
PG4504
2

GAP-CLOSE-PW R
PG4516
2
1

GAP-CLOSE-PW R
PG4508
2

GAP-CLOSE-PW R

GAP-CLOSE-PW R
PG4509
2

GAP-CLOSE-PW R
PG4510
2

GAP-CLOSE-PW R
PG4511
2

GAP-CLOSE-PW R
PG4512
2
PU4502
FDMS7698-GP

1D05V_PW R

PL4501

PU4503
FDMS0308AS-GP

PR4506
10R2F-L-GP
VTT_SENSE_L

S
S
S

84.00308.B30
2nd = 84.08058.037

PR4507

PT4504
PT4503
SE330U2VDM-L-GP
SE330U2VDM-L-GP

79.33719.L01
79.33719.L01

10KR2F-L1-GP

S
2

DY

PC4509

DY

DY

PC4508

SD:
7x7mm

IND-D42UH-4-GP

C4502
SC1U10V2KX-1GP

74.51218.073

DCR=1.5mohm

5V_S5

PW R_1D05V_LGATE

TPS51218DSCR-GP-U2

PW R_1D05V_BOOT_R 1

PW R_1D05V_BOOT 1
PW R_1D05V_UGATE
PW R_1D05V_PHASE

11
10
9
8
7
6

SC18P50V2JN-1-GP

PR4503
470KR2F-GP

GND
VBST
DRVH
SW
V5IN
DRVL

D
D
D
D

SC1KP50V2KX-1GP

PGOOD
TRIP
EN
VFB
RF

SCD1U50V3KX-GP

PC4505

1
2
3
4
5

54K9R2F-L-GP

PW R_1D05V_IMAX
PW R_1D05V_EN
PW R_1D05V_VFB
PW R_1D05V_CCM

S Pana. 0.42uH 7*7*4

PC4503
SCD1U25V3KX-L-GP

1 PR4512 2
0R0402-PAD
1

46,47 RUNPW ROK

1 PR4504 2

37,48 1D05VTT_PW RGD

PR4505
2D2R3-1-U-GP

Iomax = 20.645A
TDC = 14.45 A
OCP > 26.83A

3
2
1

G
PU4501

10KR2J-L-GP

Freq=360KHz

3D3V_S0

PR4504 change to 54K9 , OCP > 27A

2012-0130 , Wayler.

1
2

PR4516

S
S
S

DY

PC4511

PT4501
SE47U25VM-11-GP

D
D
D
D

84.07698.037
2nd = 84.08065.037

GAP-CLOSE-PW R

PC4507

2
GAP-CLOSE-PW R

5
6
7
8

GAP-CLOSE-PW R

PC4506

5
6
7
8

PC4504

SC4D7U25V5KX-GP

GAP-CLOSE-PW R
PG4523
2

PG4520
2

SC4D7U25V5KX-GP

SCD1U25V3KX-L-GP

GAP-CLOSE-PW R
PG4522
2

PW R_DCBATOUT_1D05V

GAP-CLOSE-PW R

SCD01U25V2KX-3GP

PG4521
2

PG4518
2

3
2
1

PW R_DCBATOUT_1D05V

DCBATOUT

GAP-CLOSE-PW R

1D05V_PW R
PG4513
2

1D05V_VTT
PW R_DCBATOUT_1D05V
DCBATOUT_2
PG4501
1
2

-1_20120221
1

PW R_1D05V_VFB

PR4508
20KR2F-L-GP

VCCIO_SENSE

PC4510
SC1000P50V3JN-GP-U

PR4509
10R2F-L-GP

DY

VSSIO_SENSE 8

Vout=0.704*(1+R1/R2)

0R2J-L-GP

PR4511
VSS_SENSE_L

VSS_SENSE_L

0R2J-L-GP

1
2

DY

DY

PR4510
VTT_SENSE_L

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DC to DC_1D05V(TPS51218D)

Size
A3

Document Number

Date:

Tuesday, July 10, 2012

Rev

-1

Petra Uma
Sheet
1

45

of

103

1D5V_PWR

SSID = PWR.Plane.Regulator_1p5v0p75v

1D5V_S3

PG4610
2

PG4618
2

PWR_DCBATOUT_1D5V
PG4601
2

GAP-CLOSE-PWR
PG4611
2
1

GAP-CLOSE-PWR
PG4619
2

GAP-CLOSE-PWR
PG4602
2

GAP-CLOSE-PWR
PG4612
2
1

GAP-CLOSE-PWR
PG4620
2

GAP-CLOSE-PWR
PG4603
2

GAP-CLOSE-PWR
PG4613
2
1

GAP-CLOSE-PWR
PG4621
2

GAP-CLOSE-PWR
PG4614
2
1

GAP-CLOSE-PWR
PG4622
2

GAP-CLOSE-PWR
PG4615
2

GAP-CLOSE-PWR

GAP-CLOSE-PWR
PG4616
2

GAP-CLOSE-PWR
PG4617
2

DCBATOUT_2

GAP-CLOSE-PWR

RT8207L for 1D5V

PR4604
2
1
5D1R2F-GP

5V_S5

PC4606
SC1U10V2KX-1GP

PWR_DCBATOUT_1D5V

19

PWR_1D5V_LGATE

LGATE

0D75V_S0

PG4608
2

1
2

2
5
6
7
8

3
2
1

5V_S5

R1

PR4608
30K9R2F-GP

VTTREF
5

DY

EC change

PC4610
SC18P50V2JN-1-GP

77.53971.01L
2nd = 79.3971V.6AL

R2

Vout=0.75*(1+R1/R2)

PR4609
30KR2F-GP

GND

GND

PWR_1D5V_FB

PT4602
SE390U2D5VM-12-GP

RT8207LZQW-GP

1 PR4607 2
0R0402-PAD

DDR_VREF_S3

Close to PIN9
PC4608
SCD033U16V2KX-GP

37 0D75V_EN
DDR_VREF_PWR

PWR_1D5V_VDDQ

74.08207.D73

1PWR_1D5V_VTTREF

+0.75VS
Iomax: 1.2A

DEM

84.00308.B30
2nd = 84.08058.037

PC4613

Iomax=1A
OCP>1.5A
Close to output cap pin1, not
inside of the output cap

FB

VTTSNS

25

VTT

S
S
S

24

FDMS0308AS-GP
G

MODE
VDDQ

DDR_VREF_PWR

18
17

PGND
NC#17

DY

VTTGND

SD:
7x7mm
PU4603

GAP-CLOSE-PWR

Close to pin23

68.R681A.10A
2nd = 68.R6810.20B

NC#7

1
PWR_1D5V_VDDQ

1D5V_PWR

2
IND-D68UH-36-GP

VLDOIN

23
7

DCR= 5 ~ 5.5 mohm

Idc=15.5A, Isat=25A

PWR_1D5V_PHASE

20

PWR_1D5V_PHASE_L

3
2
1

14

15

PHASE

1
2
2D2R3-1-U-GP

SC1U16V3KX-5GP

GAP-CLOSE-PWR
PG4607
1
2

VDD

CS

PWR_1D5V_VTTIN

UGATE

PWR_1D5V_UGATE

S3

GAP-CLOSE-PWR
PC4603
PG4606
SC10U6D3V5MX-L1-GP
2

PWR_1D5V_BOOT

IccMAX = 18.38A
IccTDC = 12.86A
OCP > 23.89A

PL4601

10

22
21

S CYNTEC. 0.68uH 7*7*3

S5

PWR_0D75V_EN
PG4605
2

BOOT

PGOOD
TON

PR4606

D
D
D
D

1D5V_S3

11

VDDP

16

1
2

20100728

12

PC4609
SCD1U25V3KX-L-GP

S
S
S

1PR4610
2PWR_1D5V_TON
620KR2F-GP
PWR_1D5V_EN

4
PU4601

13

45,47 RUNPWROK

1D5V_S3

PC4615

PR4602
10KR2F-L1-GP

PWR_DCBATOUT_1D5V

D
D
D
D

84.07698.037
2nd = 84.08065.037

Close to pin23

5
6
7
8

PU4602
FDMS7698-GP

3D3V_S5

1
1

1
2

5V_S5

SC4D7U25V5KX-GP

C694
SC1U10V2KX-1GP

DY
SC4D7U25V5KX-GP

1 PR4605 2
0R0603-PAD

PC4616 PC4617

SCD1U25V3KX-L-GP

PWR_1D5V_VDDP

PWR_1D5V_CS

DY

GAP-CLOSE-PWR
PC4614
SC4D7U25V5KX-GP

PC4612
SCD1U10V2KX-L1-GP

PR4603

PWR_1D5V_EN

2
0R0402-PAD

PC4602

8K87R2F-2-GP

SC1KP50V2KX-1GP

1
PR4612

PWR_1D5V_VCC5

19,27 PM_SLP_S4#

1D5V_PWR

1 PR4615 2
0R0402-PAD

PWR_0D75V_EN

GAP-CLOSE-PWR

PG4609
2

GAP-CLOSE-PWR

PC4605
SC10U6D3V5MX-L1-GP

SC10U6D3V5MX-L1-GP

PC4604

DY
A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

RT8207
Size
Custom
Date:
5

Document Number

Rev

-1

Petra Uma

Tuesday, July 10, 2012

Sheet
1

46

of

103

SSID = PWR.Plane.Regulator_1p8v
RT9025 for 1D8V_S0

3D3V_S0

5V_S5

1
2

Vo(cal.)=1.812V

1
PR4705
16K2R2F-GP

GAP-CLOSE-PWR
PG4702
2

1D8V_S0

GAP-CLOSE-PWR
PC4706

DY
B

2nd = 74.09661.07D

PC4705
2

2
1
2

PC4707
SCD1U10V2KX-L1-GP

PWR_1D8V_ADJ

74.09025.B3D

PC4704
2

PR4704
20K5R2F-GP

VDD
VIN
EN
PGOOD

5
6
7
8
9

4
3
2
1

NC#5
VOUT
ADJ
GND
GND

RT9025-25ZSP-GP
B

PG4701
2

PU4701

SC10U6D3V5MX-L1-GP

45,46 RUNPWROK

1
1D8V_LDO

SC10U6D3V5MX-L1-GP

PWR_1D8V_EN

1 PR4706 2
0R0402-PAD

PC4702
SC1U10V2KX-1GP

SC100P50V2JN-L-GP

19,27,29,36,37 PM_SLP_S3#

SC10U6D3V5MX-L1-GP

PC4701

Iomax>2.22A
OCP>3A

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

LDO_1D8V(RT9025)
Size
A4

Document Number

Date:
5

Rev

Petra Uma
Tuesday, July 10, 2012

Sheet

-1
47

of
1

103

LDO G978 for VCCSA

D

PU4802

1
2
3
4

D0
GND
D1
VEN/MODE
VO#3
POK
VO#4
VPP
VIN

5V_S0

9
8
7
6
5

PW R_VCCSA_EN
D85V_PWRGD

SA_20111223A
1D05V_VTT_CPU

G978F11U-GP
PWR_G978_VIN

74.00978.031

PC4808
SC22U6D3V5MX-L3-GP

PG4810
2

GAP-CLOSE-PW R
PG4811
2

GAP-CLOSE-PW R
PG4812
2

GAP-CLOSE-PW R
PG4813
2

0D85V_LDO

0D85V_LDO

PWR_VCCSA_VID0
PW R_VCCSA_VID1

PC4809
SC1U10V2KX-1GP

0D85V_PW R

0D85V_LDO

GAP-CLOSE-PW R

1
PR4803

PWM SY8037 for VCCSA

D85V_PW RGD

1
PR4808

PW R_VCCSA_VID0

PW R_VCCSA_EN

DY

2
1KR2F-L-GP
2
0R0402-PAD
2
0R0402-PAD

VCCSA_VID1

VCCSA_VID0

2
0R0402-PAD

VID0

VID1

0.9V

0.8V

VCCSA

0D85V_PW R

1D05VTT_PW RGD 37,45

PC4810
SC1U6D3V2KX-L-1-GP

0.725V

0.675V

0D85V_S0

PG4804
2

GAP-CLOSE-PW R
PG4805
2

GAP-CLOSE-PW R
PG4806
2

GAP-CLOSE-PW R
PG4807
2

GAP-CLOSE-PW R
PG4808
2

GAP-CLOSE-PW R
PG4809
2

PR4807
10KR2J-L-GP

DY

ALL_POW ER_OK 27,37,42

1
PR4801

3D3V_S0

2
0R0402-PAD

1
PR4812
1
PR4804
1
PR4805

PW R_VCCSA_VID1

DY

2
10KR2J-L-GP

Design Current =4 A

DY
2

1
2

1
2

SCD1U25V3KX-L-GP

SC22U6D3V5MX-L3-GP

SC10U6D3V5KX-1GP

DY

GAP-CLOSE-PW R

PC4806

PC4805

PC4804

SC10U6D3V5KX-1GP

PC4803

0D85V_PW R

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

VCCSA SY8037
5

Size
A3

Document Number

Date:

Tuesday, July 10, 2012

Rev

-1

Petra Uma
Sheet
1

48

of

103

SSID = VIDEO
3D3V_S0

F4902
FUSE-1D1A6V-4GP-U

3D3V_CAMERA_S0

69.50007.691

F4901
POLYSW-1D1A24V-GP-U

DCBATOUT_LCD

2
1

1
2

29

INT_MIC_L_R

R4921
1KR2J-L2-GP
3D3V_S0

INT_MIC_L_R
1

1 33R2J-L1-GP
L_BKLT_CTRL 17
3D3V_CAMERA_S0
2 0R0603-PAD
USB_PN3 18
2 0R0603-PAD
USB_PP3 18

DY

EDP

1 R4910 2
0R2J-L-GP

LVDSA_DATA0 17
LVDSA_DATA0# 17

84.2N702.J31
2ND = 84.2N702.031

R4917
100KR2J-4-GP

DP_HPD0_C

AUD_AGND

2
1

1
2

EDP
LCDVDD

3D3V_S0

DP_TXP1_CPU_C
DP_TXN1_CPU_C

EDP 1
EDP 1

2 C4916
2 C4915

SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP

DP_AUXP_CPU_C
DP_AUXN_CPU_C

EDP 1
EDP 1

2 C4911
2 C4912

SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP

DP_TXP0_CPU_C
DP_TXN0_CPU_C

EDP 1
EDP 1

2 C4913
2 C4914

SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP

C4902
SC1U6D3V2KX-L-1-GP

DP_TXP1_CPU 4
DP_TXN1_CPU 4
DP_AUXP_CPU 4
DP_AUXN_CPU 4
DP_TXP0_CPU 4
DP_TXN0_CPU 4
3D3V_S0

RN4908
SRN0J-6-GP
4
3

3D3V_S0

EDP_DDC_DATA
EDP_DDC_CLK

LCDVDD

R4929

LCDVDD

3D3V_S0

EDP#_LVDS_R

1 R4923 2EDP#_LVDS_B B
150KR2J-L1-GP

2
0R0402-PAD

EDP#_LVDS

22

Q4904
MMBT3904-4-GP

84.T3904.C11
2ND = 84.03904.P11

3rd = 84.03904.L06

EDP: pin35 NC
LVDS: pin35 GND

1
2

4
1

NC#4

SY6288C6AAC-GP

74.06288.B7F
2nd = 74.09724.09F

DY
4
3

1
2

SC4D7U6D3V3KX-L-GP
C4908

SC56P50V2JN-2GP
C4909

100KR2J-4-GP
R4914

IN

SC4D7U6D3V3KX-L-GP
C4907

EN
GND
OUT

17 LVDS_VDD_EN

1
2
3

EDP#_LVDS_C

U4901

Layout 40 mil

R4933
10KR2J-L-GP

DY

R4915
10KR2J-L-GP

-1_20120214
Change DUMMY from eDP
to DY (For eDP_EDID)

DP_DDC_DATA_CPU_C
DP_DDC_CLK_CPU_C

RN4907
SRN0J-6-GP
1
4
2
3

LVDS_DDC_DATA_R 17
LVDS_DDC_CLK_R 17
1

1
2

1
R4922
100KR2J-4-GP

2nd = 20.F1860.040

DY

DP_TXP0_CPU_C
DP_TXN0_CPU_C
EDP#_LVDS_R
DP_DDC_DATA_CPU_C
DP_DDC_CLK_CPU_C

DY

R4918
100KR2J-4-GP

DY

DP_AUXP_CPU_C
DP_AUXN_CPU_C

20.F1816.040

DY

DY

4 DP_AUXN_CPU
4 DP_AUXP_CPU

DY

DP_TXP1_CPU_C
DP_TXN1_CPU_C

R4919
100KR2J-4-GP

DY
1

Q4902
2N7002K-2-GP

LVDSA_DATA1 17
LVDSA_DATA1# 17

C4901
SCD1U10V2KX-L1-GP

R4916
100KR2J-4-GP

AUD_GND

LVDSA_DATA2 17
LVDSA_DATA2# 17

EC4906
MLVG0402220NV05BP-GP-U

LVDSA_CLK 17
LVDSA_CLK# 17

PS-CON40-GP

4
2

DP_HPD#

CCD GND

1 R4907 2
0R0402-PAD

DP_HPD0_C

EDP 2 0R2J-L-GP

1 R4908
1 R4909

1D05V_VTT

-1_20120301

USB_CAMERA#
USB_CAMERA

R4920 1
R4902 2

27
AUD_GND

DBC_EN_C
BLON_OUT_C
LCD_BRIGHTNESS

1
2
MODEL_ID_R

2
C4905
SCD1U50V3KX-GP

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
NP2
42

SCD1U50V3KX-GP
C4904

41
NP1
1

C4903
SC10U6D3V3MX-L-GP

SC4D7U25V5KX-GP
C4906

DY

SCD1U10V2KX-L1-GP
EC4903

LCD1

DCBATOUT_LCD

DCBATOUT

69.50007.A31
2nd = 69.50007.A41

2ND = 69.50007.771

EDP_DDC_CLK

RNH491
SRN2K2J-1-GP
Q4901
2N7002KDW-GP

84.2N702.A3F
2nd = 84.DM601.03F
1

DY

SML1_CLK 20,27,28

EDP_DDC_DATA
SML1_DATA 20,27,28

2 R4904 1
10KR2J-L-GP

3D3V_S0

DBC_EN_C
C4910
SC100P50V2JN-L-GP

2
1

100KR2J-4-GP
R4911

1 R4903 2
1KR2J-L2-GP

BLON_OUT

R4906
10KR2J-L-GP
2

DY

1
2

1
2

DY

SC33P50V2JN-3GP
EC4902

DY

SC5D6P50V2CN-1GP
EC4905

DY

SC5D6P50V2CN-1GP
EC4904

LCD_BRIGHTNESS
DP_TXN1_CPU_C
DP_TXP1_CPU_C

27

DY

BLON_OUT_C

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

LCD Connector
Size
A2

Document Number

Date:

Tuesday, July 10, 2012

Rev

-1

Petra Uma
Sheet

49

of

103

CRT DDCDATA & DDCCLK level shift

CRT_DDCCLK_CON

CRT_R

CRT_R

CRT_G

CRT_G

59

CRT_B

CRT_B

59

59

59

2
1

RN5002
SRN2K2J-1-GP

3D3V_S0

RN5003
SRN10KJ-L-GP

3
4

59

CRT_VSYNC_CON

83.R5003.C8F
2ND = 83.R5003.H8H

SCD01U16V2KX-L1-GP
C5012

CRT_HSYNC_CON

3rd = 83.5R003.08F

3D3V_S0

59

CRT_VSYNC_CON

D5001
CH551H-30PT-GP

5V_CRT_S0

59

CRT_HSYNC_CON

5V_HDMI

3
4

CRT_DDCDATA_CON

CRT_DDCCLK_CON

17 CRT_DDC_DATA

CRT_DDCDATA_CON

2
1

CRT_DDCDATA_CON

5V_CRT_S0

17 CRT_DDC_CLK
CRT_DDCCLK_CON
Q5001
2N7002KDW -GP

84.2N702.A3F
2nd = 84.DM601.03F

L5001
BLM18BB220SN-GP

68.00084.A11
C

17 CRT_RED

CRT_R

L5002
BLM18BB220SN-GP

68.00084.A11

C5011

DY SC100P50V2JN-L-GP
2

DY
2

1
1
2

1
2

1
2

1
2

1
2

1
2

8
7
6
5

SC10P50V2JN-4GP
C5006

SC10P50V2JN-4GP
C5005

SC10P50V2JN-4GP
C5004

1
2
3
4

DY

CRT_DDCDATA_CON
CRT_HSYNC_CON
CRT_VSYNC_CON
CRT_DDCCLK_CON
SC18P50V2JN-1-GP
C5010

DY

SC18P50V2JN-1-GP
C5009

CRT_B

SC10P50V2JN-4GP
C5003

SC10P50V2JN-4GP
C5002

SC10P50V2JN-4GP
C5001

RN5004
SRN150F-1-GP

SC100P50V2JN-L-GP
C5008

68.00084.A11
17 CRT_BLUE

CRT_G

2
L5003
BLM18BB220SN-GP

17 CRT_GREEN

5V_S0

CRT_VSYNC

U5001C
TC74VHCT125AFTQK2M-GP

73.74125.F0B
2nd = 73.74125.L13
8

CRT_VSYNC1_1

17 CRT_HSYNC

12

13

5V_S0

14

10

14

5V_S0

17

73.74125.F0B
2nd = 73.74125.L13

U5001A
TC74VHCT125AFTQK2M-GP

73.74125.F0B
2nd = 73.74125.L13

14

14

5V_S0
U5001B
TC74VHCT125AFTQK2M-GP

CRT_HSYNC1_1

1 R5001 2
10R2J-2-GP

CRT_HSYNC_CON

CRT_VSYNC1_1

1 R5002 2
10R2J-2-GP

CRT_VSYNC_CON

U5001D
TC74VHCT125AFTQK2M-GP

73.74125.F0B
2nd = 73.74125.L13
11

CRT_HSYNC1_1
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CRT Connector
5

Size
A3

Document Number

Date:

Tuesday, July 10, 2012

Rev

-1

Petra Uma
Sheet
1

50

of

103

SSID = VIDEO

HDMI Level Shifter & CONNECTOR

HDMI1

20
22
1

HDMI_DATA2_R#
HDMI_DATA2_R
HDMI_DATA0_R#
HDMI_DATA0_R
HDMI_DATA1_R
HDMI_DATA1_R#
HDMI_CLK_R
HDMI_CLK_R#

5
6
7
8

HDMI_DATA1_R#
HDMI_DATA0_R
HDMI_DATA0_R#
HDMI_CLK_R
HDMI_CLK_R#
5V_HDMI

5V_HDMI

3D3V_S0

-1_20120221

5V_S0

1
D

R5110
200KR2J-L1-GP

Q5102
MMBT3904-4-GP

84.T3904.C11
2ND = 84.03904.P11
3rd = 84.03904.L06

1 R5111 2HDMI_HPD_B B
150KR2J-L1-GP

17 HDMI_DATA2_R#
17 HDMI_DATA2_R

HDMI_HPD_E

DY

1 R5129 2
0R0402-PAD

HDMI_PCH_DET

17

Q5105

69.50007.691
2nd = 69.50007.771

22.10296.631

HDMI_PLL_GND

17 HDMI_DATA1_R#
17 HDMI_DATA1_R

F5101
FUSE-1D1A6V-4GP-U

17 HDMI_DATA0_R#
17 HDMI_DATA0_R
C

5V_S0

DDC_CLK_HDMI
DDC_DATA_HDMI

HPD_HDMI_CON

4
3
2
1

RN5115
SRN680J-1-GP

17 HDMI_CLK_R#
17 HDMI_CLK_R

HDMI_DATA2_R#
HDMI_DATA1_R

SKT-HDMI23-45-GP

RN5114
SRN680J-1-GP

1
2
3
4

8
7
6
5

Close to HDMI Connector

HDMI_DATA2_R

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
23
21

G
R5112
10KR2J-L-GP

2N7002A-7-GP

D5103
BAW 56-5-GP

83.00056.Q11
2nd = 83.00056.K11
5V_S0_D1

5V_S0

3
2

4
3

5V_S0_D2

Q5106
2N7002KDW -GP

17 PCH_HDMI_CLK

RN5102
SRN2K2J-1-GP

3D3V_S0

1
2

84.2N702.A3F
2nd = 84.DM601.03F

DDC_CLK_HDMI
DDC_DATA_HDMI

17 PCH_HDMI_DATA

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

HDMI Level Shifter/Connector

5

Size
A3

Document Number

Date:

Tuesday, July 10, 2012

Rev

-1

Petra Uma
Sheet
1

51

of

103

SSID = SATA

SATA HDD Connector

-1_20120223

HDD2

HDD1

23
NP1
1

2 C5602 SATA_RXN0_C
SATA_RXP0_C
2
C5603 Non cable

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NP2
24

C5606
SCD1U10V2KX-L1-GP

Non cable

SC10U25V5KX-GP
C5605

5V_S0

-1_20120301

C5613

C5604

21 SATA_RXN0
21 SATA_RXP0

2
3
4
5
6
7

Non cable

SCD01U16V2KX-L1-GP 1
Non cable 1
SCD01U16V2KX-L1-GP

5V_S0

SATA_TXP0
SATA_TXN0

1 C5610 SATA_TXP0_C
1 C5609 SATA_TXN0_C

Cable
SATA_TXP0
SATA_TXN0

SCD01U16V2KX-L1-GP 1
SCD01U16V2KX-L1-GP 1

21 SATA_RXN0
21 SATA_RXP0

SCD01U16V2KX-L1-GP 1
SCD01U16V2KX-L1-GP 1

21
21

SCD1U10V2KX-L1-GP

SCD01U16V2KX-L1-GP 2
SCD01U16V2KX-L1-GP 2

SC10U25V5KX-GP

21
21

-1_20120301

Non cable

2 C5614 SATA_TXP0_3C
2 C5615 SATA_TXN0_3C

Cable Cable

2 C5616 SATA_RXN0_3C
2 C5617 SATA_RXP0_3C

Cable

Cable

22
1

21
NP1

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
24

NP2
23

FOX-CON20-1-GP-U

Non-cable

20.F1546.020

SKT-SATA22P-40-GP

22.10300.351
2nd = 22.10300.031
3rd = 22.10300.011

SATA Zero Power ODD

ODD Connector
ODD1

SCD01U16V2KX-L1-GP 1
SCD01U16V2KX-L1-GP 1

21
21

SATA_RXN4
SATA_RXP4

SCD01U16V2KX-L1-GP 1
SCD01U16V2KX-L1-GP 1

2 C5611
2 C5612
2 C5607
2 C5608

SATA_TXN4_C
SATA_TXP4_C
SATA_RX4-_C
SATA_RX4+_C

+5V
+5V

S3
S2

AA+

S5
S6

BB+

MD
DP

P4
P1

GND
GND
GND
GND
GND
GND
GND

S1
S4
S7
P5
P6
14
15

SATA_ODD_DA#_C

0R2J-L-GP

2 R5602

1
2
3
4

SATA_ODD_DA# 18
SATA_ODD_PRSNT# 22
22 SATA_ODD_PW RGT

GND
OUT#8
IN#2
OUT#7
IN#3
OUT#6
EN/EN#
OCB

ODD_PW R_5V

8
7
6
5

SY6288CCAC-GP
R5604
10KR2J-L-GP

TC5602
SC10U25V5KX-GP

SATA_TXN4
SATA_TXP4

P2
P3

ZPO

U5601

ZPO

74.06288.079
2nd = 74.02311.A79

DY
2

21
21

ODD_PW R_5V

ODD

R5603 2
0R5J-5-GP

TC5601
SC10U25V5KX-GP

5V_S0

DY

5V_S0

NP1
NP2

NP1
NP2

High Active 2A

SKT-SATA7P-6P-119-GP

22.10300.H31
2nd = 22.10300.H61

3D3V_S0

R5605
10KR2J-L-GP

SATA_ODD_DA#_C

ODD_PWRGT#

RN5601
SRN10KJ-L-GP
1
4 SATA_ODD_PW RGT
2
ZPO 3 SATA_ODD_DA#

Q5601
2N7002KDW -GP

ZPO
1

3D3V_S0

84.2N702.A3F
2nd = 84.DM601.03F

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
SATA_ODD_PW RGT

SATA_ODD_DA#
Title

HDD/ODD
Size
A3

Document Number

Date:

Tuesday, July 10, 2012

Rev

-1

Petra Uma
Sheet

56

of

103

SSID = AUDIO
D

LOUT1
5
4
2

AUD_HP1_JD# 29
AUD_HP1_JACK_R1

1 R5802 2
0R2J-L-GP
1 R5803 2
0R2J-L-GP

AUD_HP1_JACK_L1
1

EC5802
MLVG0402101NV05-GP

AUD_AGND

EC5801
MLVG0402101NV05-GP

COMBO_MIC

DY
2

DY

22.10270.661
2nd = 22.10270.941

AUD_HP1_JACK_L2 29

COMBO_MIC 29

R5801
549R3F-GP

AUDIO-JK235-GP-U

AUD_HP1_JACK_R2 29

AUD_HP1_JACK_L2

COMBO_MIC_R1 2

1
6
3

AUD_HP1_JACK_R2

EC5803
MLVG0402101NV05-GP

DY

SPK1

AUD_AGND

5
1

AUD_SPK_L-_R 29

2
3
4

AUD_SPK_L+_R 29
AUD_SPK_R-_R 29
AUD_SPK_R+_R 29
1

DY
2

1
2

1
2

DY

SC680P50V2KX-2GP
EC5807

DY

SC680P50V2KX-2GP
EC5806

DY

SC680P50V2KX-2GP
EC5805

SC680P50V2KX-2GP
EC5804

ACES-CON4-29-GP

20.F1639.004
2nd = 20.F1804.004
3rd = 20.F1352.004

SA:change to be DGND

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

Audio Jack
Size
A4

Document Number

Date:
5

Rev

Petra Uma
Tuesday, July 10, 2012

Sheet

-1
58

of
1

103

SSID = LAN
FT1

27
25

31

MDI3-

31

MDI1+

31

MDI1-

31

MDI2+

XRF_TDC1

SCD1U10V2KX-L1-GP
C5901

31

31

31

23

RJ45_7

24

MCT1

22

RJ45_8

20

RJ45_3

21

MCT2

19

RJ45_6

17

RJ45_4

18

MCT3

1:1

1:1

MDI2-

16

RJ45_5

MDI0+

11

14

RJ45_1

SKT-IO24-GP-U

10

15

MCT4

22.10342.011
2nd = 22.10342.021

13

RJ45_2

12

50
CRT_DDCCLK_CON 50
CRT_VSYNC_CON 50
CRT_DDCDATA_CON 50
CRT_HSYNC_CON 50

CONN_PWR
CONN_PWR2

5V_CRT_S0

10M/100M/1G_LED# 31
LAN_ACT_LED# 31

RJ45_4
RJ45_7
RJ45_5
RJ45_8
RJ45_1
RJ45_3
RJ45_2
RJ45_6

2
1

3D3V_S5

3
4

CONN_PWR
CONN_PWR2

RN5901
SRN470J-4-GP-U
EC5901
SC100P50V2JN-L-GP

26
28

1:1

MDI0-

CRT_B

MDI3+

31

50
50

XF5901
D

CRT_R
CRT_G

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

EC5902
SC100P50V2JN-L-GP

DY

DY

1:1
XFORM-24P-63-GP

XRF_TDC1

68.89240.30D
2nd = 68.IH601.301

C5916
SC1KP50V2JN-2GP

DY
U5904

5V_S5

U5901
5V_S5

TVLST2304AD0-GP

TVLST2304AD0-GP

1
31

2
2

31

MDI0+

31

MDI0-

MDI1+

31

MDI1U5902
U5903

5V_S5

5V_S5

31

MDI3+

MDI3-

MDI2+

MCT2

MCT1

MCT4

MDI2-

MDI2-

MCT3

MDI1+

MDI2+

MCT4

MCT3

MDI0+

31

31

TVLST2304AD0-GP

MDI3-

MCT2

MDI0-

TVLST2304AD0-GP

MDI3+

MCT1

MDI1-

31

1
R5904
75R3J-L-GP

R5902
75R3J-L-GP

R5901
75R3J-L-GP

R5903
75R3J-L-GP

GDT4

DY

GDT3

DY

1
2

<Core Design>

Wistron Corporation

MCT_R

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

-1_20120301
C5905
SC1KP2KV6KX-GP

Title

1
2

1
2

GDT2

B88069X9231T203-GP

DY

B88069X9231T203-GP

SC1KP50V2KX-1GP
C5906

SC1KP50V2KX-1GP
C5907

EC5907

SC6D8P50V2CN-GP

EC5908

SC6D8P50V2CN-GP

EC5906

SC6D8P50V2CN-GP

EC5905

SC6D8P50V2CN-GP

EC5904

SC6D8P50V2CN-GP

EC5903

SC6D8P50V2CN-GP

SC6D8P50V2CN-GP

SC6D8P50V2CN-GP

EC5909

GDT1

B88069X9231T203-GP

B88069X9231T203-GP

EC5910

DY

LAN_ACT_LED#
10M/100M/1G_LED#

LAN CONNECTOR
Size
Custom
Date:

Document Number

Rev

-1

Petra Uma

Tuesday, July 10, 2012

Sheet
1

59

of

103

SSID = Flash.ROM

1
2
3
4

RN6001
SRN4K7J-10-GP

1
2

DY

8
7
6
5

SCD1U10V2KX-L1-GP
C6002

SC10U6D3V5KX-1GP
C6001

3D3V_S5

3D3V_S5

SPI_HOLD_0#
3D3V_S5
U6001

1
2
3
4

CS#
SO/SIO1
WP#
GND

VCC
HOLD#
SCLK
SI/SIO0

8
7
6
5

SPI_CLK_R 21,27
SPI_SI_R 21,27

DY
2

72.25640.D01
2nd = 72.25Q64.B01

Q6001
CH715FPT-GP

SSID = RTC

RTC1

RTC_PW R

1 R6002 2
1KR2J-L2-GP

Width=20mils

C6003
SC1U6D3V2KX-L-1-GP

DY

+RTC_VCC

83.R0304.B81
2nd = 83.00040.E81

RTC_AUX_S5

DY

SC4D7P50V2CN-1GP
EC6001

MX25L6406EM2I-12G-GP

DY

SC4D7P50V2CN-1GP
EC6003

EC6002
SC4D7P50V2CN-1GP

SPI_SO
SPI_W P#

2
33R2J-L1-GP

1
R6001

21,27 SPI_CS0#_R
21,27 SPI_SO_R

3D3V_AUX_S5

1
2
NP1
NP2

PWR
GND
NP1
NP2

BAT-330DG02PSS0301CE-GP-U1

62.70001.051
2nd = 62.70001.061

<Core Design>
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Flash/RTC
Size
Custom
Date:
5

Document Number

Rev

-1

Petra Uma
Tuesday, July 10, 2012

Sheet
1

60

of

103

SSID = USB

USB20_V2
D

1
2

DY

SC10U10V5ZY-1GP
C6103

SCD1U16V2KX-L-GP
C6102

Close to AUSB2

USB20_V2
AUSB2

8
6
1

L6101
FILTER-4P-6-GP
18

USB_PN0

USBPN0_C

18

USB_PP0

USBPP0_C

2
3
4
5
7
SKT-USB8-3-GP-U

22.10321.B81
2nd = 22.10321.C41
3rd = 22.10321.E01

Low Active 2A
USB20_V2

SY6288DCAC-GP

74.06288.A79
2nd = 74.02301.079

DY
2

8
7
6
5

OUT#8
OUT#7
OUT#6
OCB

SC10U10V5ZY-1GP
C6106

C6105
SC1U10V3KX-L1-GP

GND
IN#2
IN#3
EN/EN#

SCD1U16V2KX-L-GP
C6104

1
2
3
4

U6102

5V_S5

27,62 USB_PW R_EN#

B

USB20_V2
AUSB3

USBPN9_C

18

USB_PP9

USBPP9_C

FILTER-4P-6-GP

2
3
4
5
7

USB_PN9

TC6102
SE220U6D3VM-30-GP

77.52271.09L
2

L6102
18

USB20_V2

8
6
1

SKT-USB8-3-GP-U

22.10321.B81
2nd = 22.10321.C41
3rd = 22.10321.E01

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

USB Power SW
5

Size
A3

Document Number

Date:

Tuesday, July 10, 2012

Rev

-1

Petra Uma
Sheet
1

61

of

103

Low Active 2A
USB30_VCCA

SY6288DCAC-GP

74.06288.A79
2nd = 74.02301.079

8
7
6
5

OUT#8
OUT#7
OUT#6
OCB

SC10U10V5ZY-1GP
C6203

C6202
SC1U10V3KX-L1-GP

GND
IN#2
IN#3
EN/EN#

SCD1U16V2KX-L-GP
C6201

1
2
3
4

U6201

5V_S5

DY

27,61 USB_PW R_EN#

USB_PP1

USB_PN1_L
USB_PP1_L

L6201
FILTER-4P-6-GP

2
3

DD+

GND_DRAIN

10
11
4

CHASSIS#10
CHASSIS#11
GND

VBUS

STDA_SSRXSTDA_SSRX+

5
6

STDA_SSTXSTDA_SSTX+

8
9

CHASSIS#12
CHASSIS#13

12
13

USB30_TN0_C
USB30_TP0_C

2
2

1 SCD1U16V2KX-L-GP
1 SCD1U16V2KX-L-GP

C6206
C6207

USB30_RN2
USB30_RP2

18
18

USB30_TN2
USB30_TP2

18
18

USB30_VCCA

USB_PN1

18

18

USB30_VCCA

TC6201
SE220U6D3VM-30-GP

77.52271.09L

AUSB1
SKT-USB13-23-GP

22.10339.521
2nd = 22.10339.141
3rd = 22.10321.Z41

USB 3.0 Connector

Pin definition
B

POWER

USB 2.0 D-

USB 2.0 D+

GND

StdA_SSRX-

StdA_SSRX+

GND

StdA_SSTX-

StdA_SSTX+

SuperSpeed RX

SuperSpeed TX

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

USB 3.0 Port

5

Size
A3

Document Number

Date:

Tuesday, July 10, 2012

Rev

-1

Petra Uma
Sheet
1

62

of

103

SSID = Wireless

Mini Card Connector(802.11a/b/g/n)

3D3V_IOAC
3D3V_IOAC
1D5V_S0

DY

W LAN_RST#

PCIE_CLK_WLAN#

DY
2

PCIE_CLK_WLAN

DY

E51_TXD 27
W IFI_RF_EN 27

3D3V_IOAC

E51_RXD 27

2 0R0402-PAD

DY
2

2 0R0402-PAD

DY
2

R6502

DY
2

R6501

E51_TXD_R

EC6510
SC10P50V2JN-4GP

USB_PP11

SC8P250V2CC-GP
EC6512

DY

USB_PN11

SC8P250V2CC-GP
EC6513

E51_RXD_R

+5V_MINI_DEBUG

W LAN_RST#

SC68P50V2JN-1GP
EC6503

20

SC68P50V2JN-1GP
EC6507

20

PCIE_CLK_W LAN

-1_20120301

20

SC68P50V2JN-1GP
EC6509

PCIE_RXN4 20
PCIE_RXP4 20

W LAN_RST#
W LAN_RST#

1 R6504 2
0R2J-L-GP
1 R6505 2

DY

DEBUG_DET#

PCIE_TXN4 20

0R2J-L-GP

PCIE_TXP4 20

-1_20120223

PLT_RST# 5,18,27,31,36,71,97
WLAN_PERST# 27

USB_PN11 18
USB_PP11 18

2nd = 84.03413.A31
84.02130.031
AP_DET#

Q6501
DMP2130L-7-GP

5V_S5

AP_DET# 27

+5V_MINI_DEBUG

+5V_MINI_DEBUG

R6503
100KR2J-4-GP

PCIE_CLK_W LAN#

C6505
SC10U6D3V5KX-1GP

DY

SC56P50V2JN-2GP
EC6511

CLK_PCIE_W LAN_REQ#

C6508
MLVG0402220NV05BP-GP-U

W LAN_W AKE# 27

IOAC
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
NP2
54

1
2
0R2J-L-GP

SCD1U16V2KX-L-GP
C6504

R6511
W LAN_W AKE#_R

1
2

SC10U6D3V5KX-1GP
C6503

53
NP1

WIFI_RF_EN
SCD1U16V2KX-L-GP
C6502

1D5V_S0

W LAN1

DEBUG_DET#
SKT-MINI52P-110-GP

62.10043.G01
2nd = 62.10043.C31

Q6502

G
27 BLUETOOTH_EN

D
S

+5V_MINI_DEBUG

2N7002K-2-GP

84.2N702.J31
2nd = 84.2N702.031

3D3V_S0
3D3V_SRC

3D3V_IOAC
R6512

non-IOAC
2

C6501
SC1U10V2KX-1GP

0R2J-L-GP

IOAC

U6501

1
2
3
4

27 W LAN_PW R_EN#

GND
IN#2
IN#3
EN/EN#

IOAC
<Core Design>

OUT#8
OUT#7
OUT#6
OCB

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

SY6288DCAC-GP

74.06288.A79
2nd = 74.02301.079

8
7
6
5

MINICARD(WLAN)/ITP CONN
3

Size
A3

Document Number

Date:

Tuesday, July 10, 2012

Rev

-1

Petra Uma
Sheet
1

65

of

103

Power button LED

Q6801
27

PW RLED

R1

FRONT_PW RLED#_Q

FRONT_PW RLED#_Q 82

R2
LTC043ZUB-FS8-GP

84.00043.011
2nd = 84.00143.E1K
LED-BO-5-GP-U1

Power STDBY_LED

FRONT_PW RLED#_Q

1 R6801

2 330R2F-GP FRONT_PW RLED#_R

STDBY_LED#_Q

1 R6802

2 330R2F-GP STDBY_LED#_R

27

STDBY_LED

5V_S5

PLED1

Q6802
R1

STDBY_LED#_Q

83.00326.A70

2
R2
LTC043ZUB-FS8-GP

84.00043.011
2nd = 84.00143.E1K

LED-BO-5-GP-U1
DC_BATFULL#_Q
CHARGE_LED#_Q

1 R6803

2 330R2F-GP

DC_BATFULL#_R

1 R6804

2 330R2F-GP

CHARGE_LED#_R

5V_AUX_S5

CHLED1

Battery LED2(DC_BATFULL)

83.00326.A70

Q6805

27 DC_BATFULL

R1

DC_BATFULL#_Q

2
R2
LTC043ZUB-FS8-GP

84.00043.011
2nd = 84.00143.E1K

Battery LED1(CHARGE)

KBC_PW RBTN#

Q6808

CHARGE_LED

R1

CHARGE_LED#_Q

2
R2
LTC043ZUB-FS8-GP

27

KBC_PW RBTN# 27,29,82

EC6801
MLVG0402101NV05-GP

84.00043.011
2nd = 84.00143.E1K

<Core Design>
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

LED Bard/Power Button

Size
Custom
Date:
5

Document Number

Rev

-1

Petra Uma
Tuesday, July 10, 2012

Sheet
1

68

of

103

SSID = KBC
Internal KeyBoard
Connector

TOUCH PAD
3D3V_S0
3D3V_S0

RN6901
SRN4K7J-8-GP

2nd = 20.K0752.026
20.K0733.026

28

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KCOL17

KCOL0

1
2

27 TPCLK
27 TPDATA

KROW0
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7

27

4
3

KROW [0..7]

27

KCOL[0..17]

27

RN6902
SRN33J-5-GP-U
4
3

SC56P50V2JN-2GP
EC6902

KB1
ETY-CON26-7-GP

1
2

TPAD1
ACES-CON8-37-GP
10

1
TP_CLK
TP_DATA

2
3
4
5
6
7
8

14,15,20 PCH_SMBDATA
14,15,20 PCH_SMBCLK
18 TP_IN#

14

0.5 pitch

20.K0637.008

TPAD2
ACES-CON8-40-GP

9
1

15

2
3
4
5
6
7
8
10

1.0 pitch

20.K0667.008
2nd = 20.K0665.008

-1_20120302A
20.K0722.004
ACES-CON4-50-GP

5V_S0

6
B

KB_BL_DET_R

KB_LED_PW M_D

1 R6901 2
100KR2J-4-GP

KB_BL_DET 27

4
3
2

C6901
SCD1U25V2KX-GP

5
R6902
200KR2F-L-GP

KB2

Q6901
AO3418-GP

R6903
27

KB_BL_PW M

KB_BL_PW M_R

84.03418.031

DY

C6902
SCD1U10V2KX-L1-GP

0R2J-L-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Key Board/Touch Pad

5

Size
A3

Document Number

Date:

Tuesday, July 10, 2012

Rev

-1

Petra Uma
Sheet
1

69

of

103

3D3V_AUX_KBC
C

C7002
SCD1U10V2KX-L1-GP

APX9132HAI-TRG-GP
LID1
1

VDD
GND

LID_CLOSE#

LID_CLOSE#_1

DY

VOUT

1st = 74.05712.0BB
2nd = 74.01803.07B

27

1 R7002 2
100R2J-L-GP

C7001
SCD047U16V2KX-1-GP

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

Hall Sensor
Size
A4

Document Number

Date:
5

Rev

Petra Uma
Tuesday, July 10, 2012

Sheet

-1
70

of
1

103

3D3V_S0
DB1
21,27 LPC_AD0
21,27 LPC_AD1
21,27 LPC_AD2
21,27 LPC_AD3
21,27 LPC_FRAME#
5,18,27,31,36,65,97 PLT_RST#

18

CLK_PCI_LPC

1
2
3
4
5
6
7
8
9
10
11
12

DY

MLX-CON10-7-GP

20.D0183.110

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

Dubug connector
Size
A4

Document Number

Date:
5

Rev

Petra Uma
Tuesday, July 10, 2012

Sheet

-1
71

of
1

103

SSID = SDIO
D

SD/MMC Card Reader

CARD_3V3

CARD1

Layout 40 mil

VDD
CLK
CMD

31
31

SD_CLK
SD_CMD

5
2

31
31

SD_WP
SD_CD#

11
10

WRITE_PROTECT
CARD_DETECT

12
13

12
13

DAT0
DAT1
DAT2

7
8
9

SD_DATA0 31
SD_DATA1 31
SD_DATA2 31

CD/DAT3

SD_DATA3 31

1
2

C7401
SC4D7U6D3V3KX-L-GP

NP1
NP2
VSS1
VSS2

NP1
NP2
3
6

SDCARD-13P-2-GP
C

62.10051.C41
2nd = 62.10051.D71

SD_CLK
EC7401
SC33P50V2JN-3GP

DY

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

CARD Reader CONN

Size
A4

Document Number

Date:
5

Rev

Petra Uma
Tuesday, July 10, 2012

Sheet

-1
74

of
1

103

PWRCN1
7
1
2
3
4
5
6

5V_S5
KBC_PWRBTN# 27,29,68
FRONT_PWRLED#_Q 68
C

8
ACES-CON6-52-GP

20.K0721.006
2nd = 20.K0382.006

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

IO Board Connector
Size
A4

Document Number

Date:
5

Rev

Petra Uma
Tuesday, July 10, 2012

Sheet

-1
82

of
1

103

34.4TU18.001
2nd = 34.4TU18.101

HS1

34.4TU18.001
2nd = 34.4TU18.101

HS2

34.4TU18.001
2nd = 34.4TU18.101

HS3
H11
HOLE335R115-GP

CPU

H10
HOLE335R115-GP

H5

STF237R128H41-GP

H4

STF237R128H41-GP

STF237R128H41-GP

H3

H6
HOLE335R115-GP

HOLE355X355R111-S1-GP

H2

Check test point

HOLE355X355R111-S1-GP

HOLE355X355R111-S1-GP

HOLE355X355R111-S1-GP

HOLE355X355R111-S1-GP

H1

3D3V_S0

AFTP1

3D3V_AUX_S5

AFTP7

3D3V_S5

AFTP8

5V_S5

AFTP9

AFTP10

AFTP11

AFTP12

AFTP13

19,27 PM_PW RBTN#

5,22,36 H_CPUPW RGD
27,36 S5_ENABLE

EC change

H12
HOLE335R115-GP

5,18,27,31,36,65,71

PLT_RST#

Test Point
Dimm Door

1
2

DY

1
2

1
2

1
2

1
2

1
2

1
2

1
2

DY

SCD1U10V2KX-L1-GP
EC9708

DY

3D3V_S0

SCD1U50V3KX-GP
EC9704

SCD1U50V3KX-GP
EC9721

DY

SCD1U50V3KX-GP
EC9722

SCD1U50V3KX-GP
EC9723

PW R_VCCCORE1_DCBATOUT

SCD1U50V3KX-GP
EC9707

DY

SCD1U50V3KX-GP
EC9702

DCBATOUT_2

SCD1U50V3KX-GP
EC9701

DY

SCD1U50V3KX-GP
EC9714

DY

SCD1U50V3KX-GP
EC9715

DCBATOUT

1
2

AD_JK
SCD1U50V3KX-GP
EC9716

DY

SCD1U10V2KX-L1-GP
EC9706

DY

SCD1U10V2KX-L1-GP
EC9705

1D05V_VTT

DY
1D5V_S3

5V_S0

5V_S5

2
EC9728
MLVG0402101NV05-GP

1
2

1
2

1
2

1
2

1
2

1
2

1
2

DY

SCD1U10V2KX-L1-GP
EC9725

DY

SCD1U10V2KX-L1-GP
EC9720

SCD1U10V2KX-L1-GP
EC9719

DY

SCD1U10V2KX-L1-GP
EC9718

DY

SCD1U10V2KX-L1-GP
EC9717

DY

SCD1U10V2KX-L1-GP
EC9713

DY

SCD1U10V2KX-L1-GP
EC9712

DY

SCD1U10V2KX-L1-GP
EC9711

DY
EC9729
MLVG0402101NV05-GP

AUD_AGND

-1_20120301

1
2

1
2

1
2

DY

LCDVDD

<Core Design>

SCD1U10V2KX-L1-GP
EC9726

DY

SCD1U50V3KX-GP
EC9732

DY

SCD1U50V3KX-GP
EC9731

SCD1U50V3KX-GP
EC9730

DCBATOUT

BT+

-1_20120301

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

UNUSED PARTS/EMI Capacitors

3

Size
A3

Document Number

Date:

Tuesday, July 10, 2012

Rev

-1

Petra Uma
Sheet
1

97

of

103

Power Sequence
PU4601

PM_SLP_S4#

1D5V_S3

PU4501

RUNPWROK

1D05V_S0

U4801

1.05VTT_PWRGD

0D85V_S0

0D85V_S0

1D5V_S3

1D05V_VTT

0D75V_EN

ALL_POWER_OK

0D75V_S0

PLT_RST#

U?

U?

U?
U?

ALL_POWER_OK

EC

S0_PWR_GOOD

PCH

PM_DRAM_PWRGD

AND GATE

VDDPWRGOOD

CPU

H_CPU_SVIDCLK

ALL_POWER_OK
H_CPUPWRGD

U?

VCC_GFXCORE
CPU_CORE

SYS_PWROK
VCC_CORE
U?

H_CPU_SVIDCLK
IMVP_PWRGD

AND GATE

S0_PWR_GOOD

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Change History
Size
A3
Date:
5

Document Number

Rev

-1

Petra Uma

W ednesday, February 22, 2012

Sheet
1

98

of

103

Intel-Power Up Sequence
(AC mode)

(DC mode)

red word: KBC GPIO

+RTC_VCC

+RTC_VCC

T1

T1

PCH_RTCRST#

PCH_RTCRST#

+PWR_SRC

+PWR_SRC

T2

+3.3V_RTC_LDO
D

red word: KBC GPIO

T2

+3.3V_RTC_LDO
T3

S5_ENABLE

KBC GPIO36 control

Press Power button

KBC_PWRBTN_EC#

T4

+5V_ALW

T5

+3.3V_ALW

T6

T4

S5_ENABLE

+5VALW_PCH_VCC5REFSUS

KBC GPIO36 control

T5

+5V_ALW
+15V_ALW

T7

T8

T9
T10
>10ms

PCH_RSMRST#(EC Delay 40ms)

T11

+5V_ALW & +3.3V_ALW need meet 0.7V difference

T7

+5V_ALW & +3.3V_ALW need meet 0.7V difference

+5VALW_PCH_VCC5REFSUS

PCH to KBC GPI94

SUS_PWR_DN_ACK

T6

+3.3V_ALW

TPS51125 to KBC GPIO46

3V_5V_POK

KBC_PWRBTN_EC# GPIO3
EC_ENABLE# (GPIO51) keep low

T3

+KBC_PWR

KBC GPIO43 to PCH

+15V_ALW

PCH to KBC GPIO00

3V_5V_POK

PCH_SUSCLK_KBC

T8

T9

TPS51125 to KBC GPIO46

T10

KBC GPO84 to PCH

PM_PWRBTN#

AC_PRESENT_EC

PCH to KBC GPI94

T12 <200ms

SUS_PWR_DN_ACK

T11

KBC GPIO43 to PCH

PCH_RSMRST#

Press Power button

T12 >10ms
T13

PCH_SUSCLK_KBC

AC KBC_PWRBTN_EC#

PCH to KBC GPIO01

KBC_PWRBTN_EC# GPIO3
3V_5V_POK

T13

DC PCH_RSMRST#

KBC GPO84 to PCH

T14

AC PM_PWRBTN#
PM_SLP_S4#

AC PM_PWRBTN#
T14

T15
>30us

PM_SLP_S3#

T16

PM_LAN_ENABLE

PM_SLP_S4#

T15
>30us

PM_SLP_S3#
C

KBC GPO16 to LAN

T17

+3.3V_LAN
T16

PM_LAN_ENABLE

KBC GPO16 to LAN

T17

+3.3V_LAN
+1.5V_SUS

T18

+V_DDR_REF(0.9V)

T19

+5V_RUN

+5V_RUN & +3.3V_RUN need meet 0.7V difference

T21

T18

+V_DDR_REF(0.9V)

T19

+5V_RUN & +3.3V_RUN need meet 0.7V difference

+5V_RUN

T20

+3.3V_RUN

T21

T22

+5VS_PCH_VCC5REF

T20

+3.3V_RUN

+1.5V_SUS

T22

+5VS_PCH_VCC5REF

+1.5V_RUN

T23

+1.8V_RUN

T24

T25 >1ms

H_PWRGD

KBC GPIO71 to RT8208B

+1.5V_RUN

T23

+1.8V_RUN

T24

T25 >1ms

GFX_CORE_EN(Discrete only)

H_PWRGD

KBC GPIO71 to RT8208B

GFX_CORE_EN(Discrete only)------Delay 5ms

T27

T28

T28

KBC GPIO30 to APL5930

T30
T31

+1.8V_RUN_VGA(Discrete only)
T30

KBC GPIO66 to APL5930

T31

+3.3V_RUN_VGA(Discrete only)
T32

+3.3V_RUN_VGA_EN(Discrete only)-->DY reserved

T32

+3.3V_RUN_VGA_EN(Discrete only)-->DY reserved

1.8V_VGA_RUN_EN(Discrete only)------Delay 5ms

+1.8V_RUN_VGA(Discrete only)

KBC GPIO66 to APL5930

1.8V_VGA_RUN_EN(Discrete only)

T29

+1.0V_RUN_VGA(Discrete only)

KBC GPIO30 to APL5930

T29

+1.0V_RUN_VGA(Discrete only)

1.0V_RUN_VGA_EN(Discrete only)------Delay 4ms

+3.3V_RUN_VGA(Discrete only)

T27

1.0V_RUN_VGA_EN(Discrete only)

T26

+VGA_CORE(Discrete only)

T26

+VGA_CORE(Discrete only)

KBC GPI95
T33

-->Reserved for sequence

KBC GPI95
RUNPWROK

T33

-->Reserved for sequence

T34
T35

+1.05V_VTT

RUNPWROK

1.5CPU_1.05VTT_PWRGD(after delay 1ms GPI96-VDDPWRGOOD_EC output

T34
T35

+1.05V_VTT
B

1.5CPU_1.05VTT_PWRGD(after delay 1ms GPI96-VDDPWRGOOD_EC output

T37

+0.75V_DDR_VTT

TPS51218 to KBC GPI34

T36

for s3 reduction)

TPS51218 to KBC GPI34

T36

for s3 reduction)

T38

H_VTTPWRGD

T37

+0.75V_DDR_VTT

T38

H_VTTPWRGD

+1.05V_VTT

T39

CPU to TPS51611

GFX_VR_EN(UMA only)

+1.05V_VTT

T39

UMA GFX CORE Power

T40

+CPU_GFX_CORE(UMA only)

CPU to TPS51611

GFX_VR_EN(UMA only)

UMA GFX CORE Power

T40

+CPU_GFX_CORE(UMA only)

1.5CPU_1.05VTT_PWRGD

T41

( >99ms )

T41

T42

( >99ms )

CLKIN_BCLK(from CK505) stable

CPU CORE Power

43 >1ms

CLK_CPU_BCLK

CLKIN_BCLK(from CK505) stable

ISL62883 to CLOCKGEN

1.5CPU_1.05VTT_PWRGD

ISL62884 to KBC GPO14

T44 >1ms
1.5CPU_1.05VTT_PWRGD

T46

>5ms

3ms<
+1.5V_RUN_CPU

T46 >5ms

PM_PWROK
+VCC_CORE

3ms<

PM_PWROK
+1.5V_RUN_CPU

T47 <20ms

T49 >100ns

PM_DRAM_PWRGD

T47 <20ms

T49 >100ns

T48 >1ms

(for S3 Reduction)

T48 >1ms
H_VTTPWRGD

T50 >1ms

PM_PWROK
+VCC_CORE

T51 >1ms

T51 >1ms

T50 >1ms

0.05ms<

T52 <650ms

H_PWRGD

T53
0.05ms<

T52 <650ms

>1ms

PLT_RST#

H_PWRGD

T53
>1ms

PLT_RST#

Delay 10ms

KBC GPIO47 to PCH

Delay 10ms

(for S3 Reduction)
H_VTTPWRGD

T45

T45
KBC GPIO47 to PCH

PM_PWROK

ISL62884 to KBC GPO14

T44 >1ms

IMVP_PWRGD

CK_PWRGD
IMVP_PWRGD

ISL62883 to CLOCKGEN

CK_PWRGD

43 >1ms

PM_DRAM_PWRGD

CPU CORE Power

CLK_CPU_BCLK

T42
<3ms

+VCC_CORE

<3ms

+VCC_CORE

KBC GPO53 to ISL62883

IMVP_VR_ON

KBC GPO53 to ISL62883

IMVP_VR_ON

1.5CPU_1.05VTT_PWRGD

T54

KBC LRESET#
T54

KBC GPIO45

<Core Design>

PLTRST_DELAY#

KBC LRESET#

T55

Wistron Corporation

H_CPURST#

KBC GPIO45

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

PLTRST_DELAY#

T55

Title

Power Sequence

H_CPURST#
Size
A1
Date:
5

Document Number

Rev

-1

Petra Uma

Wednesday, February 22, 2012

1

Sheet

99

of

103

DCBATOUT

Adapter

RT8207LZQW
ISL95836HRTZ
rev 1.7

TPS51218DSCR

G978
DDR_VREF_S3

P1403EV8

0D75V_S0

1D5V_S3

Charger
VCC_CORE

BQ24747
+AD

Battery

VCC_GFXCORE

1D05V_VTT

0D85V_S0

AO4468

For UMA

1D5V_S0

RT8223MZQW

1D5V_DDR_S0
C

3D3V_AUX_S5

DMP2305U

+KBC_PWR

5V_AUX_S5

3D3V_SRC

5V_S5

SY6288DCAC

SY6288DCAC

USB30_VCCA

USB20_V2

USB3.0 Power

AO4468

AO4468

5V_S0

SY6288DCAC

3D3V_S0

3D3V_IOAC

USB Power

SY6288CAAC

3D3V_S5

WLAN Power

AME8818BEEV330Z
RT9025

SY6288C6AAC

3D3V_CARD_S0

3D3V_DAC_S0

1D8V_S0

LCDVDD

Power Shape
Regulator

LDO

Switch

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Power Block Diagram

Size
A3
Date:
5

Document Number

Rev

-1

Petra Uma

W ednesday, February 22, 2012

Sheet
1

100

of

103

3D3V_S5

3D3V_S0

KBC SMBus Block Diagram

PCH SMBus Block Diagram

5V_S0

3D3V_S0
SRN2K2J-1-GP

SRN2K2J-1-GP

SMBCLK

SMB_CLK

SMBDATA

SMB_DATA

DIMM 1

PCH_SMBCLK
PCH_SMBDATA

SRN10KJ-5-GP
1

TouchPad Conn.

SCL
SDA

3D3V_S5

SMBus Address:A0

PSDAT1

TPDATA

PSCLK1

TPCLK

TPDATA

TPDATA

TPCLK

TPCLK

2N7002SPT

3D3V_AUX_KBC

SRN2K2J-8-GP

SML1CLK

SML1_CLK

SML1DATA

SML1_DATA

To KBC & eDP

SML0CLK

SML0_CLK

SML0DATA

SML0_DATA

SRN4K7J-8-GP

DIMM 2
PCH_SMBCLK
PCH_SMBDATA

3D3V_S5

SCL

Battery Conn.

SRN100J-3-GP

SDA

GPIO17/SCL1

BAT_SCL

BATA_SCL_1

CLK_SMB

GPIO22/SDA1

BAT_SDA

BATA_SDA_1

DAT_SMB

SMBus address:16

SMBus Address:A4
SRN2K2J-1-GP

PCH

3D3V_S0

5V_S0

PCH_SMBCLK
PCH_SMBDATA

SRN2K2J-1-GP

Minicard
WLAN

BQ24747

KBC
NPCE885P

SMB_CLK
SMB_DATA

SCL
SDA

SRN1K5J-GP

UMA

SDVO_CTRLCLK
SDVO_CTRLDATA

SCL

Level
Shift

PCH_HDMI_CLK
PCH_HDMI_DATA

SMBus address:12

SDA
DDC_CLK_HDMI

LCDVDD_eDP
2

PCH

HDMI CONN

DDC_DATA_HDMI

LCDVDD_eDP
SRN2K2J-1-GP

UMA

3D3V_S0

eDP

LCD_SMBCLK

SCL

LCD_SMBDATA

SDA

SMBus address:XX

SRN2K2J-1-GP
SRN0J-6-GP
L_DDC_CLK
L_DDC_DATA

CRT_DDC_CLK
CRT_DDC_DATA

LVDS_DDC_CLK_R

LVDS_DDC_CLK

CLK

LVDS_DDC_DATA_R

LVDS_DDC_DATA

DATA

GPIO73/SCL2

SML1_CLK

GPIO74/SDA2

SML1_DATA

2N7002DW-1-GP

LCD CONN

CRT_DDC_CLK
CRT_DDC_DATA

3D3V_S0

5V_S0

DIS

3D3V_S0
SRN2K2J-1-GP

SRN10KJ-6-GP

SRN0J-6-GP
CRT_DDCCLK_CON
CRT_DDCDATA_CON

FT1 Conn

2N7002DW-1-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

SMBUS Block Diagram

Size
A2
Date:
A

Document Number

Rev

-1

Petra Uma

Wednesday, February 22, 2012

E

Sheet

101

of

103

Thermal Block Diagram

Audio Block Diagram

SPKR_PORT_D_LPAGE28

DXP

P2800_DXP

SPEAKER

SPKR_PORT_D_R+
MMBT3904-3-GP
SC2200P50V2KX-2GP

DXN

Thermal
NCT7718W

P2800_DXN

Codec
ALC271

Place near CPU

PWM CORE

CMBO
LOUT

AUD_HP1_JACK_R1

MMBT3904-3-GP

PCH
SMBUS

AUD_HP1_JACK_L1

SML1_CLK
SML1_DATA

T8

COMBO_MIC

PURE_HW_SHUTDOWN#
THERM_SYS_SHDN#
OTZ

2N7002

AUD_HP1_JD#

PGOD
G

Put under CPU(T8 HW shutdown)

EN

IMVP_PWRGD

3V/5V

VR
INT_MIC_L_R

AMIC

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Thermal/Audio Block Diagram

Size
Custom
Date:
A

Document Number

Rev

Petra Uma
Wednesday, February 22, 2012

Sheet

-1
102

of

103