Roll

Number:

INSTITUTE OF AERONAUTICAL ENGINEERING

DUNDIGAL 500 043, HYDERABAD

Time: 2 hours
Date:

I M.Tech IISemester(R13) II Midterm Examinations, JAN 2016

VLSI TECHNOOGY AND DESIGN (VLSI Design/ES)
Max. Marks: 25
Session: AN
Answer All Questions from Part - A
Answer any three Questions from Part - B
All parts of the question must be answered in one place only
PART A
(5 X 2= 10 marks)

Q 1.

Differentiate latch and flip-flop.

Q 2.
Q 3.

Draw a one bit SRAM cell.

How many tests are required to fully test for S-A-0 faults for a network with 8 primary
inputs?
Define floor planning in chip design.
What is meant by slicing floor plan?

Q 4.
Q5.

PART B
(3 X 5 = 15 marks)
Q6. Design a shift register using two phase clock generation technique.
Q7. Discuss the floor planning methods with neat diagrams.
Q8. Explain in detail about built in self test technique.
Q9. Design a 44 register array using RAM.
Q10. Discuss the concept of global interconnect with neat diagrams.