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4-bit Brent Kung Parallel Prefix Adder Simulation Study Using Silvaco EDA Tools
Anas Zainal Abidin, Syed Abdul Mutalib Al Junid, Khairul Khaizi Mohd Sharif,
Zulkifli Othman, Muhammad Adib Haron
Faculty of Electrical Engineering
Universiti Teknologi Mara
Shah Alam, 40450, Selangor, Malaysia
e-mail: samaljunid@salam.uitm.edu.my
Abstract In IC design environment, the chip performance is influence by design environment, schematic and sizing parameter of
the transistor. Therefore, this study is an attempt to investigate the performance of 4-bit Brent Kung Parallel Prefix Adder using
Silvaco EDA Tools and targeted to 0.18um Silterra Technology. The objective of this project is to review the performance of the
adder by forming different of transistors gate sizing and schematics. Furthermore, the study been carried out by implementing
Brent Kung Adder in Basic Logic Gate and Compound Gate, then simulate the design in various sizes of transistors in order to see
the effects on propagation delay, power consumption and the number of transistors used. At the end of this paper, evidently the
improvement of transistors size contributes reducing the propagation delay and proportionally advances the power consumption.
Besides, the Compound Gate takes about 35.58% power consumption decreased, reduced 9.16% of propagation delay and less 96
transistors used rather than Basic Logic Gate. Nevertheless, larger size of buffers required to stable the output consistency in
Compound Gate schematic.
Keywords - Brent Kung Adder, Parallel Prefix Adder
I.
INTRODUCTION
II.
PRELIMINARY BACKGROUND
A. Pre-processing stage
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ANAS ZAINAL ABIDIN et al: 4-BIT BRENT KUNG PARALLEL PREFIX ADDER SIMULATION STUDY USING . .
Block diagram illustrated above represent the n bit
Parallel Prefix Adder operation that begin with Preprocessing stage for generating and as in equation (1)
and (2).
III.
DESIGN METHODOLOGY
Fig.
Fig. 3: Complex logic cells inside the Prefix Carry Tree [5]
C. Post-processing stage
Complement the overall adder operation, carry bits that
produced from the second stage shall pass through the last
part known as Post-Processing stage. The procedure to
obtain the final adder result is able by the following equation
(4).
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ANAS ZAINAL ABIDIN et al: 4-BIT BRENT KUNG PARALLEL PREFIX ADDER SIMULATION STUDY USING . .
Fig. 6: Schematic and symbol for OR gate, AND gate and XOR gate
(a)
(b)
Fig. 9: (a) 4-bit Brent Kung Parallel Prefix Adder Tree schematic design,
(b) Block diagram of the tree adder stage
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ANAS ZAINAL ABIDIN et al: 4-BIT BRENT KUNG PARALLEL PREFIX ADDER SIMULATION STUDY USING . .
Fig. 11: Complete diagram of 4-bit Brent Kung Parallel Prefix Adder
B. Compound Gate
Other than that, this report also performed schematic
arrangement in Compound Gate, which, comprises of
combination of the series and parallel switch structures [7].
This technique has evidenced to decrease the number of
transistors used and directly subtract the total area
consumption in layout design, compared to Basic Logic Gate
circuit implementation.
This method can be conducted by converting the circuit
inside the block with satisfied as Compound Gate format.
The rest of 4-bit Brent Kung Parallel Prefix Adder schematic
connections has to be the same arrangement.
Fig. 12 show the XOR schematic in Compound Gate
system while the Pre-processing stage circuit for Compound
Gate resource established at Fig. 13.
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ANAS ZAINAL ABIDIN et al: 4-BIT BRENT KUNG PARALLEL PREFIX ADDER SIMULATION STUDY USING . .
Two types of trigger for output signals known as rise
(low to high) and fall (high to low) been considered, the
measured implementation done as Fig. 19 (a) rising
propagation delay and Fig. 19 (b) falling propagation delay
for one of the input and output signals simulation.
and
and
Scale Size
3
4
10
20
40
PMOS width, Wp
(um)
0.54
0.72
1.8
3.6
7.2
NMOS Width, Wn
(um)
0.27
0.36
0.9
1.8
3.6
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ANAS ZAINAL ABIDIN et al: 4-BIT BRENT KUNG PARALLEL PREFIX ADDER SIMULATION STUDY USING . .
Supply drain
current, Idd
(nA)
41.616
41.992
46.580
59.768
101.14
Power
consumption, P=IV
(nW)
74.909
75.586
83.844
107.582
182.052
Buffer
1
2
3
4
5
6
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ANAS ZAINAL ABIDIN et al: 4-BIT BRENT KUNG PARALLEL PREFIX ADDER SIMULATION STUDY USING . .
Fig. 21: reducing glitch using different sizes of transistor in the buffer
Supply drain
current, Idd
(nA)
130.970
131.210
133.470
139.990
160.100
Power
consumption, P=IV
(nW)
235.746
236.178
240.246
251.982
288.180
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ANAS ZAINAL ABIDIN et al: 4-BIT BRENT KUNG PARALLEL PREFIX ADDER SIMULATION STUDY USING . .
Table 6: Current, Power and the number of transistors comparison
LAYOUT DESIGN
Basic Logic
Gate (Buffer 1)
Compound
Gate (Buffer 1)
Compound
Gate (Buffer 6)
Supply drain
current, Idd
(nA)
101.14
Power
consumption,
P=IV (nW)
182.052
Number of
Transistors
64.913
116.843
198
160.100
288.180
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Fig. 24: Brent Kung Parallel Prefix Adder Layout in full custom
VI.
294
CONCLUSION
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ANAS ZAINAL ABIDIN et al: 4-BIT BRENT KUNG PARALLEL PREFIX ADDER SIMULATION STUDY USING . .
consumption and take more space for the layout area design.
Furthermore, the Compound Gate design are able to reduce
the complexity in the circuit with subtracting a lot number
of transistors used over than Basic Logic Gate schematic
done. While, directly decrease the power consumption of
the adder and spend less for the delay. Nevertheless,
Compound Gate performance has a concern in glitch noises
produced at the output signals which force an engineer to
sizing wider on the transistors at the buffer cell in order to
get over the thing.
ACKNOWLEDGEMENT
This project sponsor by Universiti Teknologi MARA under
Research Intensive Faculty Excellent Fund (RIF) reference
no 600-RMI/DANA 5/3/RIF (371/2012).
REFERENCES
[1] Cory Merkel, David Brenner, "8-bit Parallel Prefix Adders Using Brent
Kung Tree BIST", EECC730, November 2008
[2] Amos R. Omondi, Benjamin Premkumar, "Residue number systems:
theory and implementation", Imperial College Press, Technology &
Engineering, 2007
[3] Andrew Beaumont-Smith and Cheng-Chew Lim, "Parallel Prefix
Adder Design", Department of Electrical and Electronic Engineering,
The University of Adelaide,5005, Australia, 2001
[4] Kostas Vitoroulis, "Parallel Prefix Adders", Concordia University,
2006
[5] Vibhuti Dave, Erda Oruklu and Jafar Saniie, "Performance Evaluation
of Flagged Prefix Adders for Constant Addition", Department of
Electrical and Computer Engineering, Illilois Institute of technology,
Chicago, 2006
[6] Haikun Zhu, Chung-Kuan Cheng, Ronald Graham, "Constructing
Zero-deficiency Parallel Prefix Adder of Minimum Depth",
Department of Computer Science and Engineering, La Jolla, California
92093, 2005
[7] VLSI Design, Technician Publications, ISBN=8184314817,
9788184314816
[8] A. P. Godse and D. A. Godse, "Digital Systems Design" - I: Technical
Publications, 2008.
[9] Tien-Yu Wu, Ching-Tsing Jih, Jueh-Chi Chen and Chung-Yu Wu, "A
Low Glitch 10-bit 75-MHz CMOS Vidoe D/A Converter", January
1995
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