Combinational Logic

Analysis & Design

Design Example 1
Motor

can be turned ON/OFF from 3

separate locations
3 Switches
1 ON
0 OFF
1 Switch On Motor On
2 Switches On Motor Of
3 Switches On Motor On

Motor

On low input

Design Example
Temp

exceeds set pt switch of

motor
Temp Sensor o/p Low > set point
Turn On Alarm
Alarm Light On Low

Truth Table
S3 S2 S1 TS M

S3 S2 S1 TS M

Logic Function - Motor

S3
S2
S1

N3
TS

XOR
A

BC 00

0
1

01

11

10

Odd Function

XNOR
A
0
1

BC 00

01

11

m
4

10

Even Function

m
6

Logic Function - Alarm

A = TS

Implementation

NAND Repsn
AND - INVERT

INVERT-OR

A + B

DeMorgans

(AB)

F(A,B,C,D) = AB + BD
A
B
D

AB
BD

AND-OR

NAND Conversion

A
B
D

(AB)

(BD).

F(A,B,C,D) = AB + BD
(AB
)

A
B
D

(BD)

NAND

Multi -Level Gates

D
C

CD
G3

G1

B+CD
G4

A(B+CD
)

G5

A
G2

BC

F = BC + A(B+CD)

Multi -Level Gates-NAND

D
C

(CD)
CD
G1

G3

B+
(CD)
B+CD

(A(B+(CD))
G4

B
B

A(B+CD
)

G5

A
G2

BC(BC)

F = BC + A(B+CD)

Inference

SOP - NAND

NOR Repsn
OR- INVERT

INVERT-AND

A B

DeMorgans

(A+B)

F = (A+B)(C+D)E
A
B
C
D
E

G1

G2

A+B

C+D

(A+B)(C+D)E
G3

F = (A+B)(C+D)E-NOR
A
B
C
D
E
E

G1

A+B
(A+B)

G2

C+D
(C+D)

(A+B)(C+D)E
G3

Inference

POS - NOR

Other Combinations

AND , OR,NAND,NOR

Combination
DEGENERATE

NON- DEGENERATE

OR-OR
AND-AND

AND OR
NAND-NAND
NOR-OR
OR-NAND
OR AND
NOR-NOR
NAND-AND
AND-NOR

Other Implementation
AND-OR-INVERT
SOP F

OR-AND-INVERT
POS F

Implementations
A
0
1

BC 00

1
0

m
0

m
4

01

0
0

11

m
1

0
0

F = AB + AB+C
F = (AB + AB+C)

10

m
3

m
7

0
1

m
2

m
6

AND-OR-INVERT: ANDNOR
A
B
A
B
C

G1

G2

G3

NAND-AND

A
B
A
B
C
C

G1

G2

G3
G1

Implementations
A
0
1

BC 00

1
0

m
0

m
4

01

0
0

11

m
1

0
0

F= ABC + ABC

10

m
3

m
7

0
1

m
2

m
6

Simplify
F=

ABC + ABC
F = (A+B+C)(A+B+C)
F= [(A+B+C)(A+B+C)]

OR-AND-INVERT : ORNAND
A
B
C

G1

G3
A
B
C

G2

Two Variable NAND

Implementation
G2
A
B

G4

G1

G3

Parity Generation &

Checking
No.

of 1s
Even
Odd

Parity Generation
A

Parity Generation
A

BC 00

0
1

01

11

10

Odd Function

Parity Checking
A

Parity Checking
AB

CD 00

01

11

10

00

01

11

10

Combination
IMPLEMENTATION

AND OR
NAND-NAND
NOR-OR
OR-NAND
OR AND
NOR-NOR
NAND-AND
AND-NOR

K-MAP

SOP
SOP
SOP
SOP
POS
POS
SOP
SOP

Invert POS
Invert POS
Invert
Invert

Design Example 2
Multiply

2 two-input variable
Product of 2-bits four bits

Truth Table
A
1

A
0

B
1

B
0

P3 P2 P1 P0

A
1

A
0

B
1

B
0

P3 P2 P1 P0

P3
15
P3

= A1A0B1B0

P2
10,11,14
A1A0B1B0

+
A1A0B1B0+A1A0B1B0
A1A0B1+A1A0B1Bo
A1B1(Ao+A0B0)
A1B1(Ao+Bo)
A1B1A0+A1B1B0

P1

6,7,9,11,13,14 B1B000

01

A1A0

A1A0B1

A0B1B0

A1B1B0

11

10

00

01

11

10

A1A0B0

P0

5,7,13,15

A0B0

B1B0
00
A1A0

01

11

10

00

01

11

10

Logic Circuit
A0
B0

P0
P3
A1
B1

A1
B1
B0
A1
A0
B1

P2

Logic Circuit
A1
A0
B1
A0
B1
B0
A1
B1
B0
A1
A0
B0

P1

Seven Segment Displays

COMMON ANODE

COMMON CATHODE

R
Vcc

Common Anode Display

a
f

h
d

Design Example -3
Design

a logic that will convert a

NBCD value to 7-segment equivalent
a
f

h
d

Truth Table
A
0
0
0
0
0
0
0
0
1

B
0
0
0
0
1
1
1
1
0

C
0
0
1
1
0
0
1
1
0

D
0
1
0
1
0
1
0
1
0

a
0
1
0
0
1
0
1
0
0

b
0
0
0
0
0
1
1
0
0

c
0
0
1
0
0
0
0
0
0

d
0
1
0
0
1
0
0
1
0

e
0
1
0
1
1
1
0
1
0

f
0
1
1
1
0
0
0
1
0

g
1
1
0
0
0
0
0
1
0

SOP equations
= (1,4,6)
b = (5,6)
c = (2)
d = (1,4,7,9)
e = (1,3,4,5,7,9)
f = (1,2,3,7)
g = ( 0,1,7)
a

a
AB

CD 00

00

01

01

11

m1

m1
3

10

11

X
X

a = BD + ABCD

m1
5

m1
1

10

1
X
X

m
6

m14
m1
0

b
AB

CD 00

00

01

11

m1

01

m
m1
3

10

11

b = BCD+BCD

X
X

m1
5

m1
1

10

1
X
X

m
6

m14
m1
0

c
AB

CD 00

01

11

00

01

11

m1

m1
3

10

c = BCD

10

m
2

X
X

m1
5

m1
1

X
X

m14
m1
0

d
AB

CD 00

00

01

11

10

01

m
1

m1
m
8

X
1

11

m1
3

m
9

1
X
X

10

m
7

m1
5

m1
1

X
X

d = BCD + BCD + BCD

m14
m1
0

e
AB

CD 00

00

01

11

10

m
m1
m
8

01

m
m1
3

e = D + BC

m
9

11

1
1
X
X

10

m
7

m1
5

m1
1

X
X

m14
m1
0

f
AB

CD 00

01

00

01

11

m1

m1
3

10

11

1
1
X
X

f = BC + BC+ABD

10

m
2

m
7

m1
5

m1
1

X
X

m14
m1
0

g
AB
00

CD 00

01
11

01

m1

m1
3

10

11

1
X
X

g = ABC+BCD

10

m
7

m1
5

m1
1

X
X

m14
m1
0

7447
1C

VCC 16

2 B

f 15

3 LT

g 14

4 BI/
RBO
5

a 13

7447

RBI
6A

b
12
c 11

7D

d 10

8
GND

e 9