1

KSZ8041NL Eval Board Revision 1.0

REVISION HISTORY

Table of Contents

DATE

DESCRIPTION

PAGE 01:
PAGE 02:
PAGE 03:

REVISION

1/4/07

Initial Release

1.0

4/27/07

Added 100pF capacitor (C53) on REXT (pin 10) of KSZ8041NL.

1.1

Revision History
KSZ8041NL Board -- Block Diagram
KSZ8041NL Device

CONFIDENTIAL & PROPRIETARY

Title

KSZ8041NL Eval Board

Size

Document Number

Rev
1.1

Revision History
Date:
1

Friday, April 27, 2007

Sheet
5

of

KSZ8041NL EVAL BOARD - BLOCK DIAGRAM

D

3.3V
LDO

5V DC
INPUT

TX / RX pairs

KSZ8041NL

MII / RMII Port Connector

MII / RMII
Signals

10Base-T / 100Base-TX
Integrated Magnetic RJ-45 Jack
25 MHz XTAL
(MII mode)
B

50 MHz REF_CLK from MAC

(RMII mode)
Port Status
LED
Indicators

RESET

Configuration
Headers

CONFIDENTIAL & PROPRIETARY

Title

KSZ8041NL Eval Board

Size

Document Number

Rev
1.1

KSZ8041NL Board -- Block Diagram

Date:
1

Friday, April 27, 2007

Sheet
5

of

3.3V_NL

Notes:

1
2
3
4
SW PUSHBUTTON

C6
10uF

J1

10K

1N4148

+
C4
0.1uF

C3
22uF

CT

3
2

RD+

RX+_NL

CT

RD-

NC

CHS_GND

LED0_NL
LED1_NL

BYP

VIN

GND

EN

+
C5
0.1uF

TP1

R3

C10
0.1uF

C9
10uF

C11
0.1uF

J2

RX-_NL

1
2
3
4
5
6
7
8

RX-_NL
RX+_NL
TX-_NL
TX+_NL

TXD0
TXEN
TXC
INTRP
RXER
RXC
RXDV
VDDIO_3.3

GND
VDDPLL_1.8
VDDA_3.3
RXRX+
TXTX+
XO

24
23
22
21
20
19
18
17

CRS_NL
COL_NL
TXD3_NL
TXD2_NL
TXD1_NL
TXD0_NL
TXEN_NL
TXC_NL

R4
R5

33
33

R6

33

RXER_NL
RXC_NL
RXDV_NL

R7
R8
R9

33
33
33

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

INTRP_NL

C12
49.9

TX+_NL

R11

49.9

TX-_NL

R12

49.9

RX+_NL

49.9

RX-_NL

9
10
11
12
13
14
15
16

XO_NL

R13

C16
22pF

VCC
CRS
COL
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK
TX_ER
RX_ER
RX_CLK
RX_DV
RXD0
RXD1
RXD2
RXD3
MDC
MDIO
VCC

VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCC

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

Male MII Connector

KSZ8041NL

C17

Y1

0.1uF

U1

XI_NL

SIGNAL_GND_NL

MII / RMII Port

3.3V_NL

22pF

25MHz

Place SIGNAL_GND return of C14

close to SIGNAL_GND at 5V input
power to board.

3.3V_NL

XI
REXT
MDIO
MDC
RXD3
RXD2
RXD1
RXD0

R10

C14
C15
0.1uF

C2
47uF

MIC5216-3.3BM5

RST#_NL

CHASSIS_GND_NL

1000pF / 2kV

+5V DC
Power Input

4.7K

TD-

TX-_NL

C13
0.1uF

5V_NL

32
31
30
29
28
27
26
25

TD+

3.3A_NL 1.8VPLL_NL

TX+_NL

10
9

1000pF

100K

3.3V_NL
1

75 75

SHIELD
SHIELD

75 75

C7
0.1uF

RST#
LED1
LED0
CRS
COL
TXD3
TXD2
TXD1

1
2
3
4
5
6
7
8

C1
47uF

C8
10uF

RJ-45
Magnetic Jack

TDK TLA-6T718

OUT

FBEAD
+

S1
+

D1

R1

3.3V_NL
U2

R2

FB1

Push
Button
Reset

3.3A_NL

STEWARD
HI1206N101R-00

3.3A_NL

Power_ON
Reset

1. KSZ8041NL has a Paddle Ground on bottom side of chip.

Refer to datasheet for mechanical dimensions.
2. KSZ8041NL provides the 1.8VPLL supply for VDDPLL_1.8
(pin 2). Decouple 1.8VPLL power rail as shown.
3. Place components (Y1, C16, C17, C53, R14, R15) and (R10,
R11, R12, R13, C13, C15) close to respective pins of U1.

C53

R15

100pF

6.49K

Route both traces of each differential pair

as identical to each other as possible at 6mil
width/6mil parallel spacing, and at least 18
mils away from all other signals.

RXD0_NL
RXD1_NL
RXD2_NL
RXD3_NL
MDC_NL
MDIO_NL

R14

R16
R17
R20
R21

33
33
33
33

TP2
R18

R19

4.7K

NC

TP3

NC

C53 is an additional component to the PCB.

LED Mode

Rework C53 in parallel with R15 (as shown) at

location R15 of PCB.

Strapping Options (Refer to Datasheet for descriptions)

3.3V_NL

RMII Mode (option)

KSZ8041NL
PHY RMII Signals

The RMII signal connections between KSZ8041NL

PHY and external MAC are shown in the table to
the right.

PHYAD0

RXD3_NL

J3

JUMPER

R23

1K

PHYAD1

RXD2_NL

J4

JUMPER

R25

4.7K

PHYAD2

RXD1_NL

J5

JUMPER

R26

4.7K

For RMII mode,

CONFIG0

COL_NL

J6

JUMPER

R27

4.7K

1. Remove crystal circuit (Y1, C16, C17) and TXC

termination (R6).

CONFIG1

CRS_NL

J7

JUMPER

R28

4.7K

CONFIG2

RXDV_NL

J8

JUMPER

R29

4.7K

ISO

RXER_NL

J9

JUMPER

R30

4.7K

NWAYEN

LED0_NL

J10

JUMPER

R31

1K

SPEED

LED1_NL

J11

JUMPER

R32

1K

DUPLEX

RXD0_NL

J12

JUMPER

R33

1K

2. Populate R14 with 0 Ohm and R19 with 33 Ohm

to connect 50MHz Reference Clock (provided by
MAC side via J2 pin 12) to U1 pin 9 (XI input).

3. Select RMII mode by setting strapping pins

CONFIG[2:0] to '001'.
4. Connect J2 (RMII Port) to board with RMII MAC
(e.g. Micrel KSZ8893MQL Eval Board).

KSZ8893MQL
MAC RMII Signals

[01]

LED0

LINK/ACT

LINK

LED1

SPEED

ACT

3.3V_NL
LED1

Name

Pin #

Type

Name

Type

REFCLK

Input

REF_CLK

Input

TX_EN

23

Input

CRS_DV

Output

TXD[1]

25

Input

RXD[1]

Output

TXD[0]

24

Input

RXD[0]

Output

CRSDV

18

Output

TX_EN

Input

RXD[1]

15

Output

TXD[1]

Input

RXD[0]

16

Output

TXD[0]

Input

Title

RX_ER

20

Output

TX_ER

Input

Size

R22

220

LED0_NL

R24

220

LED1_NL

LEDx2

CONFIDENTIAL & PROPRIETARY

KSZ8041NL Eval Board

Document Number

Rev
1.1

KSZ8041NL Device
Date:

[00]

Friday, April 27, 2007

Sheet
5

of