Name

No
of
bytes

No
of machine
cycles

Machine cycles

MOV A,B

OF

MOV A,M

OF,MR

MOV M,A
MVI B,08H
MVI M,08H
LXI D,2000H
LDA 8000H
STA 8000H
SHLD 8000H
LHLD 2020H
LDAX H
STAX D
XCHG

1
2
2
3
3
3
3
3
1
1
1

2
2
2
3
4
4
5
5
2
2
1

OF,MW
OF,MR
OF,MR,MR
OF,MR,MR
OF,MR,MR,MR
OF,MR,MR,MW
OF,MR,MR,MW,MW
OF,MR,MR,MR,MR
OF,MR
OF,MW
OF

ADD B
ADD M
ADC C

1
1
1

1
2
1

OF
OF,MR
OF

Example
MOV r1, r2
MOV r, m
MOV M, r.
MVI r, data
MVI M, data.
LXI rp, data 16
LDA addr.
STA addr.
SHLD addr.
LHLD addr.
LDAX rp.
STAX rp
XCHG.
ADD r.
ADD M.
ADC r.

ADC M. .
ADI data
ACI data
DAD rp.
SUB r.
SUB M.
SBB r.
SBB M. .
SUI data.
SBI data.
INR r
INR M.
DCR r.
DCR M.
. INX rp.
DCX rp
DAA

ADC M
ADI 27H
ACI 34H
DAD B
SUB D
SUB M
SBB D
SBB M
SUI 86H
SUI C2H
INR B
INR M
DCR D
DCR M
INX D
DCX H
DAA

1
2
2
1
1
1
1
1
2
2
1
1
1
1
1
1
1

2
2
2
3
1
2
1
2
2
2
1
3
1
3
1
1
1

OF,MR
OF,MR
OF,MR
OF,B,B
OF
OF,MR
OF
OF,MR
OF,MR
OF,MR
OF
OF,MR,MW
OF
OF,MR,MW
OF
OF
OF

ANA r.
ANA M.
ANI data.
ORA r.
ORA M.
ORI data.

ANA C.
ANA M.
ANI 06H.
ORA D.
ORA M.
ORI A0H.

1
1
2
1
1
2

1
2
2
1
2
2

OF
OF,MR
OF,MR
OF
OF,MR
OF,MR

XRA r.
XRA M.
XRI data.
CMA.
CMC.
STC.
CMP r.
CMP M.

XRA C
XRA M.
XRI 80H.
CMA.
CMC.
STC.
CMP D
CMP M.

1
1
2
1
1
1
1
1

1
2
2
1
1
1
1
2

OF
OF,MR
OF,MR
OF
OF
OF
OF
OF,MR

CPI data.

CPI 30H.

OF,MR

RLC

RLC

OF

RRC.
RAL.
RAR.

RRC.
RAL.
RAR.

1
1
1

1
1
1

OF
OF
OF

3
3

2 or 3

OF ,MR or OF,MR,MR

JMP addr (label).

JZ addr (label).

JNZ addr (label)

JC addr (label).

3
3

2 or 3
2 or 3

OF ,MR or OF,MR,MR
OF ,MR or OF,MR,MR

JNC addr (label).

JP addr (label).
JM addr (label).
JPE addr (label)
JPO addr (label)

3
3
3
3
3

2 or 3
2 or 3
2 or 3
2 or 3
2 or 3

OF ,MR or OF,MR,MR
OF ,MR or OF,MR,MR
OF ,MR or OF,MR,MR
OF ,MR or OF,MR,MR
OF ,MR or OF,MR,MR

OF,MR,MR,MW,MW

CZ addr (label).
CNZ addr (label)
CC addr (label).

1
3
3
3

3
2 or 5
2 or 5
2 or 5

OF,MR,MR,MW,MW
OF,MR,MR,MW,MW
OF,MR,MR,MW,MW

CNC addr (label).

CP addr (label).
CM addr (label).
CPE addr (label)
CPO addr (label)
RZ

3
3
3
3
3
1

2 or 5
2 or 5
2 or 5
2 or 5
2 or 5

OF,MR,MR,MW,MW
OF,MR,MR,MW,MW
OF,MR,MR,MW,MW
OF,MR,MR,MW,MW
OF,MR,MR,MW,MW

CALL addr (label)

(Unconditional )

RET

RET

RZ

RNZ
RC

RNZ
RC

1
1

RNC
RP
RM
RPE
RPO
RST n
(RST 0-7)

RNC
RP
RM
RPE
RPO

1
1
1
1
1

RST 1

PCHL

5
IN port-address.
OUT port-address
PUSH rp
PUSH PSW
POP rp
POP PSW
HLT
XTHL
SPHL
EI
DI
SIM
RIM

IN 80H.
OUT 80H
PUSH B
PUSH PSW
POP D
POP PSW
HLT
XTHL
SPHL
EI
DI
SIM
RIM

2
2
1
1
1
1
1
1
1
1
1
1
1

3
3
3
3
3
3
1
4
1
1
1
1
1

OF,MR,IOR
OF,MR,IOW
OF,MR,MW
OF,MR,MW
OF,MR,MR
OF,MR,MR
OF
OF,MR,MR,MW,MW
OF
OF
OF
OF
OF

NOP

NOP

OF

No of
T-states
4

Addressing
Flags
modes
affected
1. Data Transfer Group
Register
None

Register indirect

7
7
7
10
13
13
16
16
7
7
4

Register indirect
Immediate
Immediate
Immediate
Direct
Direct
Direct
Direct
Indirect
Indirect

4
7
4

None

None
None
None
None
None
None
None
None
None
None
None
2. Arithmetic Group
REGISTER
ALL S,Z,AC,P,CY
INDIRECT
ALL S,Z,AC,P,CY
REGISTER
ALL S,Z,AC,P,CY

7
7
7
10
4
7
4
7
7
7
4
10
4
10
6
6
4
4
7
7
4
7
7

INDIRECT
IMMEDIATE
IMMEDIATE
REGISTER
REGISTER
INDIRECT
REGISTER
INDIRECT
IMMEDIATE
IMMEDIATE
REGISTER
INDIRECT
REGISTER
INDIRECT
INDIRECT
INDIRECT

ALL S,Z,AC,P,CY
ALL S,Z,AC,P,CY
ALL S,Z,AC,P,CY
ALL S,Z,AC,P,CY
ALL S,Z,AC,P,CY
ALL S,Z,AC,P,CY
ALL S,Z,AC,P,CY
ALL S,Z,AC,P,CY
ALL S,Z,AC,P,CY
ALL S,Z,AC,P,CY
ALL S,Z,AC,P,CY
ALL S,Z,AC,P,CY
ALL S,Z,AC,P,CY

ALL S,Z,AC,P,CY
3. Logical Group
REGISTER
ALL S,Z,AC,P,CY
INDIRECT
ALL S,Z,AC,P,CY
IMMEDIATE ALL S,Z,AC,P,CY
REGISTER
ALL S,Z,AC,P,CY
INDIRECT
ALL S,Z,AC,P,CY
IMMEDIATE ALL S,Z,AC,P,CY

4
7
7
4
4
4
4
7

REGISTER
INDIRECT
IMMEDIATE

REGISTER
INDIRECT

ALL S,Z,AC,P,CY
ALL S,Z,AC,P,CY
ALL S,Z,AC,P,CY
ALL S,Z,AC,P,CY
ALL S,Z,AC,P,CY
ALL S,Z,AC,P,CY
ALL S,Z,AC,P,CY

IMMEDIATE

ALL S,Z,AC,P,CY

ALL S,Z,AC,P,CY

4
4
4

ALL S,Z,AC,P,CY

4.
7 or 10

Direct

Branch Group
None

7 or 10
7 or 10

Direct
Direct

None
None

7 or 10
7 or 10
7 or 10
7 or 10
7 or 10

Direct
Direct
Direct
Direct
Direct

None
None
None
None
None

18

Direct

None

10
9 or 18
9 or 18
9 or 18

Direct
Direct
Direct
Direct

None
None
None
None

9 or 18
9 or 18
9 or 18
9 or 18
9 or 18

Direct
Direct
Direct
Direct
Direct

None
None
None
None
None
None

None
None
None
None
None
None
None
12

None

6
10
10
12
12
10
10
4
16
6
4
4
4
4

5. Stack, I/O and Machine Control Group

Direct
None
Direct
None
Register
None
Register
None
Register
None
Register
None
None
None
None
None
None
None
None

None

Explanation

Group
Move Data; Move the content of the one register to another.
Move the content of memory to register. r [M]
Move the content of register to memory. M [r]
Move immediate data to register. [r] data.
Move immediate data to memory. M data.
Load register pair immediate). [rp] data 16 bits, [rh] <- 8 LSBs of data.
Load Accumulator direct. [A] [addr].
Store accumulator direct. [addr] [A].
Store H-L pair direct [addr] [L], [addr+1] [H].
Load H-L pair direct. [L] [addr], [H] [addr+1].
LOAD accumulator indirect [A] [[rp]]
Store accumulator indirect [[rp]] [A].
Exchange the contents of H-L with D-E pair [H-L] <--> [D-E].

roup
(Add register from accumulator). [A] <--- [A] + [r].
(Add memory to accumulator) [A] [A] + [[H-L]].
(Add register with carry to accumulator). [A] <--- [A] + [r] + [CS].

(Add memory with carry to accumulator) [A] <--- [A] + [[H-L]] [CS]
(Add immediate data to accumulator) [A] <--- [A] + data.
(Add with carry immediate data to accumulator). [A] <--- [A] + data + [CS].
(Add register paid to H-L pair). [H-L] <--- [H-L] + [rp].
(Subtract register from accumulator). [A] <--- [A] [r].
(Subtract memory from accumulator). [A] <--- [A] [[H-L]].
(Subtract register from accumulator with borrow). [A] <--- [A] [r] [CS].
(Subtract memory from accumulator with borrow). [A] <--- [A] [[H-L]] [CS]
(Subtract immediate data from accumulator) [A] <--- [A] data.
Subtract immediate data from accumulator with borrow[A] <--- [A] data [CS].
(Increment register content) [r] <--- [r] +1.
(Increment memory content) [[H-L]] <-- [[H-L]] + 1.
(Decrement register content). [r] <--- [r] 1.
(Decrement memory content) [[H-L]] <--- [[H-L]] 1.
(Increment register pair) [rp] <--- [rp] 1.
(Decrement register pair) [rp] <--- [rp] -1.
(Decimal adjust accumulator) .

up
(AND register with accumulator) [A] L<--- [A] ^ [r].
(AND memory with accumulator). [A] <---[A] ^ [[H-L]].
(AND immediate data with accumulator) [A] <-- [A] ^ data.
(OR register with accumulator) [A] <-- [A] v [r].
(OR memory with accumulator) [A] <-- [A] v [[H-L]]
(OR immediate data with accumulator) [A] <-- [A] v data.

(EXCLUSIVE OR register with accumulator) [A] <--[A] v [r]

(EXCLUSIVE-OR memory with accumulator) [A] <-- [A] v [[H-L]]
(EXCLUSIVE-OR immediate data with accumulator) [A] <-- [A] v data.
(Complement the accumulator) [A] <-- [A]
(Complement the carry status) [CS] <-- [CS]
(Set carry status) [CS] <-- 1.
(Compare register with accumulator) [A] [r]
(Compare memory with accumulator) [A] [[H-L]]

(Compare immediate data with accumulator) [A] data.

The 2nd byte of the instruction is data, and it is subtracted from the content of the accumulator. The status flag
set according to the result of subtraction. But the result is discarded. The content of the accumulator remains
unchanged.

(Rotate accumulator left) [An+1] <-- [An], [A0] <- [A7],

The content of the accumulator is rotated left by one bit. The seventh bit of the accumulator is moved to carr
as well as to the zero bit of the accumulator

(Rotate accumulator right) [A7] <-- [A0], [CS] <-- [A0], [An] <--[An+1].
The content of the accumulator is rotated right by one bit. The zero bit of the accumulator is moved to the sev
bit as well as to carry bit.
Only CS flag is affected
(Rotate accumulator left through carry) [An+1] <-- [An], [CS] <-- [A7], [A0] <-- [CS].
(Rotate accumulator right through carry) [An] <-- [An+1], [CS] <-- [A0], [A7] <-- [CS]

oup
(Unconditional jump: jump to the instruction specified by the address). [PC] Label.
(Jump if the result is zero)

(Jump if the result is not zero)

(Jump if there is a carry)
(Jump if there is no carry)
(Jump if the result is plus)
(Jump if the result is minus)
(Jump if even parity)
(Jump if odd parity)

CALL: call the subroutine identified by the operand)CALL instruction is used to call a subroutine. Before the
control is transferred to the subroutine, the address of the next instruction of the main program is saved in th
stack. The content of the stack pointer is decremented by two to indicate the new stack top. Then the program
jumps to subroutine starting at address specified by the label.
(Return from subroutine)
(Call on zero)
(Call on no zero)
Call on carry)
(Call with no carry)
(Call on plus)
(Call on minus)
(Call on even parity)
(Call on odd parity)
(Return on zero)

(Return on no zero)
(Return on carry)
(Return with no carry)
(Return on plus)
(Return on minus)
(Return on even parity)
(Return on odd parity)
(Restart)

load progrma counter with hl contents pc<--hl

Control Group
(Input to accumulator from I/O port) [A] [Port]
(Output from accumulator to I/O port) [Port] [A]
(Push the content of register pair to stack)
(PUSH Processor Status Word)
(Pop the content of register pair, which was saved, from the stack)
(Pop Processor Status Word)
(Halt)
(Exchange stack-top with H-L)
(Move the contents of H-L pair to stack pointer)
(Enable Interrupts)
(Disable Interrupts)
(Set Interrupt Masks)
(Read Interrupt Masks)

(No Operation