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X:\Work - ECE - 574\sevenseg\sevenseg.srcs\sources_1\new\seven_seg.

vhd

Tuesday, September 08, 2015 5:55 AM

----------------------------------------------------------------------------------- Company:
-- Engineer:
--- Create Date: 09/04/2015 03:19:11 AM
-- Design Name:
-- Module Name: seven_seg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity seven_seg is
Port ( SW : in STD_LOGIC_VECTOR (7 downto 0);
AN : out STD_LOGIC_VECTOR (7 downto 0);
segs : out STD_LOGIC_VECTOR (6 downto 0);
clk100Hz : in std_logic
);
end seven_seg;
architecture Behavioral of seven_seg is
signal count : integer range 0 to 9;

constant
constant
constant
constant
constant
constant
constant
constant
constant
constant

zero : std_logic_vector(6 downto 0) := "1000000";


one : std_logic_vector(6 downto 0) := "1111001";
two : std_logic_vector(6 downto 0) := "0100100";
three : std_logic_vector(6 downto 0) := "0110000";
four : std_logic_vector(6 downto 0) := "0011001";
five : std_logic_vector(6 downto 0) := "0010010";
six : std_logic_vector(6 downto 0) := "0000010";
seven : std_logic_vector(6 downto 0) := "1111000";
eight : std_logic_vector(6 downto 0) := "0000000";
nine : std_logic_vector(6 downto 0) := "0010000";

signal clk_1Hz,clk_3Hz : std_logic := '0'; -- define 1Hz clk and start value (for simulation)
signal count1,count2: integer range 0 to 9;
signal count3 : integer range 1 to 4 := 0 ;
begin
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X:\Work - ECE - 574\sevenseg\sevenseg.srcs\sources_1\new\seven_seg.vhd

Tuesday, September 08, 2015 5:55 AM

-- 10Hz clock
clock_1Hz:process(clk100Hz)
variable counter_100M : integer range 0 to 5_000_000;
begin
if rising_edge(clk100Hz) then
counter_100M := counter_100M + 1;
if counter_100M = 50_000_00 then
clk_1Hz <= NOT clk_1Hz;
counter_100M := 0;
end if;
end if;
end process;
-- 1KHz clock to switch display
clock_3hz:process(clk100Hz, count3)
variable counter_100M : integer range 0 to 50_000;
begin
if rising_edge(clk100Hz) then
counter_100M := counter_100M + 1;
if counter_100M = 50_000 then
clk_1Hz <= NOT clk_1Hz;
--if count3 <= 4 then
-- count3 <= 0;
--else
count3 <= count3 + 1;
--end if;
counter_100M := 0;
end if;
end if;
end process;

-- Update count
update_count: process(clk_1Hz)
begin
if rising_edge(clk_1Hz) then
if count2 = 9 then
count2<=0;
else
if count1 = 9 then
count1 <= 0;
count2 <= count2+1;
else
count1 <= count1 + 1;
end if;
end if;
end if;
end process;
-- Update Display
update_disp:process(count3)
begin
if count3 = 1 then
AN <= "11111110"; count <= count1;
elsif count3 = 2 then
AN <= "11111101"; count <= count2;
elsif count3 = 3 then
AN <= "11111011"; count <= 0;
elsif count3 = 4 then
AN <= "11110111";
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X:\Work - ECE - 574\sevenseg\sevenseg.srcs\sources_1\new\seven_seg.vhd

Tuesday, September 08, 2015 5:55 AM

count <= 0;
else
AN <= "11111111";
-- counter from 00 to 11
end if;
end process;
--display the count value on the seven segments
seven_segment_decoder_process: process(count)
begin
case count is
when 0 => segs <= zero;
when 1 => segs <= one;
when 2 => segs <= two;
when 3 => segs <= three;
when 4 => segs <= four;
when 5 => segs <= five;
when 6 => segs <= six;
when 7 => segs <= seven;
when 8 => segs <= eight;
when 9 => segs <= nine;
end case;
end process seven_segment_decoder_process;
end Behavioral;

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