Lenovo G400 LA-9632P

A
Compal Confidential
2
G400/G500 UMA M/B Schematics Document

Intel Ivy Bridge Processor with DDRIII + Panther Point PCH
2013-02-27
3
LA-9632P
REV:1.0
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/06/15
2012/07/11
Deciphered Date
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Cover Page
Rev
1.0
LA-9632P
Date:
Sheet
Wednesday, February 27, 2013

E
of
60
Compal confidential
Project Name : VIWGP (14") / VIWGR (15")
Chief River
1
Intel
Processor
Ivy Bridge
Memory Bus
Dual Channel
204pin DDRIII-SO-DIMM X2
rPGA989
37.5mm x 37.5mm
Page 12, 13
BANK 0, 1, 2
DDR3
1600MHz
1333MHz
DDR3
1066MHz
DDR3
Page 5~11
FDI *8
2.7GT/s
DMI2 *4
5GT/s
LVDS Conn.
Left USB3.0 x2
Page 23
USB30 x2
HDMI Conn.
USB20 x6
Page 25
CRT Conn.
Page 24
LAN
RJ45 Conn.
Page 28
PCIe Port 0
Atheros
AR8162/QCA8172(10/100)
PCIe x1
Page 27
Intel
PCH
Panther Point
SATA Gen3
Int. Camera
USB30 Port 0,1

Page 35
USB20 Port 9
Page 35
USB20 Port 3
Page 23
Touch Screen
Card Reader
USB20 Port 2
Page 35
USB20 Port 11 page 28
PCIe Port 1
Page 30
ODD Conn.
SATA
SATA Port 2
PCIe Mini Card

WLAN
Realtek RTS5170
HDD Conn.
SATA Port 0
FCBGA 989Balls
25mm x 25mm
Right USB2.0
Page 30
3
PCIe x1
Audio Codec
Page 26
CONEXANT
CX20757
AZALIA
Page 31
Page 14~22
Int. MIC Conn.
Int. Speaker Conn.
Audio Combo Jacks
Page 31
Page 31
Page 31
Sub-borad
SPI ROM
15"
14"
Power/B
HP & MIC
EC
2MB + 4MB
ENE KB9012
Page 14
Page 32
(LID)
LS9631
4
USB/B
Thermal Sensor
ODD/B
LS9632
Page 29
Touch Pad
Page 33
Int. KBD
Page 33
LS9634
IO/B
2011/06/15
Issued Date
(LED, LID)
LS9633
Compal Secret Data
Switch/B
(Card Reader)
2012/07/11
Deciphered Date
Title
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
LS9635
Date:
MB Block Diagram
Rev
1.0
LA-9632P
Sheet

E
of
60
BOARD ID Table
Voltage Rails
SIGNAL
+5VS
+3VS
power
plane
+1.5VS
+V1.05S_VCCP
+5VALW
+1.5V
+VCC_CORE
+VGA_CORE
+B
+3VALW
+VCC_GFXCORE_AXG
+1.8VS
State
Board ID
0
1
2
3
4
5
6
7
PCB Revision
0.1
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
+VALW
+V
+VS
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
STATE
Full ON
Clock
+0.75VS
+1.05VS
Vcc
R694
Board ID
S0
S3
0
1
2
3
3.3V
Board ID / SKU ID Table for AD channel
100K +/- 1%
VAD_BID min
0 V
0.347V
0.423V
0.541V
R695
0
12K +/- 1%
15K +/- 1%
20K +/- 1%
V AD_BID typ
0 V
0.354V
0.430V
0.550V
VAD_BID max
0 V
0.360V
0.438V
0.559V
EC AD
0x00 - 0x0B
0x0C - 0x1C
0x1D - 0x26
0x27 - 0x30
MP
PVT
DVT
EVT
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
USB Port Table
UHCI0
UHCI1
EHCI1
UHCI2
EC SM Bus2 address
EC SM Bus1 address
Device
Address
Device
Address
Smart Battery
0001 011x
Thermal Sensor
0100 1100
PCH SM Bus address
UHCI3
UHCI4
AMD-GPU SM Bus address
Device
Address
Device
DDR_JDIMM1
1010 000x A0h
Internal thermal sensor 0100 0001 41h
DDR_JDIMM2
1010 010x A4h
BOM Structure Table
USB 2.0 Port
EHCI2
UHCI5
Address
UHCI6
0
1
2
3
4
5
6
7
8
9
10
11
12
13
3 External
USB Port
USB Port (Left Side)USB3.0
USB Port (Left Side)USB3.0
Touch Screen
Camera
USB Port (Right Side USB-BD)

Mini Card(WLAN)
Card Reader
60%86&RQWURO7DEOH
6285&(
60%B(&B&.
60%B(&B'$
60%B(&B&.
60%B(&B'$
4
3&+B60%&/.
.%
9$/:
.%
96
3&+
3&+B60%'$7$ 9$/:
3&+B60/&/.
3&+
3&+B60/'$7$ 9$/:
60/&/.
3&+
60/'$7$
9$/:
9*$
%$77
.%
62',00 :/$1
7KHUPDO
6HQVRU
3&+
96
9$/:
96
96
96
96
9*6
9*6
9$/:
Item
BOM Structure
VIWGP (14")
14@
15@
VIWGR (15")
HDMI Logo
45@
LAN 10/100
8162@
LAN 10/100
8172@
LAN Switch mode
SWR@
LAN LDO Mode
LDO@
LAN Gas tube
GAS@
Camera
CMOS@
HDMI
HDMI@
HM76@
PCH is HM76
HM70@
PCH is HM70
PCH is NM70
NM70@
VGA is Mars XT
Mars@
VGA is Sun Pro
Sun@
PX@
For VGA
X76@
For VRAM and Strap
For UMA Strap
UMA@
Microphone
MIC@
Touch Screen
TS@
Connector
ME@
Board ID for EVT
EVT@
Board ID for DVT
DVT@
Board ID for PVT
PVT@
For USB2.0 (All PCH)
USB2@
For USB3.0 (HM76,HM70) USB3@
For share ROM
SROM@
For non-share ROM
NOSROM@
2011/06/15
Issued Date
Compal Secret Data
2012/07/11
Deciphered Date
Title
Size
B
Date:
Notes List
Document Number
Rev
1.0
LA-9632P
Sheet

E
of
60
Compal Secret Data
2011/06/15
Issued Date
Deciphered Date
2012/07/11
Title
VGA Notes List
Custom
Rev
1.0
LA-9632P
Date:
Sheet

1
of
60
ZZZ1
14@
ZZZ2
14"_UMA_PCB_LA9632P
15"_UMA_PCB_LA9632P
+V1.05S_VCCP
DA6000WP100
PCB 0Y0 LA-9632P REV0 M/B UMA 5
JCPU1A
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
B28
B26
A24
B23
<16>
<16>
<16>
<16>
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
<16>
<16>
<16>
<16>
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
G21
E22
F21
D21
G22
D22
F20
C21
A21
H19
E19
F18
B21
C20
D18
E17
A22
G19
E20
G18
B20
C19
D19
F17
<16> FDI_FSYNC0
<16> FDI_FSYNC1
J18
J17
<16> FDI_INT
H20
<16> FDI_LSYNC0
<16> FDI_LSYNC1
J19
H17
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC
R7
24.9_0402_1%
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
eDP_HPD
A18
A17
B16
C15
D15
C17
F16
C16
G15
C18
E16
D16
F15
eDP_COMPIO
eDP_ICOMPO
eDP_HPD#
eDP_AUX
eDP_AUX#
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
eDP
EDP_COMP
eDP_COMPIO and ICOMPO signals

should be shorted near balls
and routed with typical
impedance <25 mohms
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
PCI EXPRESS* - GRAPHICS
<16>
<16>
<16>
<16>
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
DMI
B27
B25
A25
B24
+V1.05S_VCCP
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
Intel(R) FDI
<16>
<16>
<16>
<16>
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
J22
J21
H22
PEG_COMP
PEG_ICOMPI and RCOMPO signals should be

shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with max length = 500 mils
- typical impedance = 14.5 mohms
R1
24.9_0402_1%
15@
DA6000WP000
PCB 0Y0 LA-9632P REV0 M/B UMA 3
PEG Static Lane Reversal - CFG2 is for the 16x
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
1: Normal Operation; Lane #

socket pin map definition
CFG2
definition matches
0:Lane Reversed
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
B
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
TYCO_2013620-2_IVY BRIDGE
ME@
Compal Secret Data
2011/06/15
Issued Date
Deciphered Date
2012/07/11
Title

PROCESSOR(1/7) DMI,FDI,PEG
Custom
Rev
1.0
LA-9632P
Date:
Sheet
1
of
60
JCPU1B
D
AN34
PROC_SELECT#
SKTOCC#
+V1.05S_VCCP
AL33
H_CATERR#
R9
62_0402_5%
AN33
<32> H_PECI
R15
56_0402_5%
1
2
H_PROCHOT#
<32,36,37,43> H_PROCHOT#
AL32
H_PROCHOT#_R
AN32
<19> H_THRMTRIP#
CATERR#
THERMAL
T48
CLOCKS
<19> H_SNB_IVB#
PECI
PROCHOT#
THERMTRIP#
BCLK
BCLK#
DPLL_REF_CLK
DPLL_REF_CLK#
SM_DRAMRST#
A28
A27
CLK_CPU_DMI <15>
CLK_CPU_DMI# <15>
A16
A15
2
2
R12
R13
1 1K_0402_5%
1 1K_0402_5%
R8
H_DRAMRST#
AK1
A5
A4
SM_RCOMP0 2 R16
SM_RCOMP1 2 R17
SM_RCOMP2 2 R18
+V1.05S_VCCP
H_DRAMRST# <7>
+V1.05S_VCCP
DDR3
MISC
C26
MISC
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
1 140_0402_1%
1 25.5_0402_1%
1 200_0402_1%
DDR3 Compensation Signals

RP13
TCK
TMS
TRST#
SM_DRAMPWROK
2
2
BUF_CPU_RST#
AR33
RESET#
ESD
TDI
TDO
XDP_TCK
XDP_TMS
XDP_TRST#
AR28
AP26
XDP_TDI
XDP_TDO
1
2
3
4
AR26
AR27
AP30
8
7
6
5
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_TCK
51_0804_8P4R_5%
C46
100P_0402_50V8J
ESD
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
AL35 XDP_DBRESET#
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
R28
1 1K_0402_5%
+3VS
V8
C549
22P_0402_50V8J
R29
1
2 PM_DRAM_PWRGD_R
130_0402_5%
R27
10K_0402_5%
UNCOREPWRGOOD
XDP_PRDY#
XDP_PREQ#
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7
AP33
<19> H_CPUPWRGD
PM_SYNC
JTAG & BPM
AM34
<16> H_PM_SYNC
PWR MANAGEMENT
AP29
AP27
PRDY#
PREQ#
C45
47P_0402_50V8J
ESD
+3VALW
ME@
Buffered reset to CPU

+1.5V_CPU_VDDQ
+3VS
B
R30
200_0402_5%
PM_SYS_PWRGD_BUF
R32
75_0402_5%
BUF_CPU_RST#
R34
43_0402_1%
1
2
U2
BUFO_CPU_RST# 4
NC
Y
A
1
2
3V
PCH_PLTRST#
PCH_PLTRST# <18>
SN74LVC1G07DCKR_SC70-5
74AHC1G09GW_TSSOP5
<16> PM_DRAM_PWRGD
1 R161
2
10K_0402_5%
+3VS
U1
+V1.05S_VCCP
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title

PROCESSOR(2/7) PM,XDP,CLK
Rev
1.0
LA-9632P
Date:
Sheet

1
of
60
JCPU1C
JCPU1D
<13> DDR_B_D[0..63]
C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
V6
<12> DDR_A_BS0
<12> DDR_A_BS1
<12> DDR_A_BS2
AE8
AD9
AF9
<12> DDR_A_CAS#
<12> DDR_A_RAS#
<12> DDR_A_WE#
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]
RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]
SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]
DDR SYSTEM MEMORY A
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
RSVD_TP[10]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
M_CLK_DDR0 <12>
M_CLK_DDR#0 <12>
DDR_CKE0_DIMMA <12>
AA5
AB5
V10
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
M_CLK_DDR1 <12>
M_CLK_DDR#1 <12>
DDR_CKE1_DIMMA <12>
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
DDR_CS0_DIMMA# <12>
DDR_CS1_DIMMA# <12>
AH3
AG3
AG2
AH2
M_ODT0 <12>
M_ODT1 <12>
C4
G6
J3
M6
AL6
AM8
AR12
AM15
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS#[0..7] <12>
D4
F6
K3
N6
AL5
AM9
AR11
AM14
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS[0..7] <12>
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_MA[0..15] <12>
<13> DDR_B_BS0
<13> DDR_B_BS1
<13> DDR_B_BS2
<13> DDR_B_CAS#
<13> DDR_B_RAS#
<13> DDR_B_WE#
ME@
C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA9
AA7
R6
AA10
AB8
AB9
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]
RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]
SB_CS#[0]
SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]
DDR SYSTEM MEMORY B
<12> DDR_A_D[0..63]
AB6
AA6
V9
SB_ODT[0]
SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
AE2
AD2
R9
M_CLK_DDR2 <13>
M_CLK_DDR#2 <13>
DDR_CKE2_DIMMB <13>
AE1
AD1
R10
M_CLK_DDR3 <13>
M_CLK_DDR#3 <13>
DDR_CKE3_DIMMB <13>
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
DDR_CS2_DIMMB# <13>
DDR_CS3_DIMMB# <13>
AE4
AD4
AD5
AE5
M_ODT2 <13>
M_ODT3 <13>
D7
F3
K6
N3
AN5
AP9
AK12
AP15
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS#[0..7] <13>
C7
G3
J6
M3
AN6
AP8
AK11
AP14
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS[0..7] <13>
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_MA[0..15] <13>
ME@
+1.5V
H_DRAMRST#
<6> H_DRAMRST#
R38
1K_0402_5%
2
DDR3_DRAMRST# <12,13>
Q2
LBSS138LT1G_SOT-23-3
R39
4.99K_0402_1%
DDR3_DRAMRST#_R
R37
1K_0402_5%
<10,15> DRAMRST_CNTRL_PCH
@
1 R48
2
0_0402_5%
DRAMRST_CNTRL_PCH_R
Compal Secret Data
C35
0.047U 16V K X7R 0402
Eiffel used 0.01u

Module design used 0.047u
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title
Rev
1.0
LA-9632P
Date:

PROCESSOR(3/7) DDRIII
Sheet

1
of
60
CFG Straps for Processor
Interl request AH26 short GND

check on EVT phase
+VCC_GFXCORE_AXG
@
R252
49.9_0402_1%
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
2 100_0402_1%
R88 1
2 100_0402_1%
VCC_AXG_VAL_SENSE
VSS_AXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
AJ31
AH31
AJ33
AH33
AJ26
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29
@
R257
49.9_0402_1%
VSS_VAL_SENSE
@
R255
49.9_0402_1%
J20
B18
J15
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
T13
1: Normal Operation; Lane #

socket pin map definition
CFG2
L7
AG7
AE7
AK2
definition matches
0:Lane Reversed
CFG4
W8
R42
1K_0402_1%
AT26
AM33
AJ27
T8
J16
H16
G16
CFG4
1 : Disabled; No Physical Display Port

attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
RSVD5
VSS_AXG_VAL_SENSE
PAD
Display Port Presence Strap

RSVD37
RSVD38
RSVD39
RSVD40
RESERVED
R82 1
AH27
AH26
VCC_DIE_SENSE
VSS_DIE_SENSE
@
R253
49.9_0402_1%
+VCC_CORE
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG
CFG4
AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29
PEG Static Lane Reversal - CFG2 is for the 16x
JCPU1E
RSVD24
RSVD25
RSVD27
RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5
RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9
RSVD_NCTF10
RSVD51
RSVD52
BCLK_ITP
BCLK_ITP#
RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13
KEY
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
AN35
AM35
CFG[6:5]
10: x8, x8 - Device 1 function 1 enabled ; function 2

disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
AT2
AT1
AR1
B1
ME@
PEG DEFER TRAINING
CFG7
1: (Default) PEG Train immediately following xxRESETB

de assertion
0: PEG Wait for BIOS for training
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title

PROCESSOR(4/7) RSVD,CFG
Rev
1.0
LA-9632P
Date:
Sheet

1
of
60
JCPU1F
POWER
+V1.05S_VCCP
+VCC_CORE
8.5A
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
+V1.05S_VCCP
R46
75_0402_5%
VIDALERT#
VIDSCLK
VIDSOUT
AJ29
AJ30
AJ28
H_CPU_SVIDALRT#
R50
1 R47
2 43_0402_5%
1 130_0402_5%
VR_SVID_CLK series-resistors close to VR

VR_SVID_ALRT# <43>
VR_SVID_CLK <43>
VR_SVID_DAT <43>
+V1.05S_VCCP
0.1uF on power side

B
VCC_SENCE 100ohm +-1% pull-up to VCC near processor
+VCC_CORE
Trace Impedance =27-33 ohm

Trace Length Matc < 25 mils
2
AJ35
AJ34
VCCSENSE <43>
VSSSENSE <43>
1
VCC_SENSE
VSS_SENSE
R51
100_0402_1%
VCCIO_SENSE
VSS_SENSE_VCCIO
B10
A10
VSSIO_SENSE_L
R54
100_0402_1%
VCCIO_SENSE <42>
1
R74 2VSSIO_SENSE
10_0402_1%
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO40
SVID
SENSE LINES
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
CORE SUPPLY
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
PEG AND DDR
QC=94A
DC=53A
R74 & R79 put together

VSSIO_SENSE_L <42>
+V1.05S_VCCP
R79
2
1
10_0402_1%
VSS_SENCE 100ohm +-1% pull-down to GND near processor

Compal Secret Data
Issued Date
2011/06/15
ME@
Deciphered Date
2012/07/11
Title
PROCESSOR(5/7) PWR,BYPASS
Rev
1.0
LA-9632P
Date:
Sheet
1
of
60
+1.5V_CPU_VDDQ
+1.5V
D
+VREF_DQ_DIMMA
+VREF_DQ_DIMMB
Q6
2
G
<15,7>
+V_DDR_REFA_R
+V_DDR_REFB_R
DRAMRST_CNTRL_PCH 2
G
Q9
2
G
R57
330K_0402_5%
@
M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

1
+VCC_GFXCORE_AXG
C97
0.047U_0603_25V7K
R616
10_0402_1%
Q4
2N7002H_SOT23-3
R885 R02
1
2
15K_0402_1%
1
3
RUN_ON_CPU1.5VS3
D
R56
82K_0402_5%
AP4800
Id=9.6A
U3
DMN3030LSS-13_SOP8L-8
8
1
7
2
6
3
5
B+
DRAMRST_CNTRL_PCH
<35> SUSP
1
2
SENSE
LINES
1
B4
D1
C98
.1U_0402_16V7K
+V_DDR_REFA_R
+V_DDR_REFB_R
R78
1K_0402_1%
2
2
VREF
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
DDR3 -1.5V RAILS
+1.5V_CPU_VDDQ
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
1
1
C123
220U_6.3V_M
+VCCSA
SA RAIL
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
VCCSA_SENSE
MISC
VCCPLL1
VCCPLL2
VCCPLL3
C122
10U_0603_6.3V6M
B6
A6
A2
R67
1K_0402_1%
+V_SM_VREF should
have 20 mil trace width
+V_SM_VREF_CNT
C120
10U_0603_6.3V6M
C132
1U_0402_6.3V6K
C130
10U_0603_6.3V6M
C345
22U_0805_6.3V6M
+1.8VS_VCCPLL
AL1
VCCSA_VID[0]
VCCSA_VID[1]
VCCIO_SEL
M27 +VCCSA
M26
L26
J26
J25
J24
H26
H25
+ C128 @
330U_D2_2.5VY_R9M
H23
C22
C24
C126
10U_0603_6.3V6M
1.5A
0_0805_5%
2
R626
10_0402_1%
C125
10U_0603_6.3V6M
R69
1
+1.5V_CPU_VDDQ
VSS_AXG_SENSE <43>
C124
10U_0603_6.3V6M
+1.8VS
AK35
AK34
C119
10U_0603_6.3V6M
VAXG_SENSE
VSSAXG_SENSE
SM_VREF
GRAPHICS
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
C117
10U_0603_6.3V6M
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
VCC_AXG_SENSE <43>
POWER
1.8V RAIL
+VCC_GFXCORE_AXG JCPU1G
+VCCSA_SENSE <41>
H_VCCSA_VID0
H_VCCSA_VID1
<41>
<41>
A19
ME@
IVY Bridge drives VCCIO_SEL low

VCCP_PWRCTRL:0
Sandy Bridge is NC for A19
VCCP_PWRCTRL:1
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title
PROCESSOR(6/7) PWR
Custom
Rev
1.0
LA-9632P
Date:
Sheet

1
10
of
60
JCPU1H
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
JCPU1I
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
ME@
CompalME@
Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title

PROCESSOR(7/7) VSS
Custom
Rev
1.0
LA-9632P
Date:
Sheet
1
11
of
60
+VREF_DQ_DIMMA
<7> DDR_A_D[0..63]
DDR3 SO-DIMM A
<7> DDR_A_DQS[0..7]
JDIMM1
+VREF_DQ_DIMMA
C133
.1U_0402_16V7K
C134
2.2U_0603_6.3V4Z
DDR_A_D0
DDR_A_D1
DDR_A_DM0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
<7> DDR_CKE0_DIMMA
DDR_CKE0_DIMMA
<7> DDR_A_BS2
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
<7> M_CLK_DDR0
<7> M_CLK_DDR#0
M_CLK_DDR0
M_CLK_DDR#0
<7> DDR_A_BS0
DDR_A_MA10
DDR_A_BS0
<7> DDR_A_WE#
<7> DDR_A_CAS#
DDR_A_WE#
DDR_A_CAS#
<7> DDR_CS1_DIMMA#
DDR_A_MA13
DDR_CS1_DIMMA#
G1
G2
RP16
DDR_A_DM2
+VREF_CA
DDR_A_D22
DDR_A_D23
+VREF_CB
8
7
6
5
1K_0804_8P4R_1%
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_CKE1_DIMMA
DDR_CKE1_DIMMA
<7>
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
OSCAN (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>
Layout Note:
Place near DIMM
DDR_A_BS1 <7>
DDR_A_RAS# <7>
DDR_CS0_DIMMA#
M_ODT0
M_ODT1
DDR_CS0_DIMMA#
M_ODT0 <7>
(10uF_0603_6.3V)*8
(0.1uF_402_10V)*4
<7>
M_ODT1 <7>
+VREF_CA
+1.5V
+VREF_CA
DDR_A_D36
DDR_A_D37
DDR_A_DM4
2
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
1
+
C149 @
220U_6.3V_M
DDR_A_DQS#5
DDR_A_DQS5
VDDQ(1.5V) =
DDR_A_D46
DDR_A_D47
3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
DDR_A_D52
DDR_A_D53
Layout Note:
Place near DIMM
6*0603 10uf (PER CONNECTOR)
DDR_A_DM6
VTT(0.75V) =
DDR_A_D54
DDR_A_D55
3*0805 10uf
7/28 Update connect GND directly
4*0402 1uf
+0.75VS
VREF =
DDR_A_D60
DDR_A_D61
1*0402 0.1uf
DDR_A_DQS#7
DDR_A_DQS7
1*0402 0.1uf
DDR_A_D62
DDR_A_D63
SMB_DATA_S3
SMB_CLK_S3
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
1*0402 2.2uf
VDDSPD (3.3V)=
1*0402 2.2uf
Layout Note:
Place near DIMM
SMB_DATA_S3 <13,15,26>
SMB_CLK_S3 <13,15,26>
+0.75VS
1/76BA1/86W
206
LCN_DAN06-K4806-0103
ME@
Compal Secret Data
Issued Date
1
2
3
4
C148
.1U_0402_16V7K
205
+1.5V
DDR_A_D20
DDR_A_D21
C147
.1U_0402_16V7K
C156
.1U_0402_16V7K
C155
2.2U_0603_6.3V4Z
+3VS
1K_0804_8P4R_1%
C152
1U_0402_6.3V6K
DDR_A_D58
DDR_A_D59
<13,7>
DDR_A_D14
DDR_A_D15
C150
1U_0402_6.3V6K
DDR_A_DM7
+VREF_DQ_DIMMB
DDR3_DRAMRST#
1
2
3
4
C146
.1U_0402_16V7K
DDR_A_D56
DDR_A_D57
+VREF_DQ_DIMMA
DDR_A_DM1
DDR3_DRAMRST#
8
7
6
5
C145
.1U_0402_16V7K
DDR_A_D50
DDR_A_D51
RP15
DDR_A_D12
DDR_A_D13
C144
10U_0603_6.3V6M
DDR_A_DQS#6
DDR_A_DQS6
+1.5V
DDR_A_D6
DDR_A_D7
C143
10U_0603_6.3V6M
DDR_A_D48
DDR_A_D49
<7> DDR_A_MA[0..15]
DDR_A_DQS#0
DDR_A_DQS0
C142
10U_0603_6.3V6M
DDR_A_D42
DDR_A_D43
DDR_A_D4
DDR_A_D5
C141
10U_0603_6.3V6M
DDR_A_DM5
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
<7> DDR_A_DQS#[0..7]
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
C140
10U_0603_6.3V6M
DDR_A_D40
DDR_A_D41
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
C139
10U_0603_6.3V6M
DDR_A_D34
DDR_A_D35
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
C136
2.2U_0603_6.3V4Z
DDR_A_DQS#4
DDR_A_DQS4
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
C135
.1U_0402_16V7K
DDR_A_D32
DDR_A_D33
+1.5V
4BA2/6W
2011/06/15
Deciphered Date
2012/07/11
4
Title

DDRIII-SODIMM SLOT1

Custom
Date:
Rev
1.0
LA-9632P

1
Sheet
12
of
60
4BA2/6W
+VREF_DQ_DIMMB
+1.5V
<7> DDR_B_DQS[0..7]
JDIMM2
DDR_B_D0
DDR_B_D1
DDR_B_DM0
C157
.1U_0402_16V7K
1
C158
2.2U_0603_6.3V4Z
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
For Arranale only +VREF_DQ_DIMMB

supply from a external 1.5V voltage divide
circuit.
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
<7> DDR_CKE2_DIMMB
DDR_CKE2_DIMMB
<7> DDR_B_BS2
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
<7> M_CLK_DDR2
<7> M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#2
<7> DDR_B_BS0
DDR_B_MA10
DDR_B_BS0
<7> DDR_B_WE#
<7> DDR_B_CAS#
DDR_B_WE#
DDR_B_CAS#
<7> DDR_CS3_DIMMB#
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
M_ODT3
M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>
Layout Note:
Place near DIMM
DDR_B_BS1 <7>
DDR_B_RAS# <7>
DDR_CS2_DIMMB#
M_ODT2 <7>
(10uF_0603_6.3V)*8
(0.1uF_402_10V)*4
<7>
M_ODT3 <7>
+VREF_CB
+1.5V
+VREF_CB
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
1/76BA1/86W
VDDQ(1.5V) =
3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
Layout Note:
Place near DIMM
6*0603 10uf (PER CONNECTOR)

VTT(0.75V) =
3*0805 10uf
4*0402 1uf
+0.75VS
1*0402 0.1uf
VDDSPD (3.3V)=
1*0402 0.1uf
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
1*0402 2.2uf
1*0402 2.2uf
SMB_DATA_S3 <12,15,26>
SMB_CLK_S3 <12,15,26>
+0.75VS
Layout Note:
Place near DIMM
206
TYCO_2-2013287-1
ME@
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
5
DDR_B_D62
DDR_B_D63
SMB_DATA_S3
SMB_CLK_S3
C172
.1U_0402_16V7K
DDR_B_D36
DDR_B_D37
C171
.1U_0402_16V7K
G2
DDR_B_MA15
DDR_B_MA14
C170
.1U_0402_16V7K
G1
DDR_CKE3_DIMMB
C169
.1U_0402_16V7K
205
DDR_B_D30
DDR_B_D31
C168
2
10K_0402_5%
DDR_B_DQS#3
DDR_B_DQS3
10U_0603_6.3V6M
1
R97
DDR_B_D28
DDR_B_D29
C167
+3VS
DDR_B_D22
DDR_B_D23
10U_0603_6.3V6M
C178
.1U_0402_16V7K
+3VS
C177
2.2U_0603_6.3V4Z
<7>
DDR_B_DM2
C176
1U_0402_6.3V6K
DDR_B_D58
DDR_B_D59
DDR_CKE3_DIMMB
DDR_B_D20
DDR_B_D21
C174
1U_0402_6.3V6K
DDR_B_DM7
<12,7>
C166
DDR_B_D56
DDR_B_D57
DDR3_DRAMRST#
DDR_B_D14
DDR_B_D15
10U_0603_6.3V6M
DDR_B_D50
DDR_B_D51
DDR_B_DM1
DDR3_DRAMRST#
C165
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D12
DDR_B_D13
10U_0603_6.3V6M
DDR_B_D48
DDR_B_D49
DDR_B_D6
DDR_B_D7
10U_0603_6.3V6M
DDR_B_D42
DDR_B_D43
<7> DDR_B_MA[0..15]
DDR_B_DQS#0
DDR_B_DQS0
C164
DDR_B_DM5
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
<7> DDR_B_DQS#[0..7]
DDR_B_D4
DDR_B_D5
10U_0603_6.3V6M
DDR_B_D40
DDR_B_D41
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
C163
DDR_B_D34
DDR_B_D35
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
C160
2.2U_0603_6.3V4Z
DDR_B_DQS#4
DDR_B_DQS4
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
C159
.1U_0402_16V7K
DDR_B_D32
DDR_B_D33
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
<7> DDR_B_D[0..63]
+1.5V
+VREF_DQ_DIMMB
Title

DDRIII-SODIMM SLOT2
Size
Document Number
Rev
1.0
LA-9632P
Date:

1
Sheet
13
of
60
W=20mils
W=20mils
+RTCBATT
R99
1K_0402_5%
1
2
DK^
PCH_RTCX2
DK^
<DK^
Y1
1
C180
18P_0402_50V8J
CMOS
*
C
2 1K_0402_5%
HDA_SPKR
HIGH= Enable ( No Reboot )

LOW= Disable (Default)
<31> HDA_SPKR
+3V_PCH
<31> HDA_SDIN0
R106 2
@ 1 1K_0402_5%
D20
PCH_SRTCRST#
G22
SM_INTRUDER#
K22
PCH_INTVRMEN
C17
HDA_BIT_CLK
N34
HDA_SYNC
L34
HDA_SPKR
T10
HDA_RST#
K34
HDA_SDIN0
E34
G34
ME_FLASH
C34
Low = Disabled (Default)

High = Enabled [Flash Descriptor Security Overide]
1 1K_0402_5%
A36
ME_FLASH
<32> ME_FLASH
+3V_PCH
R108
A34
HDA_SYNC
This signal has a weak internal pull-down

On Die PLL VR is supplied by
1.5V when smapled high
1.8V when sampled low
Needs to be pulled High for Chief River platfrom
PCH_GPIO33
C36
PCH_GPIO13
N32
PCH_JTAG_TCK
J3
PCH_JTAG_TMS
H7
PCH_JTAG_TDI
K5
PCH_JTAG_TDO
H1
+5VS
RP12
3
HDA_SYNC_R
HDA_RST#
1
2
3
4
Q10
1
HDA_SYNC
SPI_CLK_PCH_R
<31> HDA_RST_AUDIO#
8
7
6
5
<31> HDA_SYNC_AUDIO
B
SPI_SB_CS0#
R878
1M_0402_5%
33_0804_8P4R_5%
FWH4 / LFRAME#
SRTCRST#
INTRUDER#
INTVRMEN
LDRQ0#
LDRQ1# / GPIO23
SERIRQ
HDA_BCLK
HDA_SYNC
SPKR
HDA_RST#
HDA_SDIN0
HDA_SDIN3
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
HDA_SDIN1
HDA_SDIN2
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
HDA_SDO
HDA_DOCK_EN# / GPIO33
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
HDA_DOCK_RST# / GPIO13
JTAG_TCK
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
JTAG_TMS
SATAICOMPO
JTAG_TDI
JTAG_TDO
SATAICOMPI
SATA3COMPI
T3
Y14
T1
ME_FLASH
<31> HDA_SDOUT_AUDIO
RTCRST#
SATA3RCOMPO
HDA_BIT_CLK
For EMI
<31> HDA_BITCLK_AUDIO
RTCX2
check with vender
SPI_SI
V4
SPI_SO_R
U3
Del Q10 check with codec

VDDIO using 3VALW
SPI_CLK
SATA3RBIAS
C38
A38
B37
C37
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
D36
LPC_FRAME#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
SPI_CS1#
SPI_MOSI
SPI_MISO
SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19
<32>
<32>
<32>
<32>
EC and Mini card debug port
LPC_FRAME# <32>
E36
K36
V5
SERIRQ
AM3
AM1
AP7
AP5
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P0
SERIRQ <32>
SATA_DTX_C_IRX_N0 <30>
SATA_DTX_C_IRX_P0 <30>
SATA_ITX_C_DRX_N0 <30>
SATA_ITX_C_DRX_P0 <30>
HDD
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
SATA_DTX_C_IRX_N2
SATA_DTX_C_IRX_P2
SATA_ITX_C_DRX_N2
SATA_ITX_C_DRX_P2
SATA_DTX_C_IRX_N2 <30>
SATA_DTX_C_IRX_P2 <30>
SATA_ITX_C_DRX_N2 <30>
SATA_ITX_C_DRX_P2 <30>
ODD
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
Y10
SATA_COMP
R111
37.4_0402_1%
1
2
SATA3_COMP
R113
49.9_0402_1%
1
2
AB12
AB13
AH1
RBIAS_SATA3
P3
SATALED#
V14
PCH_GPIO21
P1
BBS_BIT0_R
+V1.05S_VCCP
+V1.05S_VCCP
2
R115
750_0402_1%
SPI_CS0#
SPI
R105 1
PCH_RTCRST#
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LPC
1
2
+3VS
C20
SATA 6G
PCH_RTCX2
RTCX1
SATA
A20
RTC
C182
1U_0603_10V4Z
(INTVRMEN should always be pull high.)
<DZdZ
U4A
PCH_RTCX1
IHDA
INTVRMEN
H
Integrated VRM enable
L
Integrated VRM disable
CLRP3
SHORT PADS
C183
1U_0603_10V4Z
1
2
R103 20K_0402_5%
1
2
R100 20K_0402_5%
PCH_INTVRMEN
SM_INTRUDER#
2 330K_0402_5%
CLRP2
SHORT PADS
2 1M_0402_5%
+RTCVCC
R102 1
DZdZ
+RTCVCC
R101 1
^
C181
18P_0402_50V8J
JTAG
dWD
>ZW
32.768KHZ_12.5PF_CM31532768DZFT
C179
1U_0603_10V4Z
>ZW
@
R104
0_0402_5%
1
1
2
10M_0402_5%
R98
+RTCVCC
PCH_RTCX1
Share ROM
@
RP2
SPI_SO_R
SPI_SI
SPI_CLK_PCH_R
SPI_SB_CS0#
PANTHER-POINT_FCBGA989
HM76@
SA00005FH70
S IC BD82HM76 SLJ8E C1 BGA 989P PCH C38!
1
2
3
4
8
7
6
5
EC_SPI_SO
EC_SPI_SI
EC_SPI_CLK
EC_SPI_CS#
EC_SPI_SO <32>
EC_SPI_SI <32>
EC_SPI_CLK <32>
EC_SPI_CS# <32>
0_0804_8P4R_5%
SPI_CLK_PCH_R
U4
+3V_ROM
HM70@
Share ROM
R124
33_0402_5%
@
SA00005MQ80
IC BD82HM70 SJTNV C1 BGA 989P PCH C38!
DPDG1.1
C190
22P_0402_50V8J
@
For EMI
U4
R127 1
2 SPI_WP#
3.3K_0402_5%
R129 1
2 SPI_HOLD#
3.3K_0402_5%
NM70@
+3V_ROM
U5
SPI_SB_CS0#
1 R131
2 SPI_SO_L
SPI_SO_R
SPI_WP#
0_0402_5%
@
+3VS
For EMI
RP17
R124;c190 close to U4.T3 pin

A
SA00005WU60
S IC BD82NM70 SLJTA C1 BGA 989P PCH C38!
<19> PCH_GPIO16
BBS_BIT0_R
SATALED#
PCH_GPIO16
SERIRQ
8
7
6
5
1
2
3
4
CS#
SO
WP#
GND
VCC
HOLD#
SCLK
SI
8
7
6
5
SPI_HOLD#
SPI_CLK_1
1 R133
2 SPI_CLK_PCH_R
0_0402_5% SPI_SI
@
W25Q64FVSSIQ_SO8
For EMI
SA000039A30
S IC FL 64M W25Q64FVSSIQ SOIC 8P SPI ROM
1
2
3
4
10K_0804_8P4R_5%
Issued Date
Compal Secret Data
2011/06/15
2012/07/11
Deciphered Date
Title
PCH (1/9) SATA,HDA,SPI, LPC, XDP
Rev
1.0
LA-9632P
Date:
Sheet
Wednesday, March 06, 2013

1
14
of
60
U4B
BF36
BE36
AY34
BB34
BG37
BH37
AY36
BB36
BJ38
BG38
AU36
AV36
BG40
BJ40
AY40
BB40
BE38
BC38
AW38
AY38
LAN
C
R153 1
R154 1
<27> CLK_PCIE_LAN#
<27> CLK_PCIE_LAN
2 0_0402_5%
2 0_0402_5%
CLK_PCIE_LAN#_R
CLK_PCIE_LAN_R
For EMI
<27> CLKREQ_LAN#
+3V_PCH
WLAN
@
@
R152
R156 1
R165 1
<26> CLK_PCIE_WLAN1#
<26> CLK_PCIE_WLAN1
J2
1 10K_0402_5%
@
@
2 0_0402_5%
2 0_0402_5%
CLK_PCIE_WLAN1#_R AB49
CLK_PCIE_WLAN1_R AB47
For EMI
<26> CLKREQ_WLAN#
+3VS
R158 2
Y40
Y39
M1
1 10K_0402_5%
AA48
AA47
PCH_GPIO20
V10
Y37
Y36
PCH_GPIO25
A8
Y43
Y45
PCH_GPIO26
L12
V45
V46
PCH_GPIO44
L14
SML0ALERT# / GPIO60
SML0CLK
SML0DATA
A12
SML1ALERT# / PCHHOT# / GPIO74

SML1CLK / GPIO58
SML1DATA / GPIO75
DRAMRST_CNTRL_PCH
C8
PCH_SML0CLK
G12
PCH_SML0DATA
DRAMRST_CNTRL_PCH <10,7>
2 R139
1
1K_0402_5%
PERN8
PERP8
PETN8
PETP8
CL_CLK1
CL_RST1#
SMB_DATA_S3 <12,13,26>
+3V_PCH
Q61A
2N7002DW-T/R7_SOT363-6
6
1
EC_SMB_CK2
+3V_PCH
EC_SMB_CK2 <29,32>
C13
E14
SML1CLK
M16
SML1DATA
VGA
EC
Thermal Sensor
+3VS
EC_SMB_DA2
EC_SMB_DA2 <29,32>
2N7002DW-T/R7_SOT363-6
Q61B
M7
+3V_PCH
T11
P10
R143
10K_0402_5%
R544
2.2K_0402_5%
PCH_SML0CLK
CLKOUT_PCIE0N
CLKOUT_PCIE0P
CLKOUT_PCIE1N
CLKOUT_PCIE1P
SMB_DATA_S3
+3V_PCH
CL_DATA1
PEG_A_CLKRQ# / GPIO47
PCIECLKRQ0# / GPIO73
1 10K_0402_5%
2N7002DW-T/R7_SOT363-6
Q60B
PERN7
PERP7
PETN7
PETP7
DIMM1
DIMM2
Mini Card
+3VS
PCH_HOT# 2 R140
PERN4
PERP4
PETN4
PETP4
PERN6
PERP6
PETN6
PETP6
PCH_SMBDATA
SMB_CLK_S3 <12,13,26>
+3V_PCH
PERN3
PERP3
PETN3
PETP3
PERN5
PERP5
PETN5
PETP5
C9
1 10K_0402_5%
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
1 R145
2 10K_0402_5%
@
M10
SMBDATA
2 R134
BG36
BJ36
AV34
AU34
PERN2
PERP2
PETN2
PETP2
PCH_SMBCLK
R545
2.2K_0402_5%
BE34
BF34
BB32
AY32
PCH_GPI011
H14
PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2
E12
2 .1U_0402_16V7K
2 .1U_0402_16V7K
SMBCLK
1
1
SMBALERT# / GPIO11
C194
C195
PERN1
PERP1
PETN1
PETP1
BG34
BJ34
AV32
AU32
PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1
Link
2 .1U_0402_16V7K
2 .1U_0402_16V7K
SMBUS
1
1
Controller
<26> PCIE_PRX_DTX_N2
<26> PCIE_PRX_DTX_P2
<26> PCIE_PTX_C_DRX_N2
<26> PCIE_PTX_C_DRX_P2
C192
C193
CLOCKS
WLAN
PCI-E*
LAN
Q60A
2N7002DW-T/R7_SOT363-6
6
1 SMB_CLK_S3
PCH_SML0DATA
AB37
AB38
+3V_PCH
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKOUT_PCIE2N
CLKOUT_PCIE2P
CLKIN_DMI_N
CLKIN_DMI_P
CLKOUT_PCIE3N
CLKOUT_PCIE3P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKOUT_PCIE4N
CLKOUT_PCIE4P
AV22
AU22
CLK_CPU_DMI#
CLK_CPU_DMI
CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>
+3VS
RP23
8
7
6
5
SML1DATA
EC_SMB_DA2
SML1CLK
EC_SMB_CK2
AM12
AM13
BF18
BE18
CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI
R155 1
R157 1
2
2
10K_0402_5%
10K_0402_5%
BJ30
BG30
CLKIN_DMI2#
CLKIN_DMI2
R159 1
R160 1
2
2
10K_0402_5%
10K_0402_5%
G24
E24
CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M
R162 1
R163 1
2
2
10K_0402_5%
10K_0402_5%
AK7
AK5
CLK_BUF_PCIE_SATA# R164 1
CLK_BUF_PCIE_SATA R166 1
2
2
10K_0402_5%
10K_0402_5%
K45
CLK_BUF_ICH_14M
R167 1
10K_0402_5%
H45
CLK_PCI_LPBACK
V47
V49
XTAL25_IN
XTAL25_OUT
Y47
XCLK_RCOMP
1
2
3
4
2.2K_0804_8P4R_5%
+3V_PCH
+3VS
RP24
8
7
6
5
PCH_SMBCLK
SMB_CLK_S3
PCH_SMBDATA
SMB_DATA_S3
1
2
3
4
2.2K_0804_8P4R_5%
CLKIN_SATA_N
CLKIN_SATA_P
CLKOUT_PCIE5N
CLKOUT_PCIE5P
REFCLK14IN
CLKIN_PCILOOPBACK
CLK_PCI_LPBACK <18>
PCH_GPIO56
E6
V40
V42
PCH_GPIO45
T13
V38
V37
PCH_GPIO46
K12
AK14
PCIE_CLK_8N AK13
PCIE_CLK_8P
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
XTAL25_IN
XTAL25_OUT
PEG_B_CLKRQ# / GPIO56
XCLK_RCOMP
R171
90.9_0402_1%
1
2
+V1.05S_VCCP
CLKOUT_PCIE6N
CLKOUT_PCIE6P
XTAL25_IN
CLKOUT_PCIE7N
CLKOUT_PCIE7P
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
K43
1
2
R169 1M_0402_5%
F47
H47
XTAL25_OUT
27M_SSC
FLEX CLOCKS
AB42
AB40
CLKOUTFLEX0 / GPIO64
K49
PCH_GPIO67
PCH_GPIO67 <19>
BIOS Request SKU ID
C196
12P_0402_50V8J
OSC
NC
NC
OSC
4
1
Y2
1 25MHZ_10PF_7V25000014
C197
12P_0402_50V8J
HM76@
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title

PCH (2/9) PCIE, SMBUS, CLK
Rev
1.0
LA-9632P
Date:
Sheet

1
15
of
60
+RTCVCC
DSWODVREN
R179
R183
1 330K_0402_5%
@
1 330K_0402_5%
U4C
Y
B
SYS_PWROK
@
R180
10K_0402_5%
+3VS
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
<5>
<5>
<5>
<5>
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
<5>
<5>
<5>
<5>
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
<5>
<5>
<5>
<5>
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
BC24
BE20
BG18
BG20
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
BE24
BC20
BJ18
BJ20
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
AW24
AW20
BB18
AV18
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
AY24
AY20
AY18
AU18
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI
<5>
<5>
<5>
<5>
DMI
PCH_PWROK
<32,43> VGATE
@
U15
MC74VHC1G08DFT2G SC70 5P
FDI_INT
+V1.05S_VCCP
1
R177
1
R178
BJ24
2
DMI_IRCOMP
49.9_0402_1%
2
RBIAS_CPY
750_0402_1%
BG25
BH21
DMI_ZCOMP
FDI_FSYNC0
DMI_IRCOMP
FDI_FSYNC1
DMI2RBIAS
FDI_LSYNC0
4mil width and place

within 500mil of the PCH
<19> SYS_RST#
<32> SYS_PWROK
SYS_RST#
SYS_PWROK
DSWVRMEN
C12
K3
P12
L22
<32> PCH_PWROK
<6> PM_DRAM_PWRGD
PCH_PWROK
L10
PM_DRAM_PWRGD
B13
C21
<32> EC_RSMRST#
System Power Management
SUSACK# is only used on platform

that support the Deep Sx state.
FDI_LSYNC1
SUSACK#
SYS_RESET#
SYS_PWROK
PWROK
APWROK
DRAMPWROK
RSMRST#
+3V_PCH
SUSWARN#
2
R192 1 300_0402_5%
1 10K_0402_5%
WAKE#
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
SUSWARN#/SUSPWRDNACK/GPIO30
SLP_S3#
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
AW16
FDI_INT
AV12
FDI_FSYNC0
BC10
FDI_FSYNC1
AV14
FDI_LSYNC0
BB10
FDI_LSYNC1
A18
DSWODVREN
E22
EC_RSMRST#
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
FDI_INT <5>
FDI_FSYNC0
<5>
FDI_FSYNC1
<5>
FDI_LSYNC0 <5>
FDI_LSYNC1 <5>
B9
PCIE_WAKE# <26>
N3
PM_CLKRUN#
G8
SUS_STAT#
N14
R299 10K_0402_5%
1
SUSCLK <32>
D10
PM_SLP_S5# <32>
H4
PM_SLP_S4# <32>
F4
PM_SLP_S3# <32>
PM_DRAM_PWRGD
R194
K16
DPWROK
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
DSWODVREN - On Die DSW VR Enable

HEnable
LDisable
E20
<32> PBTN_OUT#
SUSWARN#
<32,36,38> ACIN
D29 1
AC_PRESENT_R
H20
PWRBTN#
SLP_A#
ACPRESENT / GPIO31
SLP_SUS#
BATLOW# / GPIO72
PMSYNCH
G10
Can be left NC when IAMT is not support on the platfrom
G16
CH751H-40PT_SOD323-2
R197
1 10K_0402_5%
EC_RSMRST#
PCH_GPIO72
RI#
E10
A10
RI#
SLP_LAN# / GPIO29
AP14
K14
H_PM_SYNC
H_PM_SYNC <6>
Can be left NC if no use integrated LAN.
HM76@
+3V_PCH
R309
2 200K_0402_5%
AC_PRESENT_R
+3V_PCH
RP25
A
8
7
6
5
1
2
3
4
PCIE_WAKE#
RI#
EC_SMI#
EC_SMI# <19,32>
10K_0804_8P4R_5%
Issued Date
Compal Secret Data
2011/06/15
2012/07/11
Deciphered Date
Title
PCH (3/9) DMI,FDI,PM,
Rev
1.0
LA-9632P
Date:
Sheet

1
16
of
60
ENBKL
J47
M45
<32> ENBKL
<23> PCH_ENVDD
100K_0402_1%
P45
<23> PCH_PWM
<23> EDID_CLK
<23> EDID_DATA
EDID_CLK
EDID_DATA
T40
K47
CTRL_CLK
CTRL_DATA
T45
P39
+3VS
2 R206
2.37K_0402_1%
RP14
1
2
3
4
EDID_DATA
EDID_CLK
CTRL_DATA
CTRL_CLK
2.2K_0804_8P4R_5%
LVDS_IBG
AF37
AF36
LVD_VREF
AE48
AE47
AK39
AK40
<23> LVDS_ACLK#
<23> LVDS_ACLK
<23> LVDS_A0#
<23> LVDS_A1#
<23> LVDS_A2#
AN48
AM47
AK47
AJ48
<23> LVDS_A0
<23> LVDS_A1
<23> LVDS_A2
AN47
AM49
AK49
AJ47
L_BKLTEN
L_VDD_EN
SDVO_TVCLKINN
SDVO_TVCLKINP
L_BKLTCTL
SDVO_STALLN
SDVO_STALLP
L_DDC_CLK
L_DDC_DATA
SDVO_INTN
SDVO_INTP
LVD_IBG
LVD_VBG
SDVO_CTRLCLK
SDVO_CTRLDATA
LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
RP20
1
2
3
4
AF40
AF39
DAC_BLU
DAC_GRN
DAC_RED
AH45
AH47
AF49
AF45
150_0804_8P4R_1%
Max = 800 mils
AH43
AH49
AF47
AF43
DAC_BLU
<24> DAC_BLU
<24> CRT_DDC_CLK
<24> CRT_DDC_DATA
CRT_DDC_CLK
CRT_DDC_DATA
R524
2.2K_0402_5%
CRT_IREF T43
T42
R211
1K_0402_1%
R559
2.2K_0402_5%
T39
M40
M47
M49
<24> CRT_HSYNC
<24> CRT_VSYNC
1
N48
P49
T49
DAC_RED
<24> DAC_RED
+3VS
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
DAC_GRN
<24> DAC_GRN
LVDSB_CLK#
LVDSB_CLK
AM42
AM40
AP39
AP40
CRT_DDC_CLK
CRT_DDC_DATA
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
P38 HDMICLK_NB
M39 HDMIDAT_NB
AT49
AT47
AT40
HDMICLK_NB <25>
HDMIDAT_NB <25>
TMDS_B_HPD# <25>
AV42 TMDS_B_DATA2#_PCHHDMI@
AV40 TMDS_B_DATA2_PCH HDMI@
AV45 TMDS_B_DATA1#_PCHHDMI@
AV46 TMDS_B_DATA1_PCH HDMI@
AU48 TMDS_B_DATA0#_PCHHDMI@
AU47 TMDS_B_DATA0_PCH HDMI@
AV47 TMDS_B_CLK#_PCH HDMI@
AV49 TMDS_B_CLK_PCH
HDMI@
P46
P42
C200
C201
C202
C203
C204
C205
C206
C207
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
HDMI_TX2-_CK <25>
HDMI_TX2+_CK <25>
HDMI_TX1-_CK <25>
HDMI_TX1+_CK <25>
HDMI_TX0-_CK <25>
HDMI_TX0+_CK <25>
HDMI_CLK-_CK <25>
HDMI_CLK+_CK <25>
HDMI D2
HDMI
HDMI D1
HDMI D0
HDMI CLK
CAP move on Conn, side
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
CRT_DDC_CLK
CRT_DDC_DATA
CRT_BLUE
CRT_GREEN
CRT_RED
CRT
8
7
6
5
AP43
AP45
L_CTRL_CLK
L_CTRL_DATA
Digital Display Interface
LVDS
8
7
6
5
U4D
R438
D
HM76@
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
Size
B
Date:
PCH (4/9) LVDS,CRT,DP,HDMI

Document Number
Rev
1.0
LA-9632P
Sheet
1
17
of
60
8.2K_1206_10P8R_5%
D
+3VS
RP7
8
7
6
5
1
2
3
4
DGPU_HOLD_RST#
PCH_WL_OFF#
PCH_GPIO5
PCH_GPIO52
8.2K_0804_8P4R_5%
Pull-up resistors are not required

on these signals
R292
2 8.2K_0402_5%
PCH_GPIO51
R557
2 8.2K_0402_5%
PCH_GPIO53
B21
M20
AY16
BG46
USB3_RX1_N BE28
USB3_RX2_N BC30
USB3_RX3_N BE32
USB3_RX4_N BJ32
USB3_RX1_P BC28
USB3_RX2_P BE30
USB3_RX3_P BF32
USB3_RX4_P BG32
USB3_TX1_N AV26
USB3_TX2_N BB26
USB3_TX3_N AU28
USB3_TX4_N AY30
USB3_TX1_P AU26
USB3_TX2_P AY26
USB3_TX3_P AV28
USB3_TX4_P AW30
<34> USB3_RX1_N
<34> USB3_RX2_N
C
Boot BIOS Strap bit1 BBS1

<34> USB3_RX1_P
<34> USB3_RX2_P
Boot BIOS
Bit11 Bit10 Destination
GNT1#/
GPIO51
Reserved
Reserved
SPI
<34> USB3_TX1_N
<34> USB3_TX2_N
<34> USB3_TX1_P
<34> USB3_TX2_P
(Default)
LPC
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
K40
K38
H38
G38
DGPU_HOLD_RST#
PCH_GPIO52
C46
C44
E40
PCH_GPIO51
PCH_GPIO53
PCH_WL_OFF#
D47
E42
F46
PCH_GPIO2
PCH_GPIO3
PCH_GPIO4
PCH_GPIO5
G42
G40
C42
D44
<32> DGPU_PWR_EN
B
<26> PCH_WL_OFF#
GPIO55
PCH_WL_OFF#
R215
U4E
BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
2 1K_0402_5%
PCI_PME#
A16 swap overide Strap/Top-Block

Swap Override jumper
PCH_PLTRST#
<6> PCH_PLTRST#
Low=A16 swap
override/Top-Block
PCI_GNT3# Swap Override enabled
High=Default
22_0402_5% 1
22_0402_5% 1
<15> CLK_PCI_LPBACK
<32> CLK_PCI_EC
2 R219
2 R220
For EMI
K10
C6
CLK_PCI_LPBACK_R H49
H43
CLK_PCI_EC_R
J48
CLK_PCI_DB_R
K42
H40
RSVD1
RSVD2
RSVD3
RSVD4
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
TP21
TP22
TP23
TP24
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
USB3Rn1
USB3Rn2
USB3Rn3
USB3Rn4
USB3Rp1
USB3Rp2
USB3Rp3
USB3Rp4
USB3Tn1
USB3Tn2
USB3Tn3
USB3Tn4
USB3Tp1
USB3Tp2
USB3Tp3
USB3Tp4
RSVD28
RSVD29
AY7
AV7
AU3
BG4
AT10
BC8
D
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AV10
AT8
AY5
BA2
AT12
BF3
USB Debug Port = Port1 and Port9
PIRQA#
PIRQB#
PIRQC#
PIRQD#
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
USB
PCH_GPIO2
DGPU_PWR_EN
PCH_GPIO4
PCH_GPIO3
RSVD
10
9
8
7
6
PCI
+3VS
+3VS
RP1
1
2
3
4
5
PCI_PIRQA#
PCI_PIRQD#
PCI_PIRQC#
PCI_PIRQB#
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
USBRBIAS#
USBRBIAS
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
C33
USBRBIAS
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N9 <34>
USB20_P9 <34>
USB20_N10 <26>
USB20_P10 <26>
USB20_N11 <33>
USB20_P11 <33>
PME#
Touch Screen
USB Camera
RIGHT USB
WLAN
B
CARD READER
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
A14
K20
B17
C16
L16
A16
D14
C14
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
USB_OC0# <34>
USB_OC4# <34>
For RIGHT USB2.0 Port
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
+3V_PCH
+3V_PCH
RP18
1
2
3
4
5
10
9
8
7
6
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
A
10K_1206_10P8R_5%
R222
1
2
0_0402_5%
PCH_PLTRST#
Compal Secret Data
Issued Date
R223
100K_0402_5%
2011/06/15
Deciphered Date
2012/07/11
Title
PCH (5/9) PCI, USB
(USB 3.0)
For LEFT USB3.0 Port
PLTRST#
HM76@
C208 @
1U_0402_6.3V6K
LEFT USB
1
R218 2
22.6_0402_1%
<26,27,32> PLT_RST#
LEFT USB
Within 500 mils
B33
<34>
<34>
<34>
<34>
<34>
<34>
<23>
<23>
Rev
1.0
LA-9632P
Date:
Sheet
1
18
of
60
HM70
HM76
HM76@
HM70@
R707
R707
10K_0402_5%
PCH_GPIO71
Mars@
R704
Function
2
HM76@
R705
HM70@
R703
10K_0402_5%
1
0
PCH_GPIO71
Mars XT
Sun Pro
Reserved
NM70@
R703
PCH_GPIO70
+3VS
R706
200K_0402_5%
Sun@
NM70@
R702
PCH_GPIO69
NM70
Function
10K_0402_5%
PCH_GPIO70
+3VS
10K_0402_5%
PCH_GPIO69
+3VS
10K_0402_5%
10K_0402_5%
10K_0402_5%
U4F
On-Die PLL Voltage Regulator

This signal has a weak internal pull up
PCH_GPIO6
H36
<32> EC_SCI#
EC_SCI#
E38
HOn-Die voltage regulator enable

LOn-Die PLL Voltage Regulator disable
R240
<16,32> EC_SMI#
2 1K_0402_5% PCH_GPIO28
+3V_PCH
EC_SMI#
C10
R230 2 1K_0402_5%
PCH_GPIO12
C4
EC_LID_OUT#
G2
PCH_GPIO16
U2
BMBUSY# / GPIO0
TACH4 / GPIO68
TACH1 / GPIO1
TACH5 / GPIO69
TACH2 / GPIO6
TACH6 / GPIO70
TACH3 / GPIO7
TACH7 / GPIO71
<14> PCH_GPIO16
GPIO15
A20GATE
R245
2 10K_0402_5%
<26> PCH_BT_ON#
PCH_GPIO27
<30> ODD_EN
+3V_PCH
PCH_BT_ON#
T5
ODD_EN
E8
PCH_GPIO27
E16
R241
GPIO36, 37
When Unused as GPIO or SATA*GP
+3VS
Use 8.2K-10K pull-down
to ground.
+3VS
2 10K_0402_5%
PCH_GPIO28
P8
1 R242
2 10K_0402_5%
INTEL_BT_OFF#
K1
PCH_GPIO35
K4
<26> INTEL_BT_OFF#
+3VS
R250 @
10K_0402_5%
R244 @
10K_0402_5%
PCH_GPIO36
PCH_GPIO37
R881
10K_0402_5%
R547 @
10K_0402_5%
SATA4GP / GPIO16
PCH_GPIO36
V8
PCH_GPIO37
M5
PCH_GPIO38
N2
PCH_GPIO39
M3
PCH_GPIO48
V13
PCH_GPIO49
V3
PCH_GPIO57
D6
TACH0 / GPIO17
SCLOCK / GPIO22
GPIO24
GPIO27
GPIO28
PROCPW RGD
THRMTRIP#
INIT3_3V#
DF_TVS
TS_VSS1
STP_PCI# / GPIO34
TS_VSS2
GPIO35
TS_VSS3
SATA2GP / GPIO36
TS_VSS4
SLOAD / GPIO38
NC_1
A45
A46
+3VS
BIOS Request SKU ID
A5
RP10
VSS_NCTF_15
SATA5GP / GPIO49 / TEMP_ALERT#
VSS_NCTF_16
GPIO57
VSS_NCTF_17
+3VS
8
7
6
5
1
2
3
4
A6
PCH_GPIO39
SYS_RST#
PCH_BT_ON#
PCH_GPIO35
SYS_RST# <16>
B3
1
2
R246
UMA@
10K_0402_5%
R711
UMA@
10K_0402_5%
B47
10K_0804_8P4R_5%
BD1
BD49
BE1
BE49
PCH_GPIO38
BF1
PCH_GPIO67 <15>
BF49
10K_0402_5%
R298
PX@
R708
PX@
10K_0402_5%
PCH_GPIO67
VSS_NCTF_1
VSS_NCTF_19
VSS_NCTF_2
VSS_NCTF_20
VSS_NCTF_3
VSS_NCTF_21
VSS_NCTF_4
VSS_NCTF_5
+3VS
GATEA20 <32>
AU16
P5
KBRST#
AY10
KBRST#
KBRST# <32>
AY11
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_6
VSS_NCTF_24
VSS_NCTF_7
VSS_NCTF_25
VSS_NCTF_8
VSS_NCTF_26
VSS_NCTF_9
VSS_NCTF_27
VSS_NCTF_10
VSS_NCTF_28
VSS_NCTF_11
VSS_NCTF_29
VSS_NCTF_12
VSS_NCTF_30
VSS_NCTF_13
VSS_NCTF_31
VSS_NCTF_14
VSS_NCTF_32
R226
2 10K_0402_5%
H_CPUPWRGD <6>
PCH_THRMTRIP#_R 1
R239
2
H_THRMTRIP#
390_0402_5%
H_THRMTRIP# <6>
T14
AY1
INIT3_3V
AH8
This signal has weak internal PU,can't pull low

+1.8VS
AK11
AH10
DMI Termination Voltage
AK10
Set to Vcc when HIGH

NV_CLE
Set to Vss when LOW
P37
1
R217
SDATAOUT1 / GPIO48
NCTF
A44
P4
SDATAOUT0 / GPIO39
VSS_NCTF_18
+3VS
NV_CLE
A4
PCH_GPIO71
SATA3GP / GPIO37
PECI
CPU/MISC
D40
PCH_GPIO70
A40
R236
10K_0402_5%
GPIO
DGPU_PWROK
PCH_GPIO69
C41
LAN_PHY_PW R_CTRL / GPIO12
RCIN#
PCH_GPIO27 (Have internal Pull-High)

High: VCCVRM VR Enable
Low: VCCVRM VR Disable
PCH_GPIO68
B41
GPIO8
<32> EC_LID_OUT#
C40
A42
BG2
Weak internal
PU,Do not pull low
BG48
R216
2.2K_0402_5%
PCH_GPIO1
GPIO28
T7
PCH_GPIO0
H_SNB_IVB# <6>
1K_0402_5%
CLOSE TO THE BRANCHING POINT
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
PCH_GPIO38
PCH_GPIO67
Function
HM76@
SG(Optimus / PX)
Reserved
DIS
UMA
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title
PCH (6/9) GPIO, CPU, MISC
Size
Document Number
Custom
Rev
1.0
LA-9632P
Date:
Sheet
19
of
60
+V1.05S_VCCP
+V1.05S_VCCP
CRT
VSSALVDS
AN17
AN21
AN26
AN27
AP21
Near AN16
AP23
1
C225
1U_0402_6.3V6K
C224
1U_0402_6.3V6K
C223
1U_0402_6.3V6K
C222
1U_0402_6.3V6K
C221
10U_0603_6.3V6M
AP24
AP26
AT24
AN33
AN34
+3VS
BH29
1
C227
.1U_0402_16V7K
AP16
+1.05VS_VCCAPLL_FDI
BG6
+V1.05S_VCCP
AP17
+V1.05S_VCCP
AU20
1
C214
.1U_0402_16V7K
1
C215
10U_0603_6.3V6M
C395@
10U_0603_6.3V6M
Voltage Rail
V_PROC_IO
VCCTX_LVDS[1]
VCCTX_LVDS[2]
V5REF
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCC3_3[6]
AM38
AP36
AP37
V5REF_Sus
+1.8VS
L2
0.1UH_MLF1608DR10KT_10%_1608
2
1
+VCCTX_LVDS
1
C216
0.01U_0402_16V7K
S0 Iccmax
Current (A)
1.05
0.001
0.001
0.001
3.3
0.228
VccADAC
3.3
0.001
VccADPLLA
1.05
0.075
VccADPLLB
1.05
0.075
VccCore
1.05
1.3
VccDMI
1.05
0.042
VccIO
1.05
3.709
VccASW
1.05
0.903
VccSPI
3.3
0.01
VccDSW
3.3
0.001
VccDFTERM
1.8
0.002
VccRTC
3.3
6 uA
3.3
0.065
0.1uH inductor, 200mA
1
C217
0.01U_0402_16V7K
Vcc3_3
C218
22U_0805_6.3V6M
+3VS
V33
1
VCC3_3[7]
V34
2
C219
.1U_0402_16V7K
+1.5VS
VCCIO[18]
VCCIO[19]
Voltage
AK37
AM37
Near V33
3711mA
VCCVRM[3]
AT16
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]
+V1.05S_VCCP
Near AT20
VCCIO[20]
VCCDMI[1]
+V1.05S_VCCP
Near AB36
20mA VCCCLKDMI
AT20
AB36
1
C226
1U_0402_6.3V6K
C220
1U_0402_6.3V6K
VCCIO[25]
VCCIO[26]
VCCDFTERM[1]
190mAVCCDFTERM[2]
VCC3_3[3]
+1.5VS
1
C213
0.01U_0402_16V7K
AK36
VCCAPLLEXP
VCCVRM[2]
VccAFDIPLL
VCCIO[27]
VCCDMI[2]
FDI
+V1.05S_VCCP
C
1
U47
PCH Power Rail Table

Refer to CPU EDS R1.5
VCCIO[28]
HVCMOS
AN16
+VCCADAC
1mA VCCALVDS
DMI
BJ22
U48
1_0603_1%
1
+3VS
DFT / SPI
This pin can be left as no connect in

On-Die VR enabled mode (default).
This pin can be left as no connect in

On-Die VR enabled mode (default).
VSSADAC
VCCTX_LVDS[4]
VCCIO
+VCCAPLLEXP
VCCADAC
60mA VCCTX_LVDS[3]
AN19
1mA
LVDS
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]
VCC CORE
C212
1U_0402_6.3V6K
C211
1U_0402_6.3V6K
C210
1U_0402_6.3V6K
C209
10U_0603_6.3V6M
+3VS
L1
2
1300mA
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
L1 Change to 1 ohm P/N

S RES 1/10W 1 +-1% 0603
POWER
U4G
Near AA23
VCCDFTERM[3]
VCCDFTERM[4]
AG16
VccSus3_3
VccSusHDA
3.3 / 1.5
0.01
VccVRM
1.8 / 1.5
0.167
Near AG16
+3V_ROM
AJ16
1
AJ17
C228
.1U_0402_16V7K
VccCLKDMI
1.05
0.075
VccSSC
1.05
0.095
20mA VCCSPI
V1
Near V1
VccDIFFCLKN
1.05
0.055
VccALVDS
3.3
0.001
VccTX_LVDS
1.8
0.04
HM76@
Share ROM
+1.8VS
AG17
C230
1U_0402_6.3V6K
Share ROM
+3VALW
+3VS
+3V_ROM
@
1 R413
2
0_0402_5%
@
Q21
AO3413_SOT23
@
R419
+5VALW
Q22
2
G
2N7002H_SOT23-3
@
@
R40
1
2
0_0402_5%
C237
.1U_0402_16V7K
Compal Secret Data
Issued Date
0_0402_5%
PCH_PWR_EN_R
1
C252
.1U_0402_16V7K
<32> PCH_PWR_EN
@
R418
100K_0402_5%
C243
.1U_0402_16V7K
2011/06/15
2012/07/11
Deciphered Date
Title
PCH (7/9) PWR
Rev
1.0
LA-9632P
Date:
Sheet

1
20
of
60
Have internal VRM

+3VS
+V1.05S_VCCP
R268 @
0_0603_5%
2
1
+VCCACLK
+3VALW
Near T38
V12
+PCH_VCCDSW
C235 @
.1U_0402_16V7K
T38
+3VS
DCPSUSBYP
VCCIO[32]
VCCIO[33]
AL24
+VCCSUS1
1
AA19
AA21
AA24
C242
22U_0805_6.3V6M
C241
22U_0805_6.3V6M
AA26
AA27
AA29
AA31
AC26
C246
1U_0402_6.3V6K
C245
1U_0402_6.3V6K
+V1.05S_VCCP
C244
1U_0402_6.3V6K
AC27
AC29
AC31
AD29
AD31
W21
W23
L6
1
2
10UH_LB2012T100MR_20%
1
+1.05VS_VCCA_A_DPL
W24
C253
1U_0402_6.3V6K
C187
22U_0805_6.3V6M
C250
220U_6.3V_M
C251
1U_0402_6.3V6K
VCCSUS3_3[8]
VCCIO[14]
DCPSUS[3]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[6]
@ C239
1U_0402_6.3V6K
Near AA19
1
VCCAPLLDMI2
W26
W29
W31
W33
VCCASW[1]
VCCIO[34]
1010mA
VCCASW[2]
1mA V5REF_SUS
VCCASW[3]
Clock and Miscellaneous
2
+V1.05S_VCCP
119mA VCCSUS3_3[7]
USB
AL29
+V1.05S_VCCP
VCCASW[4]
VCCASW[5]
VCCASW[6]
VCCASW[7]
VCCASW[8]
VCCASW[9]
VCCASW[10]
VCCASW[11]
VCCASW[12]
VCCASW[13]
VCCASW[14]
VCCASW[15]
DCPSUS[4]
VCCSUS3_3[1]
1mA V5REF
VCCASW[16]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCC3_3[1]
VCC3_3[8]
VCC3_3[4]
+1.5VS
C258
.1U_0402_16V7K
T29
+3V_PCH
T23
T24
V23
2
V24
P24
+3V_PCH
C238
.1U_0402_16V7K
+V1.05S_VCCP
T26
M26
+PCH_V5REF_SUS
AN23
+VCCA_USBSUS
AN24
P34
+3V_PCH
+3V_PCH
+PCH_V5REF_RUN
N20
N22
2
P20
1
AA16
VCCASW[20]
DCPRTC
VCCVRM[4]
VCCIO[13]
+3VS
+5VALW
C249
.1U_0402_16V7K
T34
BF47
C256
1U_0402_6.3V6K
AF17
AF33
AF34
AG34
Near AF33
+V1.05S_VCCP
1
AG33
C259
1U_0402_6.3V6K
C254
.1U_0402_16V7K
VCCIO[4]
95mA
+V1.05S_VCCP
1
AF13
C255
2 .1U_0402_16V7K
+5VS
AH13
2
AH14
C257
1U_0402_6.3V6K
R279
10_0402_5%
AF14
AK1
+3VS
D2
+VCCSATAPLL
+PCH_V5REF_RUN
1
+1.5VS
AF11
+V1.05S_VCCP
AC16
AC17
AD17
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA
C248
1U_0603_10V6K
C261
1U_0402_6.3V6K
2
+VCCSST
V16
+1.05VM_VCCSUS
T17
V19
C263
.1U_0402_16V7K
+V1.05S_VCCP
DCPSST
DCPSUS[1]
DCPSUS[2]
VCCASW[22]
+V1.05S_VCCP
BJ8
Near BJ8
1
+RTCVCC
C266
.1U_0402_16V7K
A22
C269
.1U_0402_16V7K
C268
1U_0402_6.3V6K
C265
4.7U_0603_6.3V6K
V_PROC_IO 1mA
VCCRTC
MISC
C262
1U_0402_6.3V6K
VCCSSC
C240
0.1U_0603_25V7K
AJ2
HOn-Die PLL voltage regulator enable

VCCVRM[1]
VCCIO[2]
VCCASW[23]
VCCASW[21]
T21
V21
T19
+3V_PCH
HDA
Near AG33
1
80mA
VCCIO[7]
VCCDIFFCLKN[1]
55mA
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]
VCCAPLLSATA
VCCIO[3]
+V1.05S_VCCP
VCCADPLLB
80mA
CPU
VCCIO[6]
VCCADPLLA
+PCH_V5REF_SUS
1
BD47
+1.05VS_VCCA_A_DPL
RTC
+1.05VS_VCCA_A_DPL
SATA
Near AF17
+V1.05S_VCCP
D1
+3VS
2
B
+3V_PCH
R275
10_0402_5%
W16
2
VCC3_3[2]
C247
1U_0402_6.3V6K
P22
+3VS
VCCASW[19]
VCCIO[12]
Y49
VCCASW[18]
VCCIO[5]
N16
C233
1U_0402_6.3V6K
VCCASW[17]
@
+VCCRTCEXT
T27
C236
.1U_0402_16V7K
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA
BH23
P28
VCC3_3[5]
HOn-Die PLL voltage regulator enable

+VCCAPLL_CPY_PCH
P26
VCCIO[30]
3mA
VCCDSW3_3
VCCIO[31]
2
JUMP_43X118
N26
T16
VCCIO[29]
C234
.1U_0402_16V7K
VCCACLK
POWER
U4J
AD49
+V1.05S_VCCP
PCI/GPIO/LPC
Near T16
C232
1U_0402_6.3V6K
C231
10U_0603_6.3V6M
+3V_PCH
PJ1
2
+3V_PCH
10mA VCCSUSHDA
P32
1
HM76@
C271
.1U_0402_16V7K
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
5
Title

PCH (8/9) PWR

Custom
Rev
1.0
LA-9632P
Date:

1
Sheet
21
of
60
U4I
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
U4H
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
HM76@
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
HM76@
Issued Date
Compal Secret Data
2011/06/15
2012/07/11
Deciphered Date
Title
PCH (9/9) VSS
Rev
1.0
LA-9632P
Date:
Sheet

1
22
of
60
LCD POWER CIRCUIT
Camera
+3VS
W=60mils
+LCDVDD_CONN
W=60mils
U72
VIN
SS
EN
APL3512ABI-TRG_SOT23-5
R435CMOS@
150K_0402_5%
2
<17> PCH_ENVDD
(20 MIL)
1
C4
1500P_0402_50V7K
GND
+3VS_CMOS
CMOS@
Q83
LP2301ALT1G_SOT23-3
(20 MIL)
VOUT
+LCDVDD_CONN
4.7U_0603_6.3V6K
C516
+3VS
CMOS@
C518
.1U_0402_16V7K
1
R02
2
C519 @
10U_0603_6.3V6M
4.7V
<32> CMOS_ON#
1
R408
100K_0402_5%
C520 CMOS@
.1U_0402_16V7K
LCD Conn.
+LEDVDD
B+
@
R813
1
0_0805_5%
C541
4.7U_0805_25V6-K
@
JLVDS1
R509 1
2 0_0402_5%
BKOFF#
<17> PCH_PWM
<17> LVDS_ACLK
<17> LVDS_ACLK#
<17> LVDS_A2
<17> LVDS_A2#
<17> LVDS_A1
<17> LVDS_A1#
<17> LVDS_A0
<17> LVDS_A0#
<17> EDID_DATA
<17> EDID_CLK
<32> BKOFF#
BKOFF#
R716
10K_0402_5%
2
+3VS
+LCDVDD_CONN
(60 MIL)
+3VS
+3VS_CMOS
CMOS
For EMI
<18> USB20_P3
<18> USB20_N3
1 R688@
1 R684@
USB20_P3
USB20_N3
2 0_0402_5%
2 0_0402_5%
USB20_P3_R
USB20_N3_R
USB20_P3_R
USB20_N3_R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
G1
G2
G3
G4
31
32
33
34
ACES_88341-3001 ME@
L58 @
USB20_P3
USB20_N3
USB20_P3_R
USB20_N3_R
WCM-2012-900T_4P
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title

LVDS/CAMERA
Custom
Date:
Rev
1.0
LA-9632P
Sheet
1
23
of
60
DAC_BLU
DAC_GRN
DAC_RED
GREEN
BLUE
1
10P_0402_50V8J
C527
1
2
3
4
RED
10P_0402_50V8J
C526
RP22
8
7
6
5
10P_0402_50V8J
C524
10P_0402_50V8J
C522
<17> DAC_BLU
10P_0402_50V8J
C523
<17> DAC_GRN
10P_0402_50V8J
C525
FCM1608CF-121T03 0603
1
2
L30
FCM1608CF-121T03 0603
1
2
L31
FCM1608CF-121T03 0603
1
2
L32
<17> DAC_RED
+5V_Display
150_0804_8P4R_1%
JCRT1
PAD
For EMI
T66
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
NC11
RED
CRT_DDC_DAT_CONN
GREEN
JVGA_HS_R
BLUE
JVGA_VS_R
CRT_DDC_CLK_CONN
@
C531
.1U_0402_16V7K
U10
10
VIDEO1
VCC_DDC
VIDEO2
DDC_IN1
VIDEO3
DDC_IN2
DDC_OUT1
1
C6
2
0.22U_0402_10V6K
+5V_Display
RED
GREEN
BLUE
CRT_DDC_DAT_CONN
12
CRT_DDC_CLK_CONN
14
2
JVGA_VS 1 R411
22_0402_5%
JVGA_VS_R
16
2
JVGA_HS 1 R412
22_0402_5%
JVGA_HS_R
R31
4.7K_0402_5%
R33
4.7K_0402_5%
C537
.1U_0402_16V7K
<17> CRT_DDC_DATA
VCC_VIDEO
2
<17> CRT_DDC_CLK
<17> CRT_VSYNC
<17> CRT_HSYNC
11
13
15
6
SYNC_IN1
DDC_OUT2
SYNC_IN2
SYNC_OUT1
GND
SYNC_OUT2
TPD7S019-15DBQR_SSOP16
@
C411
10P_0402_50V8J
7
1
BYP
VCC_SYNC
C412
10P_0402_50V8J
+3VS
16
17
CONTE_80431-5K1-152
ME@
+5VS
C529
.1U_0402_16V7K
G
G
2011/06/15
Issued Date
Compal Secret Data
2012/07/11
Deciphered Date
Title
CRT Connector
Custom
Date:
Rev
1.0
LA-9632P
Sheet

E
24
of
60
For EMI
+5V_Display
U73
+5VS
HDMI@
+3VS
3
L36
HDMI_CLK-_CONN
<17> HDMI_TX0-_CK
HDMI_TX0-_CK
HDMI@
HDMI_TX0+_CONN
HDMI_TX0-_CONN
.1U_0402_16V7K
R485
1M_0402_5%
HDMI@
2
.1U_0402_16V7K
2
D
AP2330W-7_SC59-3
Q93
HDMI@
2N7002H_SOT23-3
TMDS_B_HPD#
<17> TMDS_B_HPD#
1
C543
GND
2
IN
C544
<17> HDMI_TX0+_CK
HDMI_TX0+_CK
1
1
WCM-2012HS-900T
OUT
HDMI_CLK+_CONN
HDMI_CLK-_CK
<17> HDMI_CLK-_CK
L35
HDMI_CLK+_CK
<17> HDMI_CLK+_CK
W=40mils
ZZZ3
45@
For CRT and HDMI
HDMI_TX1+_CK
<17> HDMI_TX1-_CK
HDMI_TX1-_CK
HDMI@
HDMI_TX1+_CONN
HDMI_TX1-_CONN
HDMI Logo
R488
20K_0402_5%
HDMI@
RO0000003HM
JHDMI1
L37
<17> HDMI_TX1+_CK
WCM-2012HS-900T
L38
<17> HDMI_TX2+_CK
HDMI_TX2+_CK
<17> HDMI_TX2-_CK
HDMI_TX2-_CK
+5V_Display
HDMIDAT_R
HDMICLK_R
HDMI@
HDMI_TX2+_CONN
HDMI_TX2-_CONN
HDMI_CLK-_CONN
HDMI_CLK+_CONN
HDMI_TX0-_CONN
WCM-2012HS-900T
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HDMI_DET
WCM-2012HS-900T
HDMI_TX0+_CONN
HDMI_TX1-_CONN
+3VS
HDMI_TX1+_CONN
HDMI_TX2-_CONN
Pull up R for PCH OR VGA SIDE
HDMI_TX2+_CONN
20
21
22
23
SUYIN_100042GR019M23DZL
ME@
2
+3VS
+5V_Display
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKG1
CK_shield
G2
CK+
G3
D0G4
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
RP21
1
2
3
4
HDMIDAT_NB
HDMIDAT_R
HDMICLK_NB
HDMICLK_R
DVT
RP26
<17> HDMICLK_NB
HDMICLK_R
HDMI_TX1+_CONN
HDMI_TX1-_CONN
HDMI_CLK+_CONN
HDMI_CLK-_CONN
8
7
6
5
Q63A
HDMI@
2N7002DW-T/R7_SOT363-6
2.2K_0804_8P4R_5%
HDMI@
<17> HDMIDAT_NB
5
6
7
8
HDMIDAT_R
680 +-5% 8P4R
HDMI@
Q63B
HDMI@
2N7002DW-T/R7_SOT363-6
RP27
HDMI_TX0+_CONN
HDMI_TX0-_CONN
HDMI_TX2+_CONN
HDMI_TX2-_CONN
5
6
7
8
ESD
HDMIDAT_R
9
HDMIDAT_R
HDMI_CLK-_CONN
9
D28

HDMI_CLK-_CONN
HDMI_TX0+_CONN 9
D33

HDMI_TX0+_CONN
HDMICLK_R
8
HDMICLK_R
HDMI_CLK+_CONN
8
HDMI_CLK+_CONN
HDMI_TX0-_CONN 8
HDMI_TX0-_CONN
HDMI_DET
7
HDMI_DET
HDMI_TX1-_CONN
7
HDMI_TX1-_CONN
HDMI_TX2+_CONN 7
HDMI_TX2+_CONN
HDMI_TX1+_CONN
6
HDMI_TX1+_CONN
HDMI_TX2-_CONN 6
HDMI_TX2-_CONN
YSCLAMP0524P_SLP2510P8-10-9
+3VS
1
2
G
Q95
HDMI@
2N7002H_SOT23-3
6
4
3
2
1
680 +-5% 8P4R
HDMI@
D32

4
3
2
1
Issued Date
Compal Secret Data
2011/06/15
Deciphered Date
2012/07/11
Title
Size
B
HDMI CONN
Document Number
Rev
1.0
LA-9632P
Date: Wednesday, February 27, 2013
Sheet
1
25
of
60
Mini Card for WLAN/WiMAX(Half)

1
+3VS
+3VS_WLAN
80mil
J6
1
2
+1.5VS
JUMP_43X79
@
<16> PCIE_WAKE#
JWLN1
R508 1
2 0_0402_5%
PCIE_WAKE#_WLAN
<19> PCH_BT_ON#
<15> CLKREQ_WLAN#
<15> CLK_PCIE_WLAN1#
<15> CLK_PCIE_WLAN1
+3VS_WLAN
1 R405
2
1K_0402_5%
For EC to detect
debug card insert.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
PCH_WL_OFF# <18>
PLT_RST# <18,27,32>
+3VS_WLAN
1 R501
1 R502
2 @ 0_0402_5%
2 @ 0_0402_5%
SMB_CLK_S3 <12,13,15>
SMB_DATA_S3 <12,13,15>
USB20_N10 <18>
USB20_P10 <18>
54
BELLW_80003-8041
ME@
R507
100K_0402_5%
3
53
DVT
<19> INTEL_BT_OFF#
100_0402_1%
R505
2
2
R506
100_0402_1%
INTEL_BT_OFF#_R
1
1
<32,33> EC_TX
<32,33> EC_RX
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
Size
Date:

Mini-Card/NEW Card/SIM
Document Number
Rev
1.0
LA-9632P
Sheet
E
26
of
60
For LAN & Green CLK
+3V_LAN
+3VALW
+LX
Close together
J10
LL2
LAN_PWR_ON#
1
2
10K_0402_5%
CL6
CL5
CL4
Note: Place Close to LAN chip

LL1 DCR< 0.15 ohm
Rate current > 1A
SWR@
4.7U_0603_6.3V6K
<32> LAN_PWR_ON#
RL3
@
QL1
LP2301ALT1G_SOT23-3
LL3
FBMA-L11160808601LMA10T_2P
FBMA-L11160808601LMA10T_2P
1
2
1
2
+1.1_AVDDL
+LX_R
+1.1_AVDDL_L
1U_0402_6.3V6K
10U_0603_6.3V6M
CL3
CL2
JUMP_43X79
LL1 SWR@
1
2 +LX
4.7UH_SIA4012-4R7M_20%
+LX_R
.1U_0402_16V7K
.1U_0402_16V7K
CL1
1000P_0402_50V7K
10U
@
CL7
.1U_0402_16V7K
SWR@SWR@SWR@
Place close to Pin34

Close to
Pin40
Vendor recommand reseve the

PU resistor close LAN chip
RL4
+3V_LAN
2 4.7K_0402_5%
UL1
+3V_LAN
8172@
+3V_LAN
PCIE_WAKE#_R
2 0_0402_5%
RL9
25
26
2 4.7K_0402_5%
@
28
27
Vendor recommand reseve the

PU resistor close LAN chip
7
8
LAN_XTALO
LAN_XTALI
+3V_LAN
RL11 1
2 4.7K_0402_5%
REFCLK_N
REFCLK_P
PERST#
SMCLK
SMDATA
RBIAS
NC
TESTMODE
VDD33
LX
XTLO
XTLI
Near
Pin6
41
CLKREQ#
DVDDL/PPS
DVDDL_REG/DVDDL
AVDDL
AVDDL
AVDDL
AVDDL
AVDDL_REG/AVDDL
Near
Pin19
+3V_LAN
40
+LX
+3V_LAN
RL8
2.37K_0402_1%
Place Close to PIN1
+LX
+1.7_VDDCT
24
37
+LX_R
30K_0402_5%
+3V_LAN
AVDDH/AVDD33
AVDDH
AVDDH_REG
16
22
9
don't @ (could be B C cost done)
+2.7_AVDDH
+3V_LAN
+2.7_AVDDH
+2.7_AVDDH
GND
AR8162-BL3A-R_QFN40_5X5
8162@
SA000052J20
S IC AR8162-BL3A-R QFN 40P E-LAN CTRL
Near
Pin13
<28>
<28>
<28>
<28>
Place Close to PIN1
CL22
.1U_0402_16V7K
CL20
CL19
1U_0402_6.3V6K
CL21
.1U_0402_16V7K
CL18
.1U_0402_16V7K
CL17
.1U_0402_16V7K
13
19
31
34
6
LAN_RBIAS
RL10
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL_L
+1.1_AVDDL
10
MDI0MDI0+
MDI1MDI1+
W AKE#
VDDCT/ISOLAN
<15> CLKREQ_LAN#
MDI0MDI0+
MDI1MDI1+
CL16
10U_0603_6.3V6M
RL7
<32> LAN_WAKE#
PLT_RST#
RX_P
Place close to Pin16

12
11
15
14
18
17
21
20
CL15
10U_0603_6.3V6M
<15> CLK_PCIE_LAN#
<15> CLK_PCIE_LAN
TRXN0
TRXP0
TRXN1
TRXP1
TRXN2
TRXP2
TRXN3
TRXP3
CL14
1U_0402_6.3V6K
32
33
AR8151/AR8161
RX_N
CL13
.1U_0402_16V7K
TX_P
RL12 if use LDO modue
CL12
1000P_0402_50V7K
1
2
35
RL12
10K_0402_5%
2 LDO@ 1
mount
1U_0402_6.3V6K
36
38
39
23
CL25
PCIE_PRX_C_DTX_P1 30
LED_0
LED_1
LED_2
Atheros
.1U_0402_16V7K
CL26
2 .1U_0402_16V7K
TX_N
.1U_0402_16V7K
CL11 1
PCIE_PRX_C_DTX_N1 29
CL24
2 .1U_0402_16V7K
1U_0402_6.3V6K
CL9
.1U_0402_16V7K
CL23
CL10
UL1
Place Close to Chip
CL8
QCA8172-BL3A-R
SA000065410
S IC QCA8172-BL3A-R QFN 40P E-LAN CTRL
1U_0402_6.3V6K
<18,26,32> PLT_RST#
.1U_0402_16V7K
PLT_RST#
Near
Pin9
Near
Pin31
Near
Pin22
@
Near
Pin37
LAN_XTALI
LAN_XTALO
YL1
4
1
CL28
15P_0402_50V8J
Lenovo
NC
OSC
OSC
NC
3
2
1 25MHZ_10PF_7V25000014
CL29
15P_0402_50V8J
Issued Date
Compal Secret Data
2011/06/15
2012/07/11
Deciphered Date
Title
LAN-AR8162/8172
Size
Document Number
Custom
Date:
Rev
1.0
LA-9632P
Sheet
1
27
of
60
ESD
Place Close to TL1
@
DL1
AZC099-04S.R7G_SOT23-6
1
4
I/O1
I/O3
MDI1+
Reserve gas tube for EMI go rural solution

MDI0+
DL1
1'S PN:SC300001G00
2'S PN:SC300002E00
GND
MDI0-
I/O2
VDD
For EMI
I/O4
MDI1RL14
1
CL30
1
2
CHASSIS1_GND
75_0805_5%
10P_0603_50V
TL1
<27> MDI0+
<27> MDI0-
For EMI
2
<27> MDI1+
<27> MDI1-
CL31
0.01U_0402_16V7K
1
2
3
4
5
6
7
8
MDI0+
MDI0-
MDI1+
MDI1-
TD+
TDCT
NC
NC
CT
RD+
RD-
TX+
TXCT
NC
NC
CT
RX+
RX-
16
15
14
13
12
11
10
9
DLL1
BS4200N-C-LV_SMB-F2
GAS@
MDO0+
MDO0MCT
Place Close to TL1
MCT
MDO1+
MDO1-
For EMI
MHPC_NS681612A
JLAN1
MDO0+
MDO0-
MDO1+
MCT
MCT
MDO1-
MCT
MCT
CL63 1
2 0.1U_0603_50V7K
CL61 1
2 0.1U_0603_50V7K
CL64 1
2 0.1U_0603_50V7K
CL65 1
2 0.1U_0603_50V7K
ESD
PR1+
CHASSIS1_GND
B
PR1PR2+
PR3+
PR3PR2PR4+
GND
GND
9
10
PR4SANTA_130456-121
CHASSIS1_GND
ME@
Issued Date
Compal Secret Data
2011/06/15
Deciphered Date
2012/07/11
Title
Size
B
Date:
LAN_Transformer
Document Number
Rev
1.0
LA-9632P
Sheet
1
28
of
60
2 Channel
+3VS
C329
.1U_0402_16V7K
@
SMSC thermal sensor

placed near PCH
1
U9
1
1
C587
2200P_0402_50V7K
REMOTE1+
REMOTE1-
+3VS
1 R335
Lenovo
VDD
SCLK
D+
SDATA
D-
ALERT#
THERM#
GND
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK2 <15,32>
EC_SMB_DA2 <15,32>
6
5
4.7K_0402_5%
@
EMC1402-2-ACZL-TR MSOP 8P
Address is 1001100xb
REMOTE1,2+/-:
Trace width/space:10/10 mil
Trace length:<8"
H_3P8
H_2P8
@
FD2
@
FD3
@
FD4
H_3P8
@
FD1
@
H18
HOLEA
HDD
@
H3
HOLEA
@
H2
HOLEA
CPU
@
H1
HOLEA
FAN1 Conn
H_3P8
+5VS
@
H8
HOLEA
H_2P8
H_2P8
H_2P8
@
H10
HOLEA
@
H11
HOLEA
H_2P8
H_2P8
@
H17
HOLEA
@
H16
HOLEA
ACES_85205-04001
ME@
@
H7
HOLEA
C591
10U_0603_6.3V6M
@
H6
HOLEA
1
2
3
4
G5
G6
1
2
3
4
5
6
<32> EC_TACH
0_0603_5%<32> EC_FAN_PWM
JFAN1
R581
Issued Date
M/B
Deciphered Date
2012/07/11
Title
Fintek-Thermal IC/FAN/screw
Custom
4
Rev
1.0
LA-9632P
Date: Wednesday, February 27, 2013
M/B
Compal Secret Data

2011/06/15
2P8 * 9 pcd
H_3P0N
H_2P5X3P5N
Sheet
1
29
of
60
SATA HDD Conn.

Near Connector
0.01U_0402_16V7K
0.01U_0402_16V7K
<14> SATA_ITX_C_DRX_P0
<14> SATA_ITX_C_DRX_N0
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
<14> SATA_DTX_C_IRX_N0
<14> SATA_DTX_C_IRX_P0
2
2
C596 1
C597 1
JHDD1
1 C184
1 C185
SATA_ITX_DRX_P0
SATA_ITX_DRX_N0
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_DTX_IRX_N0
SATA_DTX_IRX_P0
1
2
3
4
5
6
7
GND
RX+
RXGND
TXTX+
GND
+3VS
1
R551
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
2 +3V_HDD
0_0805_5%
@
+5VS
1
R550
2 +5V_HDD
0_0805_5%
@
Near HDD
+5VS
@
C598
1000P_0402_50V7K
1
C599
.1U_0402_16V7K
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Reserved
GND
12V
12V
12V
GND
GND
23
24
SUYIN_127043FB022G278ZR
C602
10U_0603_6.3V6M
ODD Power Control

2
J9
1
+5VALW
FOR 15"
+5V_ODD
SATA ODD FFC Conn.
JUMP_43X79
+5VS
Place CAP in Sub BD

D
<14> SATA_ITX_C_DRX_P2
<14> SATA_ITX_C_DRX_N2
<14> SATA_DTX_C_IRX_N2
<14> SATA_DTX_C_IRX_P2
OUT
IN
<19> ODD_EN
2
GND
SATA_ITX_C_DRX_P2
SATA_ITX_C_DRX_N2
R401 1 15@
R402 1 15@
2 0_0402_5%
2 0_0402_5%
SATA_DTX_C_IRX_N2
SATA_DTX_C_IRX_P2
R403 1 15@
R404 1 15@
2 0_0402_5%
2 0_0402_5%
1
R710
@
R675
100K_0402_5%
1
2
R568
10K_0402_5%
@
JODD2
1
2
3
4
5
6
7
8
9
10
DVT
Q99
LP2301ALT1G_SOT23-3
@
C607
0.01U_0402_16V7K
@
C608
10U_0603_6.3V6M
<32> ODD_DA#
+3VS
SATA_ITX_DRX_P2_15
SATA_ITX_DRX_N2_15
SATA_DTX_IRX_N2_15
SATA_DTX_IRX_P2_15
2
ODD_DETECT#
0_0402_5%
+5V_ODD
ODD_DA#
1
2
3
4
5
6
7
8
9
10
GND
GND
@
1
R555 2
10K_0402_5%
11
12
HB_A051020-SAHR21
ME@
Q100
DTC124EKAT146_SC59-3
@
Co-lay
FOR 14"
SATA ODD Conn.

JODD1
Near Connector
SATA_ITX_C_DRX_P2 14@ C616 1
SATA_ITX_C_DRX_N2 14@ C615 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_ITX_DRX_P2_14
SATA_ITX_DRX_N2_14
SATA_DTX_C_IRX_N2 14@ C614 1

SATA_DTX_C_IRX_P2 14@ C613 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_DTX_IRX_N2_14
SATA_DTX_IRX_P2_14
1
2
3
4
5
6
7
ODD_DETECT#
+5V_ODD
ODD_DA#
GND
A+
AGND
BB+
GND
8
9
10
11
12
13
DP
+5V
+5V
MD
GND
GND
GND
GND
15
14
ALLTO_C18518-11305-L
ME@
Compal Secret Data
2011/06/15
Issued Date
Deciphered Date
2012/07/11
Title

HDD/ODD/BT Connector
Custom
Date:

G
Rev
1.0
LA-9632P
Sheet
of
30
H
60
Sense resistors must be

connected same power
that is used for VAUX_3.3
CX20751
High Definition Audio Codec SoC
With Integrated Class-D Stereo
Amplifier.
An integrated 5 V to 3.3 V Low-dropout
voltage regulator (LDO).
An integrated 3.3 V to 1.8V Low-dropout
voltage regulator (LDO).
RA5
2 5.11K_0402_1%
RA6
2
1
2 20K_0402_1%
2 39.2K_0402_1%
Lenovo
JSENSE
+VREF_1V65
CA3 vendor suggest

change to 2.2U
1
1
RA7
RA8
+3VS
mount RA6 on the Jack Sense circuit

to configure Port-C for mono MIC.
10K_0402_1%
Don't support LINE_IN function

RA7 could be @
PLUG_IN
For Universal jack

D
+3VS
.1U_0402_16V7K
CA3
2 0_0402_5%
2.2U_0603_6.3V4Z
CA4
CA1
1U_0603_10V4Z
CA2
RA2
CA6
+3V_PCH
+3V_AVDD_HP
4.7U_0603_6.3V6K
2 0_0402_5%
CA5
.1U_0402_16V7K
+3VLP
.1U_0402_16V7K
+LDO_OUT_3.3V
RA1
AVDD_3.3 pinis output of

internal LDO. NOT connect
to external supply.
CA10
22P_0402_50V8J 33_0402_5%
.1U_0402_16V7K
4.7U_0603_6.3V6K
.1U_0402_16V7K
CA22
4.7U_0603_6.3V6K
CA23
CA19
.1U_0402_16V7K
CA21
CA20
CA18
4.7U_0603_6.3V6K
30
31
25
26
22
23
MICB_L
MICB_R
APPLE_MIC
NOKIA_MIC
HGNDA
HGNDB
HP_L
HP_R
Lenovo
Universal Jack
External MIC
MICB_L
RA17 1
2 100_0402_1%
MICB_R
RA18 1
2 100_0402_1%
RA20 1
2 3K_0402_5%
RA19 1
2 3K_0402_5%
+MICBIASB
CX20751-11Z_QFN40
41
HPOUT_L
HPOUT_L
HPOUT_R
HPOUT_R
HGNDB
HGNDB
HGNDA
HGNDA
LA3
0_0603_5%
LA2
0_0603_5%
@
DA1
@
DA2
@
LA4
0_0603_5%
@
JSPK1
PC_BEEP
SPK_R1SPK_R2+
SPK_L1SPK_L2+
Place colose to Codec chip
LA1
LA2
LA3
LA4
1
1
1
1
2
2
2
2
FCM1608CF-121T03
FCM1608CF-121T03
FCM1608CF-121T03
FCM1608CF-121T03
0603
0603
0603
0603
1
2
3
4
5
6
SPK_R1-_CONN
SPK_R2+_CONN
SPK_L1-_CONN
SPK_L2+_CONN
MIC1
1
CA44
.1U_0402_16V7K
WM-64PCY_2P
@
CA41
MIC_IN_C
GNDA
CA42
.1U_0402_16V7K
1
2
For EMI
1U_0603_10V4Z
2
1000P_0402_50V7K
CA38
RA23
2.2K_0402_5%
1000P_0402_50V7K
CA43
For EMI
+MICBIASC
1000P_0402_50V7K
CA40
@
RA22
10K_0402_5%
1000P_0402_50V7K
CA39
ICH Beep
RA492
1
2
33_0402_5%
HP_R
2
1U_0603_10V4Z
wide 20MIL
1
2
CA37 .1U_0402_16V7K
1
2
CA45 .1U_0402_16V7K
HP_L
1
CA29
LA1
0_0603_5%
<32> BEEP#
CA36
1
2
2.2U_0402_6.3V6M
CA46
1
2
2.2U_0402_6.3V6M
RIGHT+
RIGHT-
21
19
20
<14> HDA_SPKR
SINGA_2SJ2352-000131F
ME@
Headphone
EC Beep
5
6
32
33
For EMI
PC Beep
PLUG_IN
ESD
AVEE
FLY_P
FLY_N
Lenovo
4
3
1
2
For Universal jack
+MICBIASB
+MICBIASC
LEFT+
LEFT-
17
15
SPK_R2+
SPK_R1-
HGNDB
HGNDA
HPOUT_L
HPOUT_R
JSENSE
34
35
GND
2 .1U_0402_16V7K
2 2.2U_0402_6.3V6M
2 2.2U_0402_6.3V6M
AZ5125-02S.R7G_SOT23-3
Internal SPEAKER
CA28 1
CA27 1
12
14
SPK_L2+
SPK_L1-
2 100_0402_1%
2 100_0402_1%
2 15_0402_5%
2 15_0402_5%
2 .1U_0402_16V7K
MUSIC_REQ/GPIO0/PORTC_L_MIC PORTA_L
GPIO1/PORTC_R_MIC
PORTA_R
ME@
DA3
SPK_R1-_CONN
5
MIC_IN
SPK_R2+_CONN
I/O4
I/O2
VDD
GND
I/O3
I/O1
SPK_L2+_CONN
ACES_85205-04001
2
A
SPK_L1-_CONN
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
CX20751 Codec
Rev
1.0
LA-9632P
Date: Tuesday, March 05, 2013
1
2
3
4
G5
G6
+5VS
ESD
Custom
5
JHP1
RA16 1
RA12 1
RA13 1
RA14 1
APPLE_MIC
NOKIA_MIC
HP_L
HP_R
Please bypass caps very close to device.
AZ5125-02S.R7G_SOT23-3
2 .1U_0402_16V7K
36
37
MIC_IN
Combo Jack
(Normal Open)
HGNDA, HGNDB 80mils
100P_0402_50V8J
Internal analog MIC
PORTB_L_LINE
PORTB_R_LINE
PORTD_A_MIC
PORTD_B_MIC
DMIC_DAT/GPIO1
HGNDA
DMIC_CLK / MUSIC_REQ/GPIO0
HGNDB
1
40
For EMI
CA65 1
PC_BEEP
SPKR_MUTE#
38
For EMI
100P_0402_50V8J
CA34
2
1
<32> EC_MUTE#
JSENSE
MICBIASB
MICBIASC
10
39
PC_BEEP
CA64 1
BIT_CLK
SYNC
SDATA_IN
SDATA_OUT
100P_0402_50V8J
CA33
2
1
HDA_SDOUT_AUDIO
LPWR_5.0
RPWR_5.0
CLASS-D_REF
CA31
2
1
2 33_0402_5%
RESET#
13
16
11
100P_0402_50V8J
CA32
2
1
5
8
6
4
2.2U_0603_6.3V4Z
RA9
HDA_BITCLK_AUDIO
HDA_SYNC_AUDIO
For Layout
CA30
<14> HDA_BITCLK_AUDIO
<14> HDA_SYNC_AUDIO
<14> HDA_SDIN0
<14> HDA_SDOUT_AUDIO
HDA_RST_AUDIO#
For Layout
CA35
<14> HDA_RST_AUDIO#
CA66 1
UA1
CA26
29
@
1 RA21
+5VS
.1U_0402_16V7K
@
CA11
.1U_0402_16V7K
.1U_0402_16V7K
@
CA7
27
28
24
HDA_RST_AUDIO#
.1U_0402_16V7K
CA15
10 mils
For EMI
1U_0603_10V4Z
CA9
.1U_0402_16V7K
+5VS
+LDO_1.8V
AVDD_3.3
AVDD_5V
AVDD_HP
Layout Note:Path from +5VS to LPWR_5.0

RPWR_5.0 must be very low
resistance (<0.01 ohms)
VREF_1.65V
@
RA15
4.7K_0402_5%
3
7
2
18
2 0_0402_5%
FILT_1.8
VDD_IO
VDDO_3.3
DVDD_3.3
.1U_0402_16V7K
2 0_0402_5%
CA24
4.7U_0603_6.3V6K
CA25
RA4
.1U_0402_16V7K
+3V_PCH
CA17
+3VS
+3VS
CA16
ESD
RA3
@
4.7U_0603_6.3V6K
CA8
Should be same supply rail as used for

@
PCH HDA bus controller section
1U_0603_10V4Z
+3VS
Sheet
1
31
of
60
+3VLP
1@
C535
100P_0402_50V8J
0_0603_5%
<19> EC_SCI#
<37> BATT_LEN#
C661
.1U_0402_16V7K
C47
22P_0402_50V8J
KSO[0..15]
<33> KSO[0..15]
KSI[0..7]
<33> KSI[0..7]
ESD
+3V_EC
R600
2
EC_SMB_CK1
2.2K_0402_5%
R604
2
EC_SMB_DA1
2.2K_0402_5%
EC_SMB_DA2
EC_SMB_CK2
@
C665
100P_0402_50V8J
@
C666
100P_0402_50V8J
<33> KSO16
<33> KSO17
+3VALW
<37,38>
<37,38>
<15,29>
<15,29>
<30> ODD_DA#
<36> ADP_ID_CLOSE
<29> EC_TACH
<27> LAN_WAKE#
<26,33> EC_TX
<26,33> EC_RX
<16> PCH_PWROK
<33> NOVO#
R608 1
100K_0402_5%
@
Share ROM
EC_TACH
LAN_WAKE#
EC_TX
EC_RX
PCH_PWROK
NOVO#
NUM_LED#: NC
122
123
<16> SUSCLK
<18> DGPU_PWR_EN
XCLKI/GPIO5D
XCLKO/GPIO5E
ODD_DA#
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A
@
R740
100K_0402_5%
@
C93
20P_0402_50V8
63
64
65
66
75
76
BATT_TEMP
15K +/- 1%
20K +/- 1%
VAD_BID min
0 V
0.347V
0.423V
0.541V
V AD_BID typ
0 V
0.354V
0.430V
0.550V
VAD_BID max
0 V
0.360V
0.438V
0.559V
ADP_65 <37>
PS2 Interface
CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
HDA_SDO/GPXIOA02
VCIN0_PH/GPXIOD00
SPI Flash ROM
GPIO
GPIO
MP
PVT
DVT
EVT
+3VALW
BEEP# <31>
EC_FAN_PWM <29>
ACOFF <38>
@
R694
100K_0402_1%
BATT_TEMP <36,37>
+5VALW
ADP_I <37,38>
ADP_ID
BRDID
ADP_ID <36>
BRDID
ENBKL <17>
68
70
71
72
ADP_90
83
84
85
86
87
88
SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A
ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59
USB_ON#
ADP_135
SYS_PWROK_R
TP_CLK
TP_DATA
EC_TS_ON#
119
120
126
128
EC_SPI_SO
EC_SPI_SI
EC_SPI_CLK
EC_SPI_CS#
R417 1
@
1 R593
EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
GPI
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
V18R
100
101
102
103
104
105
106
107
108
10K_0402_5%
R695
PVT2@
20K_0402_1%
R695
PVT@
12K_0402_1%
R695
DVT@
15K_0402_1%
+5VS
EC_MUTE# <31>
USB_ON# <34>
ADP_135 <37>
SYS_PWROK <16>
2 0_0402_5%
TP_CLK <33>
TP_DATA <33>
+5VS
R603 1
2 4.7K_0402_5%
R598 1
2 4.7K_0402_5%
TP_CLK
EC_TS_ON# <34>
TP_DATA
ME_FLASH <14>
NTC_V <37>
BATT_TEMP
EC_SPI_SO <14>
EC_SPI_SI <14>
EC_SPI_CLK <14>
EC_SPI_CS# <14>
ACIN
1
C663
1
C664
1
R522
2
100P_0402_50V8J
2
100P_0402_50V8J
2
@ 4.7K_0402_5%
IMVP_IMON <43>
VGATE <16,43>
LAN_PWR_ON# <27>
BATT_CHG_LED# <33>
BATT_CHG_LED#
CAPS_LED#
CAPS_LED# <33>
PWR_LED# <33>
BATT_LOW_LED# <33>
SYSON <40>
VR_ON <43>
PM_SLP_S4# <16>
BATT_LOW_LED#
SYSON
H_PROCHOT# <36,37,43,6>
EC_RSMRST# <16>
EC_LID_OUT# <19>
EC_LID_OUT#
Turbo_V
R738 1
MAINPWON_R
BKOFF#
PBTN_OUT#
PCH_PWR_EN
110
112
114
115
116
117
118
LID_SW#
SUSP#
NUVOTON_VTT
PECI_KB9012
124
+V18R
KB9012QF A3 LQFP 128P_14X14
R695
100K_0402_1%
10K_0402_5%
+3VALW
97
98
99
109
73
74
89
90
91
92
93
95
121
127
USB_ON# 1
ADP_90 <37>
SPI Device Interface
Bus
EC AD
0x00 - 0x0B
0x0C - 0x1C
0x1D - 0x26
0x27 - 0x30
ADP_65
BEEP#
EC_FAN_PWM
ACOFF
EC_MUTE#
EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F
ECAGND
EC_TACH
10K_0402_5%
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
EC_SMI#
BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43
DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F
DA Output
EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47
21
23
26
27
12K +/- 1%
Board ID / SKU ID Table for AD channel
R594
GND/GND
GND/GND
GND/GND
GND/GND
GND0
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
CMOS_ON#
R605
AD Input
CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13
PWM Output
11
24
35
94
113
+3VS
77
78
79
80
GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0
LAN_WAKE#
10K_0402_5%
<16>
<16>
<16,19>
<23>
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
2
R606
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
EC_RST#
EC_SCI#
BATT_LEN#
12
13
37
20
38
<18> CLK_PCI_EC
<18,26,27> PLT_RST#
2
47K_0402_5%
2
1
R590
+3V_EC
10_0402_5%
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
1
2
3
4
5
7
8
10
AGND/AGND
2
1
2
1
@ C660 22P_0402_50V8J @ R589
<19> GATEA20
<19> KBRST#
<14> SERIRQ
<14> LPC_FRAME#
<14> LPC_AD3
<14> LPC_AD2
<14> LPC_AD1
<14> LPC_AD0
R695
0
2 0_0402_5%
R669
2
43_0402_1%
Q37
2N7002H_SOT23-3
C493
47P_0402_50V8J
+3VALW
ACIN <16,36,38>
EC_ON <39>
ON/OFF <33>
LID_SW# <33>
SUSP# <35,40,42>
2
G
PROCHOT
BKOFF# <23>
PBTN_OUT# <16>
PCH_PWR_EN <20>
SA_PGOOD <41>
ACIN
EC_ON
Turbo_V <37>
PROCHOT <37>
MAINPWON <39>
LID_SW#
1 R618
2
100K_0402_5%
H_PECI <6>
+V1.05S_VCCP
NUVOTON_VTT
R410 1
2 0_0402_5%
EMC Request
SYSON
.1U_0402_16V7K
C492
ECAGND
U31
C667
4.7U_0603_6.3V6K
67
EC_VDD/AVCC
69
0
1
2
3
+EC_VCCA
9
22
33
96
111
125
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC
1000P_0402_50V7K
C658
1000P_0402_50V7K
C662
1000P_0402_50V7K
C656
.1U_0402_16V7K
2 ECAGND
2
L45
FBM-11-160808-601-T_0603
+EC_VCCA
C659
C654
.1U_0402_16V7K
C653
.1U_0402_16V7K
+3V_EC
100K +/- 1%
Board ID
L44
FBM-11-160808-601-T_0603
1
2
1
3.3V
Vcc
R694
@ R416
1
+3V_EC
2
0_0603_5%
@
R304
+3VALW
SA00004OB30
S IC KB9012QF A4 LQFP 128P KB CONTROLLER
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title

BIOS & EC I/O Port
Size
Document Number
Custom
Date:
Rev
1.0
LA-9632P
Sheet
32
of
60
KSI[0..7]
KSI[0..7]
KSO[0..17]
KSO[0..17]
<32>
JKB1
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
KSO16
KSO17
<32>
JP3
1
2
3
4
+3VALW
<26,32> EC_TX
<26,32> EC_RX
1
2
3
4
ACES_85205-0400
ME@
@
R415
100K_0402_5%
@
1 R414
2
0_0402_5%
+3VLP
+3VALW
R642
100K_0402_5%
@
2
R701
100K_0402_5%
D26
NOVO#
<32> NOVO#
JKB2
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
31
32
GND
GND
ME@
GND2
GND1
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ACES_88514-2401
ACES_88514-3001
2
1
SHORT PADS
J11
ME@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
<32,33> KSO16
<32,33> KSO17
+3VLP
J12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NOVO_BTN#
3
ON/OFF
DAN202UT106_SC70-3
@
2
SHORT PADS
ON/OFF
ON/OFF
+3VS
<32>
For EMI
JCR1
LED1 14@
<32> PWR_LED#
PWR_LED#
2
2 14@
1
+5VALW
R623
649_0402_1%
1 R687@
1 R683@
USB20_N11
USB20_P11
<18> USB20_N11
<18> USB20_P11
1
2
3
4
2 0_0402_5% USB20_N11_R
2 0_0402_5% USB20_P11_R
19-213A-T1D-CP2Q2HY-3T_WHITE
1
2
3
4
GND
GND
L57 @
USB20_N11
USB20_P11
+5VS
LED2 14@
<32> BATT_LOW_LED#
JTP1
@
C696
8
7
2 R764
1
470_0402_5%
ME@
15@
2 R627
1
0_0402_5%
1
@ D15
PSOT24C_SOT23-3
TP_3
2 R619
1 14@ TP_1
0_0402_5%
6
5
4
3
2
1
CVILU_CF06041H0RB-NH
ME@
3
USB20_P11_R
+3VALW
14@
+3VALW
LED5 14@
<32> BATT_CHG_LED#
BATT_CHG_LED#
2
2 14@
1
+5VALW
R765
649_0402_1%
JPWRB1
<32> LID_SW#
NOVO_BTN#
ON/OFF
1
2
3
4
5
6
7
8
D24
ESD
LED6 14@
<32> CAPS_LED#
CAPS_LED#
2 14@
1
+5VS
R2
649_0402_1%
1
2
3
4
5
6
GND
GND
ACES_88058-060N
ME@
L30ESD24VC3-2 3P C/A SOT23 ESD
5
6
USB20_N11_R
GND
GND
ACES_88058-060N
Lenovo
C698 @
100P_0402_50V8J
.1U_0402_16V7K
C491
.1U_0402_16V7K
C490
6
5
4
3
2
1
TP_CLK
TP_DATA
TP_3
TP_2
TP_1
@ C697
100P_0402_50V8J
WCM-2012-900T_4P
HT-191UD5_AMBER
.1U_0402_16V7K
<32> TP_CLK
<32> TP_DATA
BATT_LOW_LED#
SW4
14@
SMT1-05_4P
5
6
5
6
SW5
14@
SMT1-05_4P
TP_2
SW6
15@
SMT1-05_4P
5
6
5
6
TP_3
15/17"
SW7
15@
SMT1-05_4P
TP_2
ESD
14"
VCC
VCC
CLK
CLK
DAT
DAT
GND
JLED1
+5VALW
+3VALW
+5VS
LID_SW#
PWR_LED#
BATT_LOW_LED#
BATT_CHG_LED#
CAPS_LED#
TP_1
GND
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
GND
GND
HB_A091020-SAHR21
ME@
For 15"
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
Size
C
Date:

ROM/KBD/PWR/CR/LED/TP Conn.
Document Number
Rev
1.0
LA-9632P
Sheet
33
of
60
ESD
@
D27
U3RXDN1 9
1 U3RXDN1
U3RXDN2 9
1U3RXDN2
U3RXDP1 8
2 U3RXDP1
U3RXDP2 8
2U3RXDP2
U3TXDN1 7
4 U3TXDN1
U3TXDN2 7
4U3TXDN2
U3TXDP1 6
5 U3TXDP1
U3TXDP2 6
5U3TXDP2
U2DN1
D31
I/O2
D22
D30
I/O4
GND
VDD
I/O1
I/O3
U2DP2
+5VALW
U2DP1
I/O2
I/O4
GND
VDD
I/O1
I/O3
+5VALW
U2DN2
For EMI
USB3.0
Intel_PCH_USB2.0
WCM-2012HS-900T
<18> USB20_N1
<18> USB20_P1
USB2@ 3
L55
Ext. USB2.0
U2DN2
U2DP2
U3RXDN2
U3RXDP2
Touch Screen
Left Ext.USB Conn. 2
Intel_PCH_USB3.0
WCM-2012HS-900T
+5VALW
+USB_VCCB
RIGHT USB PORT X1
<32,34> USB_ON#
<18> USB3_RX2_P
U36
1
2
3
4
<18> USB3_RX2_N
4
L54
8
GND VOUT 7
VIN VOUT 6
VIN VOUT 5
EN
FLG
G547I2P81U_MSOP8
+USB3_VCCA
W=80mils
USB3@ 3
JUSB2
9
1
8
3
7
2
6
4
5
U3TXDP2
SSTX+
VBUS
SSTXD+
GND
10
DGND 11
SSRX+
GND 12
GND
GND 13
SSRXGND
TAITW_PUBAU1-09FNLSCNN4H0
ME@
U3TXDN2
U2DP2
JTS1
USB_OC4# <18>
8
7
6
5
4
3
2
1
+3VS_TS
<18> USB20_N2
<18> USB20_P2
EC_TS_ON#
R726 1
TS@ 2 0_0402_5% TS_RST#
U2DN2
U3RXDP2
GND
GND
6
5
4
3
2
1
ACES_50208-00601-P01
ME@
<18> USB3_TX2_N
<18> USB3_TX2_P
1
1
C850USB3@
.1U_0402_16V7K
2 U3TXDN2_L
WCM-2012HS-900T
U3TXDP2_L
4
L53
C848USB3@
.1U_0402_16V7K
U3RXDN2
2
USB3@ 3
U3TXDN2
U3TXDP2
Near HDMI Conn.

USB Debug Port
Right Ext.USB Conn.

JUSB3 ME@
+USB_VCCB
@
R503
10_0402_5%
USB20_P9
1
L66
<32> EC_TS_ON#
R5581 @
100K_0402_5%
2
C1331
.1U_0402_16V7K
@
C2
1.2P_0402_50V8C
L51
Q156
LP2301ALT1G_SOT23-3
@
2 USB20_P9_C
2
@
C1
WCM-2012HS-900T
1.2P_0402_50V8C
@
R504
10_0402_5%
<18> USB20_P0
USB20_N9_C
USB20_N9
1 0_0402_5% USB20_N9_C
1 0_0402_5%
USB20_P9_C
<18> USB20_N9
@
<18> USB20_P9
C715
470P_0402_50V7K
@
@
U2DN1
U2DP1
U3RXDN1
U3RXDP1
0_0402_5%
D
R868 2
R869 2
USB20_N9
USB20_P9
WCM-2012HS-900T
<18> USB20_N0
R5583
S
C714
220U_6.3V_M
Intel_PCH_USB2.0
+3VS_TS
1 TS@
6
5
4
3
2
1
ACES_88058-060N
+3VS
GND
GND
6
5
4
3
2
1
.1U_0402_16V7K
C1322
8
7
W=80mils
+USB_VCCB
USB2@
Left Ext.USB Conn. 1
Intel_PCH_USB3.0
WCM-2012HS-900T
<18> USB3_RX1_N
TS@
<18> USB3_RX1_P
+USB3_VCCA
W=80mils
USB3@
JUSB1
U3TXDP1
L50
U3TXDN1
U2DP1
For EMI
U2DN1
U3RXDP1
<18> USB3_TX1_N
<18> USB3_TX1_P
1
1
C849USB3@
.1U_0402_16V7K
2
U3TXDN1_L
U3TXDP1_L
C847USB3@
.1U_0402_16V7K
WCM-2012HS-900T
U3RXDN1
2
3
USB3@
U3TXDN1
U3TXDP1
9
1
8
3
7
2
6
4
5
SSTX+
VBUS
SSTXD+
GND
10
DGND 11
SSRX+
GND 12
GND
GND 13
SSRXGND
TAITW_PUBAU1-09FNLSCNN4H0
ME@
Near Audio Jack
L49
Place TX AC coupling Cap (C843~C850). Close to connector

2A/Active Low
+5VALW
+USB3_VCCA
U35
1
2
3
4
<32,34> USB_ON#
W=80mils
8
GND VOUT 7
VIN VOUT 6
VIN VOUT 5
EN
FLG
G547I2P81U_MSOP8
USB_OC0# <18>
1
+
C736
220U_6.3V_M
@
C735
470P_0402_50V7K
2011/06/15
Deciphered Date
2012/07/11
Title
USB3.0/Left USB Ports
Size
Document Number
Custom
Date:
Compal Secret Data
Issued Date
Rev
1.0

1
Sheet
34
of
60
+5VALW to +5VS
+5VALW
+3VALW to +3VS
+5VS
+3VALW
+3VS
2@
@
C725
1U_0603_10V4Z
B+
R647
470K_0402_1%
2 SUSP
G
Q108
2N7002H_SOT23-3
@
2
D
2
G
DVT
R650
Q111
0_0402_5%
2N7002H_SOT23-3
@
C727
2200P_0402_25V7K
SUSP
DVT
C726
2200P_0402_25V7K
82K_0402_5%
Q110
2N7002H_SOT23-3
15VS_GATE_R
1
5VS_GATE2 R649
D
2
G
SUSP
R646
150K_0402_5%
R645
470_0603_5%
@
2 SUSP
G
Q107
2N7002H_SOT23-3
@
C724
C723
1 2
1 2
B+
R644
470_0603_5%
@
4.7U_0603_6.3V6K
@
C722
1U_0603_10V4Z
C721
U39
8
1
7
2
6
3
5
4.7U_0603_6.3V6K
8
1
7
2
6
3
5
4.7U_0603_6.3V6K
C720
4.7U_0603_6.3V6K
U38
+1.5V to +1.5VS
+0.75VS
C719
1U_0603_10V4Z
+3VALW
+3VLP
2
0_0402_5%
@
1.5VS_GATE
OUT
Q117
DTC124EKAT146_SC59-3
SUSP
<10> SUSP
R652
220K_0402_5%
SUSP# 2
G
2N7002H_SOT23-3
@
R653
220K_0402_5%
Q112
+RTCVCC
2 SUSP
G
Q109
2N7002H_SOT23-3
@
C729
100K_0402_5%
R648
R651
1
2
.1U_0402_16V7K
R643
470_0603_5%
@
DVT
C718
C717
1 2
2
SUSP
G
Q115
2N7002H_SOT23-3
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
2 SUSP
G
Q116
2N7002H_SOT23-3
@
3
1
R658
22_0603_5%
R659
470_0603_5%
@
+1.5VS
Q8
LP2301ALT1G_SOT23-3
S
1 2
+1.5V
+V1.05S_VCCP
IN
GND
<32,40,42> SUSP#
R1110 @
100K_0402_5%
Issued Date
Compal Secret Data
2011/06/15
Deciphered Date
2012/07/11
Title
Custom
Date:
DC Interface
Rev
1.0
LA-9632P
Sheet
E
35
of
60
VIN
PF101
7A_24VDC_429007.WRML
PQ102A
2N7002KDW-2N_SOT363-6
1
PC108
0.1U_0402_16V7K
2
1
750_0402_1%
PR110
VIN
2
1
PR111
100K_0402_1%
PQ102B
2N7002KDW-2N_SOT363-6
4
3
100K_0402_1%
1000P_0402_50V7K
ADP_ID <32>
PC109
680P_0402_50V7K
PR102
1
+3VALW
PC104
2
1
ACES_50312-00541-001
@
PC103
2
1
PC101
2
1
2 APDIN1
PC102
2
1
APDIN
100P_0402_50V8J
1
2
3
4
5
1000P_0402_50V7K
1
2
3
4
5
PL101
SMB3025500YA_2P
1
2
JDCIN1
100P_0402_50V8J
ADP_ID_CLOSE <32>
+5VS
10K_0402_1%
PR108
2
1
@
BATT_TEMP <32,37>
PR109
1
0.022U_0402_16V7K
3
2
100K_0402_1%
2
@
@
PU101A
AS393MTR-E1 SO 8P OP
PC107
100P_0402_50V8J
2
1
PR106
1
RTC Battery
PR104
JRTC1 @
1
2 1
3 2
4 GND
GND
@ PC105
2
1
+3VALW
1.5M_0402_5%
+CHGRTC_R
PR101
1K_0603_5%
1
2
+3VLP
1N4148WS-7-F_SOD323-2
PD105
2
1
+RTCBATT
PD101
S SCH DIO BAS40CW SOT-323
2
1
3
PQ101A
2N7002KDW-2N_SOT363-6
PR103
1K_0603_5%
1
2
<32,37,43,6> H_PROCHOT#
+CHGRTC
47K_0402_1%
+5VS
PC106
2
1
8
-
5
6
ACIN <16,32,38>
PU101B
2
PR105
1
0.022U_0402_16V7K
1.5M_0402_5%
PD104
PR107
1
1N4148WS-7-F_SOD323-2
2
1
PQ101B
A
2N7002KDW-2N_SOT363-6
4
3
H_PROCHOT#
47K_0402_1%
ACES_50271-0020N-001
@
A
Issued Date
Compal Secret Data
2011/06/15
2012/07/11
Deciphered Date
Title
PWR DCIN / RTC Battery
Rev
1.0
Gx00
Date:
Sheet

1
36
of
60
PF201
12A_65V_451012MRL
2
PL201
SMB3025500YA_2P
1
2
20120314
Change to +EC_VCCA from +3VLP
1
PC203
0.01U_0402_25V7K
D
<32,38> ADP_I
2
2
PR228
5.9K_0402_1%
1
4
+3VLP
PD201
2
PR205
1.5M_0402_5%
PC207
100P_0402_50V8J
1N4148WS-7-F_SOD323-2
PU201A
1
3
1
2
PQ202B
2N7002KDW-2N_SOT363-6
2
PR213
100K_0402_1%
BATT_OUT <38>
ECAGND
PC208
0.068U_0402_16V7K~N
1
O
-
PQ202A
2N7002KDW-2N_SOT363-6
<32> ADP_135
6 1
1
2
2
1
<32,36,37> BATT_TEMP
100K_0402_1%
100K_0402_1%
PR210
47K_0402_1%
2
G
PR214
PR211
0.01U_0402_25V7K
PR202
75K_0402_1%
1
2
VL
PC202
2
G
<32> ADP_90
C
VL
PR221
8.45K_0402_1%
S
+3VALW
PR222
100K_0402_1%
PQ207
2N7002KW_SOT323-3
2
G
<32> ADP_65
<32,37> PROCHOT
PR227
9.31K_0402_1%
1
<32,37> PROCHOT
A/D
BATT_TEMP <32,36,37>
1
2
PR207
10K_0402_5%
PR216
0_0402_5%
1
2
@
2N7002KW_SOT323-3
PQ208
2N7002KW_SOT323-3
+3VALW
PR229
100K_0402_1%
1
2
PR206
6.49K_0402_1%
<32> NTC_V
ADP_OCP_1
2
G
<32> Turbo_V
PR225
25.5K_0402_1%
PQ206
2N7002KW_SOT323-3
PQ201
+3VLP
2
PR215
<32,36,43,6> H_PROCHOT#
@
1
2
PR209
6.49K_0402_1%
@
1
2
3
4
5
6
7
8
9
SUYIN_200082GR007M229ZR
1
2
3
4
5
6
7
GND
GND
100K_0402_1%
EC_SMB_DA1 <32,38>
JBATT2
+EC_VCCA
+3VS
EC_SMB_CK1 <32,38>
PC201
1000P_0402_50V7K
2
1
PR204
100_0402_1%
90W(DIS) : 6.65K 100W active 90W recovery

65W(UMA): 1.65K 70W active 65W recovery
PH201 under CPU botten side :

CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C
KCBUU3!...?!!25#
BATT+
EC_SMCA
EC_SMDA
PH201
100K_0402_1%_TSM0B104F4251RZ
2
1
PR201
100_0402_1%
SUYIN_200082GR007M229ZR
KCBUU2!...?!!26#
VMB
@
JBATT1
1
1 2
2 3
3 4
4 5
5 6
6 7
7 8
GND 9
GND
PR226
12.7K_0402_1%
VMB2
PR220
B
@ PR218
1
3
PQ205
2N7002KW_SOT323-3
@ PR223
1.5M_0402_5%
1N4148WS-7-F_SOD323-2
PU201B
PD203
@ PC210
0.068U_0402_16V7K~N
8
P
O
-
@ PC213
100P_0402_50V8J
2
1
2
G
PQ209
2N7002KW_SOT323-3
<32> BATT_LEN#
2
G
47K_0402_1%
@ PR217
100K_0402_1%
1
@
100K_0402_1%
VL
+3V_LDO
@ PR208
75K_0402_1%
VMB
@ PU202
OUT
+3V_LDO
GND
SHDN#
BYP
IN
G9191-330T1U_SOT23-5
@ PC212
22U_0603_6.3V6M
2
1
+5VALW
@
PC209
4.7U_0402_6.3V6M
@ PC211
1U_0402_16V6K
Issued Date
Compal Secret Data
2011/06/15
2012/07/11
Deciphered Date
Title
PWR-BATTERY CONN/OTP
Rev
1.0
Gx00-CR
Date:
Sheet

1
37
of
60
B+
P3
P2
PQ301
AO4407AL_SO8
PQ302
AO4423L_SO8
PR301
0.01_1206_1%
CHG_B+
2
1
1
2
3
PC319
2200P_0402_50V7K
PC316
10U_0805_25V6K
DISCHG_G
PR322
200K_0402_1%
1
2
VIN
2ACOFF-1
PD302
PD303
1SS355_SOD323-2
BTST
GND
SRP
17
PR320
PC317
2.2_0603_5%
0.047U_0603_16V7K
1
2
2
1
BST_CHG
PD301
REGN
16
4
1
3
2
1
15
14
2
1
PR318
10_0402_5%
13
RB751V-40_SOD323-2
PC312
1U_0603_25V6K
1
3
CHG1
SRP
BATT+
SRN
1
PC305
0.1U_0402_25V6
DL_CHG
PC306
0.1U_0402_25V6
2
1
BQ24737VDD
SCL
ILIM
DH_CHG
PACIN
PL302
PR324
10UH_PCMB104T-100MS_6A_20% 0.01_1206_1%
LX_CHG
18
2
G
S
PC322
10U_0805_25V6K
2
1
1U_0603_25V6K
19
PQ309
S TR MDS1660URH 1N SO8
5
6
7
8
PR319
10_1206_5%
2
1
ACN
HIDRV
SRN
PR316
100K_0402_1%
2
ACP
PHASE
PU301
BQ24727RGRR_VQFN20_3P5X3P5
PR323
4.7_1206_5%
SDA
124737_SN
2
+3VALW
10
PR315
316K_0402_1%
1
2
IOUT
BM
<32,37> EC_SMB_CK1
BQ24737VCC
2N7002KW _SOT323-3
PC320
680P_0603_50V7K
20
PQ310
S TR MDS1521URH 1N SO8
<32,37> EC_SMB_DA1
PC314
VCC
3
2
1
21
5
6
7
8
100P_0402_50V8J
8
TP
PC324
0.1U_0402_25V6
2
1
LODRV
0.1U_0402_25V6
ACDET
CMPOUT
6
PC304
1
2
ACOK
<32,37> ADP_I
PC303
1
2
CMPIN
392K_0402_1%
1
PR309
2
PR308
64.9K_0402_1%
1
2
PQ313
P2
0.1U_0402_25V6
11
6.8_0402_5%
1
12
PR317
PC308
2N7002KW_SOT323-3
2
G
VIN
PR326
10K_0402_5%
<37,38> BATT_OUT
PR325
200K_0402_1%
2ACOFF-1
2
PQ314
0.1U_0402_25V6
<32> ACOFF
1
PQ305
DTC115EUA_SC70-3
ACON
PR305
150K_0402_1%
2
P2-2
3
4
PQ306
2N7002KW _SOT323-3
2
BATT_OUT <37,38>
G
2N7002KDW-2N_SOT363-6
PR303
47K_0402_1%
1
2
PACIN
PACIN
PQ307B
1 2
3
6
1
<38> ACPRN
PR306
20K_0402_1%
PQ311
DTC115EUA_SC70-3
DTC115EUA_SC70-3
PC311
1DISCHG_G-1
1
PC307
0.1U_0402_25V6
1
2
PR321
47K_0402_1%
1SS355_SOD323-2
2
1
ACP
PQ307A
2N7002KDW -2N_SOT363-6
ACN
P2-1
PQ303
8
7
6
5
PC323
10U_0805_25V6K
2
1
PC301
5600P_0402_25V7K
2
1
PC302
0.1U_0603_25V7K
2
1
PR304
200K_0402_1%
1
PR302
47K_0402_5%
2
DTA144EUA_SC70-3
PQ304
PQ312
AO4407AL_SO8
PC315
10U_0805_25V6K
1
2
2
PL301
1UH_PCMB061H-1R0MS_7A_20%
PC313
@ 10U_0805_25V6K
8
7
6
5
PC310
@ 10U_0805_25V6K
1
2
3
1
2
3
8
7
6
5
VIN
PC309
0.1U_0402_25V6
PR314
10K_0402_1%
1
2
BQ24737VDD
PR310
10K_0402_1%
3
A
1
S
PR312
2
2
G
2N7002KW_SOT323-3
PQ308
ACPRN <38>
ACIN <16,32,36>
PACIN
PR307
47K_0402_1%
12K_0402_1%
2011/06/15
Issued Date
Compal Secret Data
2012/07/11
Deciphered Date
Title
Size
Date:
CHARGER
Document Number
Rev
1.0
Gx00-CR
Sheet
W ednesday, February 27, 2013

1
38
of
60
PR411
1
3V5V_EN_R
3V5V_EN
0_0402_5%
PU401
3V5V_EN_R
PC439
1
2
SPOK
PG
LDO
PL402
+3VLP
PC414
4.7U_0603_6.3V6M
1 ENLDO_3V5V
SY8208BQNC_QFN10_3X3
@
PR412
0_0402_5%
5V_VIN
PR413
1
1K_0402_5%
3V5V_EN
PC421
0.1U_0603_25V7K
1
2
PR405
0_0603_5%
LDO
VL
SY8208CQNC_QFN10_3X3
+5VALWP
3.3UH +-20% PCMB063T-3R3MS 6.5A

1
PG
OUT
PL404
1
LX_5V
680P_0603_50V7K 4.7_1206_5%
VCC
10
PC429 @
PR406 @
2
1 5V_SN
2
1
LX
PC430
4.7U_0603_6.3V6M
1
2
PC422
4.7U_0603_6.3V6M
GND
2@
PC438
470P_0402_50V8J
BST_5V
PC437
470P_0402_50V8J
2
1
PC433
150U_D2_6.3VY_R15M
PC428 @
22U_0805_6.3V6M
BS
PC427
22U_0805_6.3V6M
2
1
EN2
PC426
22U_0805_6.3V6M
2
1
EN1
PC425
22U_0805_6.3V6M
2
1
IN
PC424
22U_0805_6.3V6M
2
1
5V_VCC
EC_ON
PU402
<32> EC_ON
6800P_0402_25V7K
PC418
0.1U_0402_25V6
2
1
PC417
2200P_0402_50V7K
2
1
PC416
10U_0805_25V6K
2
1
PC420
10U_0805_25V6K
2
1
PC419
68P_0402_50V8J
2
1
PC436
1
2
+3VALWP
PC423
22U_0805_6.3V6M
2
1
PL403
HCB2012KF-121T50_0805
1
2
1.5UH_PCMC063T-1R5MN_9A_20%
B+
LX_3V
PC435
470P_0402_50V8J
OUT
1K_0402_5%
0.1U_0603_25V7K
10
@
1
GND
PR416
2
0.01U_0402_25V7K
PC402
2
PC434
470P_0402_50V8J
2
1
PR401
0_0603_5%
LX
PC413
22U_0805_6.3V6M
2
1
PC412
22U_0805_6.3V6M
2
1
BST_3V 2
PC410
22U_0805_6.3V6M
2
1
PC409
22U_0805_6.3V6M
2
1
BS
EN2
EN1
IN
PC408
22U_0805_6.3V6M
2
1
IN
680P_0603_50V7K
4.7_1206_5%
PC406
10U_0805_25V6K
2
1
PC405
10U_0805_25V6K
2
1
PC404
2200P_0402_50V7K
2
1
PC403
0.1U_0402_25V6
2
1
3V_VIN
PC415 @
PR404
2
1 3V_SN
2
PL401
HCB2012KF-121T50_0805
1
2
PC401
68P_0402_50V8J
2
1
B+
B+
PC407
1U_0603_25V6K
2
1
@ PR415
2
PR402
499K_0402_1%
2
1
PR403
150K_0402_1%
2
1
PR414
0_0402_5%
2
1 ENLDO_3V5V
PC411
22U_0805_6.3V6M
2
1
PC432
0.047U_0402_25V7K
10K_0402_5%
PR407
2.2K_0402_5%
2
1
@ PJ401
1
+3VALWP
+3VALW
JUMP_43X118
MAINPWON
<32> MAINPWON
PR408
0_0402_5%
@ PJ402
1
2
+5VALWP
PC431
4.7U_0402_6.3V6M
1
PR409
1M_0402_1%
3V5V_EN
+5VALW
JUMP_43X118
2011/06/15
Issued Date
Compal Secret Data
2012/07/11
Deciphered Date
Title
+1.05VS_VCCP
Rev
1.0
Gx00-CR
Date:
Sheet

E
39
of
60
PL502
UG_1.5V
1
Off
13
3
2
1
1
2
PC513
2200P_0402_50V7K
PR515
4.7_1206_5%
@
PC517
680P_0603_50V7K
PC521
PC522
330U_2.5V_M 2
2 220U_6.3V_M
12
11
2
1
PR514
5.1_0603_5%
+5VALW
+1.5VP
OCP min 20A
OVP min 1.65V
PC511
1U_0603_10V6K
+3VALW
PC510
1U_0603_10V6K
2
1
PGOOD
PR511
6.65K_0402_1%
2
1
10
TON
LG_1.5V
14
2
1
PR510
10K_0402_5%
PHASE
BOOT
S5
15
S5_1.5V
S3
S3_1.5V
VDD
PGOOD_1.5V
PR507
5.9K_0402_1%
2
1
PJ504
2
@
JUMP_43X118
@ PC508
0.1U_0402_16V7K
17
+1.5VP
PR509
887K_0402_1%
2
1 1.5V_B+
PC503
0.1U_0402_16V6K
PL501
1UH_PCMB104T-1R0MH_18A_20%
2
1
16
18
VDDQ
FB
VDDP
PR505
0_0402_5%
1
2
<32> SYSON
CS
RT8207MZQW _W QFN20_3X3
VTTREF
UGATE
20
GND
PGND
PR502
64.9K_0402_1%
1
2
<32,35,40,42> SUSP#
LGATE
VTTSNS
PC506
0.033U_0402_16V7K
19
VTTGND
+1.5VP
VLDOIN
+VTT_REFP
VTT
PAD
1
2
PC505
10U_0805_25V6K
PC504
10U_0805_25V6K
PU501
21
PR501
PC512
2.2_0603_5%
0.1U_0603_25V7K
1
2 BST_1.5V-1
1
2
BST_1.5V
+0.75VSP
3
2
1
LX_1.5V
PR503
0_0603_5%
Note: S3 - sleep ; S5 - power off
Off
PC509
0.1U_0402_25V6
Off
S4/S5
1
Lo
+1.5VP
Lo
On
Off
(Hi-Z)
PC520
4.7U_0805_25V6-K
On
On
On
On
Hi
Hi
Lo
Hi
S3
0.75VSP
S0
PC501
10U_0805_25V6K
VTT_REFP
PQ501
MDU1516URH_POWERDFN56-8-5
1.5VP
PQ502
MDU1511RH_POWERDFN56-8-5
S5
S3
B+
1
2
HCB2012KF-121T50_0805
1.5V_B+
STATE
PJ505
1
+1.5VP
PR506
5.76K_0402_1%
+1.5V
JUMP_43X118
@ PC526
0.1U_0402_16V6K
PJ506
2
+0.75VSP
+0.75VS
JUMP_43X79
@
3
PU502
SY8033BDBC_DFN10_3X3
PR504
1M_0402_5%
1
2
PC519
0.1U_0402_25V6
PC518
68P_0402_50V8J
1
2
PC516
2200P_0402_50V7K
PC515
22U_0805_6.3VAM
1
2
PC514
22U_0805_6.3VAM
@
PC524
0.1U_0402_10V7K
PC525
68P_0402_50V8J
2
1
PG
PR512
20K_0402_1%
+1.8VSP
PJ507
2
+1.8VSP
+1.8VS
@ JUMP_43X79
1.8VSP_FB
1
0_0402_5%
11
2 EN_1.8VSP
PC507 @
0.1U_0402_10V7K
1
1 2
FB=0.6Volt
PR508
4.7_1206_5%
FB
EN
PR516
<32,35,40,42> SUSP#
LX
SVIN
TP
PVIN
1.8VSP_LX
PC523
680P_0603_50V7K
PC502
22U_0805_6.3VAM
LX
NC
@ JUMP_43X79
PVIN
NC
10
1.8VSP_VIN
+3VALW
PL503
1UH_PH041H-1R0MS_3.8A_20%
1
2
PJ502
PR513
10K_0402_1%
4
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title

+1.5VP/+1.8VSP
Custom
Rev
1.0
Gx00-CR
Date:

D
Sheet
40
of
60
VID [0]
0
0
1
1
VID[1]
0
1
0
1
VCCSA Vout
0.9V
0.8V
0.725V
0.675V
PJ601
2
+VCCSAP
+VCCSA
JUMP_43X118
PR613
output voltage adjustable network
+V1.05S_VCCP
+VCCSA
0.005_1206_1%
SY8037BDCC_DFN12_3X3
PL601
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1
2
9
8
7
SVIN
LX
FB
PG
VOUT
VID1
EN
VID0
SA_PGOOD
PR601
100K_0402_5%
1
2
<32>
@
PR602
4.7_0603_5%
+3VS
5
2
@ PC605
680P_0402_50V7K
6
@ PR614
0_0402_5%
13
LX
+VCCSA_PHASE
+V1.05S_VCCP_PWRGOOD
<42>
PR603
0_0402_5%
PR608
1M_0402_5%
+VCCSAP
PC609
22U_0805_6.3V6M
1
2
10
PVIN
PC607
22U_0805_6.3V6M
1
2
PC602
68P_0402_50V8J
2
1FB_VCCSA_IC
LX
1 2
11
PVIN
JUMP_43X79
12
GND
2 +VCCSA_PWR_SRC
PC604
22U_0805_6.3V6M
1
2
PU601
2
PC601
22U_0805_6.3V6M
1
2
PC608
22U_0805_6.3V6M
1
2
PC603
22U_0805_6.3V6M
1
2
PJ602
+3VALW
@ PC606
.1U_0402_16V7K
H_VCCSA_VID0
PR604
1K_0402_5%
2
1
FB_VCCSA
<10>
The 1k PD on the VCCSA VIDs are empty.

These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.
PR605
1K_0402_5%
2
1
H_VCCSA_VID1
<10>
PR606
100_0402_1%
2
1
+VCCSA_SENSE
<10>
PR607
0_0402_5%
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
Date:
5

+VCCSAP
Size
C
Document Number
Rev
1.0
Gx00-CR
1
Sheet
41
of
60
PJ701
PR701
60.4K_0402_1%
1
2
11
DH_1.05VS_VCCP
10
DL_1.05VS_VCCP
DL
PC704
1000P_0402_50V7K
PR711
75K_0402_1%
2
1
10_0402_1%
PC708
1U_0603_10V6K
1
2
PC709
3
2
1
PGND
8
GND
7
TRIP
6
0.01UF_0402_25V7K
PQ702
S TR MDU1511RH 1N POWERDFN56-8
+5VALW
PR703
<9> VCCIO_SENSE
V5
COMP
VSNS
PC706
PC715
0.1U_0402_25V6
2
1
PC713
4.7U_0805_25V6-K
2
1
B+
PC714
+1.05VS_VCCPP
1
+
<9> VSSIO_SENSE_L
JUMP_43X118
PL701
1UH_PCMB104T-1R0MH_18A_20%
2
1
1000P_0603_50V7K
LX_1.05VS_VCCP
DH
GSNS
PR714
4.7_1206_5%
REFIN
12
0_0402_5%
PC712
10U_0805_25V6K
2
1
PC711
2200P_0402_50V7K
2
1
13
SW
TPS51219RTER_QFN16_3X3
+V1.05S_VCCP
BST
EN
MODE
PC703
0.01UF_0402_25V7K
14
1
1
VREF
PC707
0.1U_0603_25V7K
1
2
12K_0402_1%
PR712
2
PQ701
S TR MDU1516URH 1N POW ERDFN56-8
PR713
2.2_0603_5%
1
2
BST_1.05VS_VCCP
15
16
PGOOD
PAD
PU701
17
10.7K_0402_1%~N
PR704
2
1
PR705
2
PC702
0.1U_0402_25V6
2
1
PL702
HCB2012KF-121T50_0805
2
1
1.05VS_B+
3
2
1
100K_0402_1%
PR710
100K_0402_1%
2
1
2
PC701
.1U_0402_16V7K
2
PR706
+3VS
<41> +V1.05S_VCCP_PW RGOOD
PR702
JUMP_43X118
PJ703
2
1
2
1
+1.05VS_VCCPP
@
@ 10K_0402_1%
<32,35,40> SUSP#
330U_6.3V_M
2
B
+1.05VP
OCP min 20A
OVP min 1.24V
PR709
1
2
1
2
10_0402_1%
PC705
1000P_0402_50V7K
Compal Secret Data
2011/06/15
Issued Date
Deciphered Date
2012/07/11
5
Title

+1.05VS_VCCP
Size
Document Number
Custom
Rev
1.0
Gx00-CR
Date:
Sheet
1
42
of
60
PR955
1K_0402_1%
DROOP
PC937
1
2
1
PC922
2
0.22U_0603_25V7K
BST1_1
PR928
0_0402_5%
Option for
1 phase GFX
CSP2A
SW1 <44>
+5VS
3P: 73.2K
2P: 41.2K
PR935
0_0402_5%
Option for
2 phase CPU
3Phase: @
2Phase: install
6132_PWM
CSP3
PC924
2
.1U_0402_16V7K
PC931
SWN2 <44>
TSENSE
@
PR960
6.98K_0402_1%
PR945
SWN1 <44>
5.62K_0402_1%
2 PC936
220P_0402_50V7K
1 PR952 2NTC_PH201 1 PR953 2

75K_0402_1%
165K_0402_1%
PH903
2
@
PR961
6.98K_0402_1%
PR949
100K_0603_1%
1
2
SWN1
SWN2
3P: 1500p0.047U_0402_16V7K
CSREF
2P: 1200p
CSSUM
PC934
2
1000P_0402_50V7K
1_0402_5%
CSREF <44>
PC932
1000P_0402_50V7K
PR941
5.62K_0402_1%
2
PR917
2
CSREF
CSP2
PC927
0.047U_0402_16V7K
PUT COLSE
TO VCORE
Phase 1
Inductor
1_0402_5%
1
SW2 <44>
2Phase: @
1Phase: install
PR934 2
41.2K_0402_1%
2
1
+5VS
HG1 <44>
1
PR931 2
CSP1
CSREF
1000P_0402_50V7K
3P: 806
2P: 1K
PR916
2
1
PR915
2
CSP2A
CSP1A
TSENSEA
PAD
VSNA
VSPA
DIFFA
TRBSTA#
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
100K_0402_1%_TSM0B104F4251RZ
+5VS
SW1A <44>
PC920
1
2
2.2U_0603_10V7K
0_0402_5%
LG1 <44>
BST1
6132P_VCCP
3P: 21K
2P: 12.4K
3P: 2200p
2P: 3300p
PC919
2
0.22U_0603_25V7K
LG2 <44>
2
1 PR930
CSP1
CSP2
CSP3
3P: 3.65K
2P: 9.53K
3P: 23.7K
2P: 24.9K
LG1A <44>
1
1
PR9242 BST2_1
2.2_0603_5%
HG2 <44>
PR946 1
806_0402_1%
.1U_0402_16V7K
PC933
8.06K_0402_1%
3P: 348
2P: 1.21K
PR921
PC918
2 BSTA1_1
1
2
2.2_0603_5%
0.22U_0603_25V7K
2.2_0603_5%
PR943
PC929
2
1COMP_CPU1 2
1
6.04K_0402_1%
1500P_0402_50V7K
3P: 6.04K
2P: 4.32K
PR948
1
0.033U_0402_16V7K
PR944
PC930
1
2FB_CPU3 1
2
10_0402_1%
0.033U_0402_16V7K
PR947
1
2
FB_CPU2
CSCOMP
HG1A <44>
BST2
PH904
PUT COLSE
TO V_GT
HOT SPOT
PC928
1
2FB_CPU1 1
2
49.9_0402_1%
680P_0402_50V7K
BSTA1
22P_0402_50V8J
PR942
TRBST#
PC926
2
1
1 PR940 2
1K_0402_1%
3P: 330p
2P: 1000p
B
3P: 22p
2P: 10p
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
PC923
1000P_0402_50V7K
VSP
2P: 36K
1P: 26.1K
1
2
PR938
0_0402_5%
2
1
<9> VCCSENSE
VSN
PC935
1
2
PR936
0_0402_5%
2
1
<16,32> VGATE
<9> VSSSENSE
PR918
1
2
26.1K_0402_1%
TSENSE
PR933
10K_0402_5%
<32,36,37,6> H_PROCHOT#
SWN1A <44>
6132_PWMA
24.9K_0402_1%
@
PR932
75_0402_1%
PC921
PR929 1K_0402_1%
+3VS
PR913
5.6K_0402_1%
.1U_0402_16V7K
TRBST#
FB
COMP
IOUT
ILIM
DROOP
CSCOMP
CSSUM
CSREF
CSP3
CSP2
CSP1
TSNS
DRVEN
PWM
CPU_B+
+V1.05S_VCCP
PC914
2
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PR927
60.4K_0402_1%
1
VCC
PWMA
VDDBP
BSTA
VRDYA
HGA
EN
SWA
SDIO
LGA
ALERT#
BST2
SCLK
HG2
VBOOT NCP6132AMNR2G_QFN60_7X7
SW2
ROSC
LG2
VRMP
PVCC
VRHOT#
PGND
VRDY
LG1
VSN
SW1
VSP
HG1
DIFF
BST1
PR950
1
PR926
0_0402_5%
1VR_SVID_DAT1
0_0402_5%
PR925
1
2
10K_0402_1%
.1U_0402_16V7K
PC917
1
2
3
4
5
VR_SVID_DAT1
6
VR_SVID_ALRT#
VR_SVID_CLK7
8
VBOOT
9
ROSC_CPU
10
VRMP
11
H_PROCHOT#
12
VGATE
13
14
15
DIFF_CPU
2.2U_0603_10V7K
PR920
2
1VR_ON_CPU
<32> VR_ON
0.01U_0402_25V7K
<9> VR_SVID_DAT
<9> VR_SVID_ALRT#
<9> VR_SVID_CLK
PR923
1
2
54.9_0402_1%
PR922 2
130_0402_1%
PC916
.1U_0402_16V7K
CSP1A
PU901
6132_VCC
TRBST#
FB_CPU
COMP_CPU
IMVP_IMON
IMON
IMON
1
2 ILIM_CPU
PR939 12.4K_0402_1%
DROOP
CSCOMP
1
PR919 2
2_0603_5%
PC915
1
2
SWN1A
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
Switching Frequency = 450KHz

+5VS
PR912 2
PC911
1000P_0402_50V7K
1PR914
2
15.8K_0402_1%
CSCOMPA
DIFFA
TRBSTA#
FBA
COMPA
IMONA
ILIMA
DROOPA
+V1.05S_VCCP
TSENSEA
PC910
0.047U_0402_16V7K
CSREFA <44>
CSSUMA
2
PC912
1000P_0402_50V7K
PR954
0_0402_5%
2
1
<10> VSS_AXG_SENSE
2P: 1.65K
1P: 1K
63.4K_0603_1%
2P: 21.5K
1P: 15.8K
CSREFA
1000P_0402_50V7K
CSREFA
<10> VCC_AXG_SENSE
PC906
1
2
DROOPA
PR910 10P_0402_50V8J PC909

2 COMPA11
2
1K_0402_1%
PR907
165K_0402_1%
6.04K_0402_1% 2200P_0402_50V7K
PR937
0_0402_5%
2
1
CSCOMPA
PH902
100K_0402_1%_TSM0B104F4251RZ
PR906
220K_0402_5%_ERTJ0EV224J
NTC_PH203
200K_0402_1%
PR909 2
1K_0402_1%
200K_0402_1%
680P_0402_50V7K
FBA2
PC908
1
2
1
2
10_0402_1%
PC907
1
2
PR908
4700P_0402_25V7K
24.9K_0402_1%
2P: 24K
1P: 24.9K
10.7K_0402_1%
PC905
PUT COLSE
TO GT
Inductor
PH901
1.21K_0402_1%
FBA1
PR902 2
PR903
TRBSTA#
PC902
2
.1U_0402_16V7K
1 PR904 2
PR905
1
2
75K_0402_1%
2 PC901
680P_0402_50V7K
PC904
1
2
FBA3
PC903
1
2
PR901 2
1200P_0402_50V7K
10_0402_1%
470P_0402_50V7K
PR915,PR946=200K(setting 113 degreeC)

PR915,PR946=8.25K(setting 93 degreeC)
PR951
100K_0603_1%
PUT COLSE
TO VCORE
HOT SPOT
1
220K_0402_5%_ERTJ0EV224J
<32> IMVP_IMON
A
Compal Secret Data
Issued Date
2011/06/15
2012/07/11
Deciphered Date
Title

PWR-CPU_CORE
Custom
Date:
Rev
1.0
Gx00-CR
Sheet

1
43
of
60
PQ901
2
CSREF <43>
<43> LG2
3
2
1
PQ904
SWN1 <43>
@
PC948
PC944
0.1U_0402_25V6
2
1
V2N_CPU 2 PR959 1
10_0402_1%
CSREF
SWN2 <43>
@
PC949
10_0402_1%
PR957
4.7_1206_5%
@
SNUB_CPU2
2
3
2
1
PQ903
PR958
2
V1N_CPU
+VCC_CORE
PL903
S COIL 0.22UH +-20% PCMB104T-R22MS 35A
1
4
<43> SW2
1SNUB_CPU1
PC943
10U_0805_25V6K
2
1
PC942
10U_0805_25V6K
2
1
S TR MDU1516URH 1N POWERDFN56-8
PR956
4.7_1206_5%
<43> LG1
PQ902
<43> HG2
+ PC947
220U_25V_M
<43> SW1
CPU_B+
+VCC_CORE
PL902
3
2
1
PL901
HCB4532KF-800T90_1812
1
2
3
2
1
CPU_B+
B+
PC941
2200P_0402_25V7K
2
1
PC940
0.1U_0402_25V6
2
1
<43> HG1
PC939
10U_0805_25V6K
2
1
PC938
10U_0805_25V6K
2
1
CPU_B+
PC946
2200P_0402_25V7K
2
1
680P_0603_50V7K
680P_0603_50V7K
DC 35W CPU
VID1=1.05V
IccMax=53A
Icc_Dyn=43A
Icc_TDC=36A
R_LL=1.9m ohm
OCP~65A
QC 45W CPU
VID1=0.9V
IccMax=94A
Icc_Dyn=66A
Icc_TDC=52A
R_LL=1.9m ohm
OCP~110A
PC960
2200P_0402_25V7K
2
1
PC959
0.1U_0402_25V6
2
1
PC958
10U_0805_25V6K
2
1
PC957
10U_0805_25V6K
2
1
CPU_B+
<43> HG1A
+VCC_GFXCORE_AXG
<43> SW1A
PR967
4.7_1206_5%
@
3
2
1
PQ909
SNUB_GFX1
<43> LG1A
V1N_GFX
3
2
1
PL905
PQ907
PR971 1
CSREFA <43>
10_0402_1%
@
PC968
SWN1A <43>
680P_0603_50V7K
A
QC 45W GT2
VID1=1.23V
IccMax=46A
Icc_Dyn=37A
Icc_TDC=38A
R_LL=3.9m ohm
OCP~55A
DC 35W GT2
VID1=1.23V
IccMax=33A
Icc_Dyn=20.2A
Icc_TDC=21.5A
R_LL=3.9m ohm
OCP~40A
Compal Secret Data
Issued Date
2011/06/15
Deciphered Date
2012/07/11
Title
Date:
5

PWR-CPU_CORE
Size
C
Document Number
Rev
1.0
Gx00-CR
1
Sheet
44
of
60
+VCC_CORE
1
+VCC_CORE
1
PC1
10U_0805_6.3VAM
1
PC2
10U_0805_6.3VAM
1
PC3
10U_0805_6.3VAM
Below is 458544_CRV_PDDG_0.5 Table 5-8.
+VCC_GFXCORE_AXG
Socket Bottom
5 x 22 F (0805)
5 x (0805) no-stuff
sites
Socket Top
7 x 22 F (0805)
2 x (0805) no-stuff
sites
1
PC4
10U_0805_6.3VAM
PC5
10U_0805_6.3VAM
+VCC_GFXCORE_AXG
1
PC10
10U_0805_6.3VAM
+VCC_CORE
+
PC64
22U_0805_6.3V6M
1
+
PC67
330U_D2_2V_Y
1
PC63
22U_0805_6.3V6M
PC66
330U_D2_2V_Y
PC56
22U_0805_6.3V6M
PC53
22U_0805_6.3V6M
2
1
PC52
22U_0805_6.3V6M
PC33
22U_0805_6.3V6M
PC32
22U_0805_6.3V6M
PC51
22U_0805_6.3V6M
PC31
22U_0805_6.3V6M
1
PC62
22U_0805_6.3V6M
PC30
22U_0805_6.3V6M
PC48
22U_0805_6.3V6M
PC61
22U_0805_6.3V6M
1
PC47
22U_0805_6.3V6M
PC50
22U_0805_6.3V6M
PC29
22U_0805_6.3V6M
1
PC46
22U_0805_6.3V6M
+V1.05S_VCCP
PC59
330U_D2_2V_Y
1
PC45
22U_0805_6.3V6M
PC58
330U_D2_2V_Y
1
PC44
22U_0805_6.3V6M
+V1.05S_VCCP
PC28
22U_0805_6.3V6M
PC43
22U_0805_6.3V6M
PC24
22U_0805_6.3V6M
PC42
22U_0805_6.3V6M
PC23
22U_0805_6.3V6M
PC41
22U_0805_6.3V6M
1
PC40
22U_0805_6.3V6M
PC22
22U_0805_6.3V6M
1
PC39
22U_0805_6.3V6M
PC21
22U_0805_6.3V6M
PC38
22U_0805_6.3V6M
PC20
22U_0805_6.3V6M
PC36
22U_0805_6.3V6M
PC27
22U_0805_6.3V6M
PC19
22U_0805_6.3V6M
1
PC9
10U_0805_6.3VAM
PC18
22U_0805_6.3V6M
1
PC8
10U_0805_6.3VAM
PC17
22U_0805_6.3V6M
1
PC7
10U_0805_6.3VAM
PC15
22U_0805_6.3V6M
1
PC6
10U_0805_6.3VAM
PC13
22U_0805_6.3V6M
@
PC71
22U_0805_6.3V6M
@
PC72
22U_0805_6.3V6M
1
+
PC74
330U_D2_2V_Y
1
+
PC78
330U_D2_2V_Y
PC73
330U_D2_2V_Y
PC77
330U_D2_2V_Y
PC76
330U_D2_2V_Y
+VCC_CORE
2@
Compal Secret Data
2011/06/15
Issued Date
Deciphered Date
2012/07/11
5
Title

PWR - PROCESSOR DECOUPLING
Size
Document Number
Rev
1.0
LA-9632P
Date:
Sheet
1
45
of
60
VIWGP/R HW PIR List
Jufn
Qbhf
NPEJGJDBUJPO!MJTU
QVSQPTF
Q/57
Bee!QS213-QD219-QD21:!
Gps!BEQ`JE!qjo!efufdu
Q/58
Bee!QS336-QS338-QS339-QR317-QR318-QR319
Gps!qspufdu!bebqufs!gvodujpo
Q/5:
Bee!QS521-QD544
Gps!4WBMXQ06WBMXQ!tfrvfodf
Q/5:
Bee!QD545-QD546-QD547-QD548
Gps!FNJ!tpmvujpo
Q/5:
Bee!QD543!boe!dibohf!QM515!gspn!2/6vI!up!4/4vI!
Gps!jnqspwf!pvuqvu!wpmubhf!sjqqmf
Q/61
Dibohf!QS613!gspn!5:/:l!up!75/:l
Gps!,1/86WTQ!tfrvfodf
Q/62
Bee!QD748!
Gps!,1/:6WHTQ!tfrvfodf
Q/65
Dibohf!QD:18-QS:23-QS:38-QD:39
Gps!DQV!Usbotjfou!!Dpnqfotbujpo
FWU!UP!EWU
:
21
22
23
C
24
25
26
27
28
29
2:
31
32
33
B
34
35
36
2011/06/15
Issued Date
Compal Secret Data
Deciphered Date
2012/07/11
Title
Custom
PIR (PWR)
Rev
C38-G series Chief River Schematic1.0
Date:
Sheet

1
46
of
60
COMPAL CONFIDENTIAL
10
A1
EC
PQ2
PCH_RSMRST#_R
EC_ON
A4
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
PM_SLP_SUS#
B6
11
H_CPUPWRGD
PLT_RST#
12
16
CPU
SYSON
SYSON#
V
V
PU702
+V1.05S
PU602
+V1.05S_VCCP
SA_PGOOD
(DIS)
U38
+5VS
8b
8a
Q8
+1.5VS
PU701
+0.75VS
8a
(DIS)
U39
+3VS
13
VR_ON
SVID
DGPU_PWR_EN
PU601
+VCC_SA
+1.5V
PU501
SUSP#,SUSP
13
DGPU_PWROK
ON/OFF
PBTN_OUT#
VGATE
14
B7
15
SYS_PWROK
PM_DRAM_PWRGD
PCH
A5
51ON#
V V
B3
C
PCH_PWROK
B+
10
B4
B2
B1
B7
+5VALW
V V
+3VALW
PU401
A5
B+
BATT
+3V_PCH
+5V_PCH
B5
PU301
A3
A2
VV
VIN
V V
BATT
MODE
PCH_PWROK
AC
MODE
MODEL NAME: Power Sequence Block Diagram

LA-9631P
PCB NAME:
REVISION:
2011/07/13
DATE:
DGPU
SVID
PU901
+VCC_CORE
14 VGATE
Issued Date
Compal Secret Data
2011/06/15
2012/07/11
Deciphered Date
Title
Power sequence
Rev
1.0
LA-9632P
Date:
Sheet

1
47
of
60
VIWGP/R HW PIR List
Jufn
Qbhf
NPEJGJDBUJPO!MJTU
QVSQPTF
Q/47
Dibohf!D837-!D838!up!3/3oG
Gps!Tfrvfodf
Q/37
Bee!S516
Gps!Joufm!Dpncp!Dbse
Q/36
Efmfuf!SQ2:/!Bee!SQ37-!SQ38
Cfdbvtf!NF!npejgz!NJD!mpdbujpo
Q/25
Bee!S517-!S518-!S519-!S51:
Sftfswf!gps!jnqspwfnfou!gbdupsz!qspdfttft
Q/43
Bee!FD`TQJ`TP-!FD`TQJ`TJ-!FD`TQJ`DML-!FD`TQJ`DT$!up!FD
Q/43
Bee!QDI`QXS`FO!up!FD!Qjo/218
Q/43
Sftfswf!S521
Sftfswf!Qvmm.ijhi!gps!HQJP
Q/633
Dibohf!gppuqsjou!pg!KDQV2-!V5
Gps!Mfopwp!svmf
Q/32
Bee!R32-!S51-!D348-!S336-!D354
Sftfswf!gps!qpxfs!dpotvnqujpo
21
Q/35
Bee!S522-!S523-!D522-!D523
Sftfswf!gps!FNJ
22
Q/43
Bee!BEQ`76!up!FD!Qjo/32
Gps!bebqufs!qspufdujpo
23
Q/43
Bee!BEQ`:1!up!FD!Qjo/79
24
Q/43
Bee!BEQ`246!up!FD!Qjo/96
25
Q/43
Dibohf!FD`GBO`QXN!gspn!FD!Qjo/45!up!FD!Qjo/37
Gps!dpnnpo!eftjho
26
Q/43
Dibohf!OPWP$!gspn!FD!Qjo/37!up!FD!Qjo/45
Gps!dpnnpo!eftjho
27
Q/43
Bee!BEQ`JE!up!FD!Qjo/77
Gps!bebqufs
28
Q/43
Dibohf!QDI`FOCLM!gspn!FD!Qjo/84!up!FD!Qjo/87
Gps!dpnnpo!eftjho
29
Q/43
Dibohf!JNWQ`JNPO!gspn!FD!Qjo/87!up!FD!Qjo/84
Gps!dpnnpo!eftjho
2:
Q/43
Bee!WHBUF!up!FD!Qjo/85
Sftfswf!gps!tfrvfodf
31
Q/43
Bee!TZT`QXSPL!up!FD!Qjo/97
Sftfswf!gps!tfrvfodf
32
Q/43
Dibohf!FD`UT`PO$!gspn!FD!Qjo/96!up!FD!Qjo/:8
Gps!dpnnpo!eftjho
33
Q/43
Dibohf!EHQV`QXS`FO!gspn!FD!Qjo/218!up!FD!Qjo/234
Gps!dpnnpo!eftjho
34
Q/43
Dibohf!TVTDML!gspn!FD!Qjo/234!up!FD!Qjo/233
Gps!dpnnpo!eftjho
FWU!UP!EWU
Issued Date
Compal Secret Data
2011/06/15
2012/07/11
Deciphered Date
Title
HW-PIR1
Date:
Rev
1.0
LA-9632P
Sheet

1
48
of
60
VIWGP/R HW PIR List
Jufn
Qbhf
NPEJGJDBUJPO!MJTU
QVSQPTF
Q/41
Efmfuf!S527-!Bee!K:
Op!offe![fsp!PEE!Gvodujpo
Q/37
Sftfswf!S619
Gps!mfblbhf!dvssfou!jttvf!pg!Buifspt!XMBO
Q/34
Bee!S61:
qspufdu!CLPGG$!ebnbhf
Q/43
Sftfswf!S527
Sftfswf!,4WMQ!qpxfs!sbjm!up!FD!
Q/43
Dibohf!FD`STU$!qpxfs!sbjm!up!,4W`FD
Vtjoh!qpxfs!sbjm!xijdi!uif!tbnf!xjui!FD/
Q/43
Dibohf!FD`TNC`DL2!'!FD`TNC`EB2!qpxfs!sbjm!up!,4W`FD
Vtjoh!qpxfs!sbjm!xijdi!uif!tbnf!xjui!FD/
Q/25
Dibohf!V6!gspn!5NC!up!9NC!SPN
Gpmmpx!dpnnpo!eftjho
Q/25
Efmfuf!S377-!S332-!V7
Ju!jt!gps!3NC!SPN-!xf!epo(u!offe!ju
Q/42
Sftfswf!sftjtubodf!up!,4WMQ!boe!,4WBMX/
Gps!Tqfblfs!Opjtf!jo!T6
Q/43
Sftfswf!sftjtubodf!jo!FD!gps!tibsf!SPN/
Gpmmpx!dpnnpo!eftjho
Q/52
Sftfswf!,W2/16T`WDDQ`QXSHPPE!pg!,W/16T`WDDQ!up!dpoofdu!up!TB`QHPPE
Gps!Dfmfspo!DQV
EWU!UP!QWU
Issued Date
Compal Secret Data
2011/06/15
2012/07/11
Deciphered Date
Title
HW-PIR2
Date:
Rev
1.0
LA-9632P
Sheet

1
49
of
60

Lenovo G400 LA-9632P

Caricato da

Informazioni sul documento

Descrizione originale:

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

Lenovo G400 LA-9632P

Caricato da

Copyright:

Formati disponibili

A

G400/G500 UMA M/B Schematics Document

Compal Electronics, Inc.

Compal Secret Data

Wednesday, February 27, 2013

USB30 Port 0,1

USB20 Port 11 page 28

PCIe Mini Card

Int. MIC Conn.

Int. Speaker Conn.

Audio Combo Jacks

Compal Secret Data

Compal Electronics, Inc.

Wednesday, February 27, 2013

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

Board ID / SKU ID Table for AD channel

USB Port Table

PCH SM Bus address

AMD-GPU SM Bus address

1010 000x A0h

Internal thermal sensor 0100 0001 41h

1010 010x A4h

BOM Structure Table

USB 2.0 Port

USB Port (Right Side USB-BD)

Compal Electronics, Inc.

Compal Secret Data

Wednesday, February 27, 2013

Compal Electronics, Inc.

Compal Secret Data

VGA Notes List

Wednesday, February 27, 2013

eDP_COMPIO and ICOMPO signals

PCI EXPRESS* - GRAPHICS

PEG_ICOMPI and RCOMPO signals should be

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane #

Compal Secret Data

Compal Electronics, Inc.

Wednesday, February 27, 2013

DDR3 Compensation Signals

JTAG & BPM

Buffered reset to CPU

Compal Secret Data

Compal Electronics, Inc.

Wednesday, February 27, 2013

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY B

Compal Secret Data

Eiffel used 0.01u

Compal Electronics, Inc.

Wednesday, February 27, 2013

CFG Straps for Processor

Interl request AH26 short GND

1: Normal Operation; Lane #

1 : Disabled; No Physical Display Port

Display Port Presence Strap

PEG Static Lane Reversal - CFG2 is for the 16x

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB