Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
ISSN: 2278-0181
Vol. 3 Issue 2, February - 2014
IJE
RT
I.
INTRODUCTION
IJERTV3IS20685
II.
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MBIST ALGORITHMS:
A.
-r0, w1
-r1, w0
IJERTV3IS20685
r0, w1
r1, w 0
r0
Test length
Fault Coverage
March C
11n
March C-
10n
March C+
14n
AF,SAF,TF,CFin,and CFid
MATS
4n
AF,SAF
MATS+
5n
AF,SAF
Marching
14n
AF,SAF,TF
MATS++
6n
March A
15n
March Y
8n
March B
17n
m Name
1/0
IJE
RT
A. Basic Architecture
The proposed MBISR Scheme is flexible. There are 60 normal
words and 4 Normal-Redundant words. When the BISR is
used, the Normal-Redundant words are accessed as normal
ones. Otherwise, the Normal-Redundant words can only be
accessed when there are faults in normal words. In this case,
the SRAM can only offer capacity of 60 words to users. This
should be referred in SRAM manual in details.
This kind of selectable redundancy architecture can save area
and increase efficiency. After BISR is applied, other modules
in SRAM can remain unchanged. Thus the selectable
redundancy wont bring any problem to SRAM compiler.
Repair is a popular technique for memory yield improvement.
The MBISR flow is shown Figure 1.
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Built-in Self-Test
Reconfiguration
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IJERTV3IS20685
D. BISR Flow:
Each fault address can be stored only once into FaultA-Mem. March C- has 6 steps. In another word, the addresses
will be read 5 times in one test. Some faulty addresses can be
detected in more than one step. Take Stuck-at-0 fault for
example, it can be detected in both 3rd and 5th steps. But the
fault address shouldnt be stored twice. So we propose an
efficient method to solve the problem in BIAA module. Below
figure shows the flows of storing fault addresses. BIST detects
whether the current address is faulty. If it is, BIAA checks
whether the Fault-A-Mem overflows. If not, the current fault
address should be compared with those already stored in
Fault-A-Mem. Only if the faulty address isnt equal to any
address in Fault-A-Mem, it can be stored. To simplify the
comparison, write a redundant address into Fault-A-Mem as
background. In this case, the fault address can be compared
with all the data stored in Fault-A-Mem no matter how many
fault addresses have been stored
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IJE
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IV.
th
EXPERIMENTAL RESULTS
E. BISR Features:
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:
:
:
:
:
:
:
:
:
12
1
1
1
1
1
1
1
1
Final Results
IJE
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RTL
Top
Level
Output
File
Name:
top_sample.ngr
Top Level Output File Name : top sample
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
: 19
Cell Usage:
# BELS
: 540
#
INV
: 2
#
LUT2
: 20
#
LUT3
: 155
#
LUT3_D
: 4
#
LUT3_L
: 4
#
LUT4
: 198
#
LUT4_D
: 13
#
LUT4_L
: 15
#
MUXF5
: 84
#
MUXF6
: 28
#
MUXF7
: 12
#
MUXF8
: 4
#
VCC
: 1
# FlipFlops/Latches
: 319
#
FDCE
: 4
#
FDE
: 311
#
LDE
: 4
# Clock Buffers
: 1
#
BUFGP
: 1
# IO Buffers
: 18
#
IBUF
: 15
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:
:
3
2
1
1
1
75
5
61
9
1
1
19
1
1
1
OBUF
: 3
V CONCLUSION
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REFERENCES
[1]
[2]
[3]
[4]
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[5]
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