Microelectronic Circuit Design

Fourth Edition
Solutions to Exercises
CHAPTER 7
Page 370

(a )

20
A
K p = 40x106 = 800 2
V
1

( b) V
(c) V

20
A
mA
| Kn = 100x106 = 2000 2 = 2.00 2
V
V
1

TN

= 0.6 + 0.5 2.5 + 0.6 0.6 = 1.09 V

TP

= 0.6 0.75 2.5 + 0.7 0.7 = 1.31 V

Page 372
(a ) For vI = 1 V , VGSN VTN = 1 0.6 = 0.4V and VGSP VTP = 1.5 + 0.6 = 0.9V
MN is saturated for vO 0.4 V. MP is in the triode region for vO 1.6 V. 1.6 V v O 2.5 V

(b) M
(c) M

is saturated for vO 1.6 V. 0.4 V v O 1.6 V

is in the triode region for vO 0.4 V. MP is saturated for v O 1.6 V. 0 v O 0.4 V

W
10 25
Kn W
=
= 2.5 =
L P K p L N
1 1

R. C. Jaeger and T. N. Blalock

08/12/10

Page 373
Both transistors are saturated since VGS = VDS .
K
2
2
Kn
VGSN VTN ) = p (VGSP VTP )
(
2
2

Kn = K p

VGSN = VGSP vI = VDD v I v I =

VTN = VTP

VDD
2

10K p
2
K
2
VGSN VTN ) = p (VGSP VTP ) 10 (VGSN VTN ) = VGSP + VTP
(
2
2
10 (vI 0.6) = 4 v I 0.6 vI = 1.273 V
Kp
2
10K p
2
VGSN VTN ) =
VGSP VTP ) (VGSN VTN ) = 10 (VGSP + VTP )
(
(
2
2
vI 0.6 = 10 (4 v I 0.6) vI = 2.37 V

Page 375
W
Kn
L N Kn
KR =
=
= 2.5
W
Kp
K p
L P
VIH =

2KR (VDD VTN + VTP )

VOL

(V

DD

KRVTN + VTP )

K 1
( K 1) 1+ 3K
2(2.5)(2.5 0.6 0.6) (2.5 2.5(0.6) 0.6)
=

= 1.22V
2.5 1
(2.5 1) 1+ 3(2.5)
( K + 1)V V K V V = (2.5 + 1)1.22 2.5 2.5(0.6) + 0.6 = 0.174V
=
2K
2(2.5)
2 K (V V + V ) (V K V + V )
=

K 1
( K 1) K + 3
2 2.5 (2.5 0.6 0.6) (2.5 2.5(0.6) 0.6)
=

= 0.902V
2.5 1
(2.5 1) 2.5 + 3
( K + 1)V + V K V V = (2.5 + 1)0.902 + 2.5 2.5(0.6) + 0.6 = 2.38V
=
R

VIH

IH

DD

R TN

TP

VIL

DD

VIL
VOH

NM H = VOH

TN

TP

DD

DD

TP

IL

R TN

R TN

TP

2
2
VIH = 2.38 1.22 = 1.16 V | NM L = VIL VOL = 0.902 0.174 = 0.728 V

R. C. Jaeger and T. N. Blalock

08/12/10

Page 376
Symmetrical Inverter : P = 1.2RonnC = 1.2

1012 F

( )

2 104 (2.5 0.6)

= 3.16 ns

Page 377

Symmetrical Inverter : Ronn =

P
109 s
=
= 167
1.2C 1.2 5x1012 F

W
1
1
31.5
=
=
=
'
4
1
L N Ronn Kn (VGS VTN ) 167 10 (2.5 0.6)

( )

W
W
78.8
= 2.5 =
1
L P
L N

Page 379

The inverters need to be increased in size by a factor of

W
3.77 4.22
= 1.12
=
1
L N
1

280ps
= 1.12.
250ps

W
9.43 10.6
= 1.12
=
1
L P
1

W
3.77 3.3 0.75 3.43
=

=
1
L N 1 3.3 0.5

W 9.43 3.3 0.75 8.59

| =

=
1
L P 1 3.3 0.5

Page 380

PHL = 2.4RonnC =

2.4C
2.4C
C
=
= 1.26
Kn
Kn (VGS VTN ) Kn (2.5 0.6)

PLH = 2.4RonpC =

2.4C
2.4C
C
=
= 1.26
Kp
K p (VGS VTN ) K p (2.5 0.6)

PHL = 2.4RonnC =

2.4C
2.4C
C
=
= 0.94
Kn
Kn (VGS VTN ) Kn (3.3 0.75)

PLH = 2.4RonpC =

2.4C
2.4C
C
=
= 0.94
Kp
K p (VGS VTN ) K p (3.3 0.75)

Page 381
The inverter in Fig. 7.12 is a symmetrical design, so the maximum current occurs
2
V
10-4 2
for vO = v I = DD . Both transistors are saturated : iDN =
(1.25 0.6) = 42.3 A
2
2 1
-5
2
4x10 5
Checking : iDP =
(1.25 0.6) = 42.3 A
2 1
3

R. C. Jaeger and T. N. Blalock

08/12/10

Page 382
2
10
CVDD
(a) PDP 5 =

F (2.5V )

2
10
CVDD
b
PDP

=
()
5

F (3.3V )

10
CV 2
(c) PDP 5DD =

F (1.8V )

13

13

13

5
2

5
5

= 0.13 pJ = 130 fJ
= 0.22 pJ = 220 fJ

= 0.065 pJ = 65 fJ

Page 388
Remove the NMOS and PMOS transistors connected to input E, and ground the source of
the NMOS transistor connected to input D. The are now 4 NMOS transistors in series, and
W
2 8
W
5
| =
= 4 =
L N
1 1
L P 1
Page 392
There are two NMOS transistors in series in the AB and CD NMOS paths, and three PMOS
transistors in the ACE and BDE PMOS paths. Therefore :
W
2 4
W
W
5 15
2
= 2 =
|
=
| = 3 =

L N ABCD
1 1
L N E 1
L P
1 1
Page 396
(a) The logic network for F = AB + C is

B
C
A

2
P = CVDD
f = 50x1012 F (5V ) 10 7 Hz = 12.5 mW

R. C. Jaeger and T. N. Blalock

08/12/10

Page 400
1

50 pF 2
=
= 31.6
50 fF

P = 31.6 o + 31.6 o = 63.2 o

z = e ln z

( )

| z ln z = e ln z

1
ln z

=e

50 pF 7
=
= 2.683
50 fF
1, 2.68 , 2.6832 = 7.20, 2.6833 = 19.3, 2.6834 = 51.8, 2.6835 = 139, 2.6836 = 373
A6 = (1+ 3.16 + 10 + 31.6 + 100 + 316) Ao = 462 Ao
A7 = (1+ 2.68 + 7.20 + 19.3 + 51.8 + 139 + 373) Ao = 594 Ao

Page 401
From the figure, 10/1 devices give a maximum Ron of 4 k. The W/L ratios must be 4 times
W 10 40
larger in order to reduce the maximum Ron to 1 k. = 4 =
L 1 1

R. C. Jaeger and T. N. Blalock

08/12/10