Pass-Transistor Logic

Inputs

B
Switch

Out

Network

Out
B

N transistors
No static consumption

NMOS-only switch
C=5V

C=5V
A=5V

A=5V
B

M2

Mn

CL

M1

VB does not pull up to 5V, but 5V - VTN

Threshold voltage loss causes
static power consumption

Solution 1: Transmission Gate

C
A

C
A

B
C

C
C=5V
A=5V

B
CL
C=0V

Resistance of Transmission Gate

30000.0
Rn
(W/L)p =(W/L)n =
1.8/1.2

R (Ohm)

20000.0
Rp

10000.0

0.0
0.0

Req

1.0

2.0

3.0
Vout

4.0

5.0

Pass-Transistor Based Multiplexer

S

VDD
S

VDD

M2
F

S
M1
B

GND
In
1

In
2

Transmission Gate XOR

M2

F
M1
B
B

M3/M4

Delay in Transmission Gate Networks

5

5
V1

In

Vi

Vi-1
C

Vn-1

Vi+1
C

Vn

(a)
Req

Req

V1

In

Req

Vi

Vn-1

Vi+1

Req

(b)
m
Req

Req

Req

Req

Req

Req

In
C

CC

(c)

CC

Vn

Elmore Delay (Chapter 8)

Vin

R1
C1

R2

Ri-1

C2

i-1

Ci-1

Ri

Ci

RN

CN

Assume All internal nodes are precharged to VDD and a step voltage is
applied at the input Vin
N
N =

Ri C j = C i R j
i=1 j=i
i=1 j=1

Delay Optimization

Transmission Gate Full Adder

P
VDD
A

VDD
Ci

Ci

P
B

A
P

Ci

S Sum Generation

Ci
B

P
A
P

Setup

VDD
Co Carry Generation

Ci
A

VDD

(2) NMOS Only Logic: Level Restoring Transistor

VDD
Level Restorer

VDD

Mr
B
A

Mn

M2
X

Out
M1

Advantage: Full Swing

Disadvantage: More Complex, Larger Capacitance
Other approaches: reduced threshold NMOS

Level Restoring Transistor

3.0

without
without

3.0

with
VB

1.0
-1.00

with

5.0

VX

Vout (V)

5.0

t (nsec)

1.0
4

(a) Output node

6 -1.00

t (nsec)

(b) Intermediate node X

Solution 3: Single Transistor Pass Gate with VT=0

VDD
0V

5V

VDD

0V

VDD

Out

5V

WATCH OUT FOR LEAKAGE CURRENTS

Complimentary Pass Transistor Logic

A
A
B
B
A
A
B
B

Pass-Transistor

(a)
Inverse
Pass-Transistor
Network

Network

F=AB

F=A+B

F=AB
AND/NAND

F=A

(b)

F=A+B

B
OR/NOR

A
EXOR/NEXOR

F=A

4 Input NAND in CPL