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  • CS6211 Set1

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    Sampath Kumar
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    The document outlines the exam for a digital laboratory course at Anna University in Chennai, India. The exam consists of 20 questions worth 100 marks each, involving designing and implementing various digital logic circuits using basic logic gates and integrated circuits. Circuits include half/full adders, half/full subtractors, code converters, comparators, parity generators/checkers, multiplexers/demultiplexers, counters, and shift registers. Students are also tasked with simulating some of the circuits using VHDL or Verilog HDL.

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    CS6211 SET1

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    The document outlines the exam for a digital laboratory course at Anna University in Chennai, India. The exam consists of 20 questions worth 100 marks each, involving designing and implementing various digital logic circuits using basic logic gates and integrated circuits. Circuits include half/full adders, half/full subtractors, code converters, comparators, parity generators/checkers, multiplexers/demultiplexers, counters, and shift registers. Students are also tasked with simulating some of the circuits using VHDL or Verilog HDL.

    Copyright:

    © All Rights Reserved
    Scarica in formato PDF, TXT o leggi online su Scribd
    Segnala contenuti inappropriati
    28 visualizzazioni2 pagine

    CS6211 Set1

    Caricato da

    Sampath Kumar
    The document outlines the exam for a digital laboratory course at Anna University in Chennai, India. The exam consists of 20 questions worth 100 marks each, involving designing and implementing various digital logic circuits using basic logic gates and integrated circuits. Circuits include half/full adders, half/full subtractors, code converters, comparators, parity generators/checkers, multiplexers/demultiplexers, counters, and shift registers. Students are also tasked with simulating some of the circuits using VHDL or Verilog HDL.

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    © All Rights Reserved
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    ANNA UNIVERSITY : CHENNAI 600 025


    B.E/B.Tech DEGREE EXAMINATIONS, APRIL/MAY 2014
    Regulations R-2013
    Second Semester
    (B.E. Computer Science and Engineering)
    CS6211 - Digital Laboratory

    Time: 3 Hours

    Maximum Marks: 100

    1. Verify Boolean Theorems using basic logic gates.

    (100)

    2. Design and implement half adder and full adder combinational circuits using basic
    logic gates.
    (100)

    3. Design and implement half subtractor and full subtractor combinational circuits using
    basic logic gates.
    (100)

    4. Design and implement 4-bit Binary to gray code converter and Gray to binary code
    converter using basic logic gates.
    (100)

    5. Design and implement 4-bit BCD to excess-3 code converter and Excess-3 to BCD
    code converter using basic logic gates.
    (100)

    6. Design and implement 4-bit adder and subtractor using IC 7483.

    (100)

    7. Design and implement an 8-bit magnitude comparator using IC 7485.

    (100)

    8. Design and implement an 8-bit odd parity generator / checker using IC 74180. (100)

    2/2

    9. Design and implement an 8-bit even parity generator / checker using IC 74180. (100)

    10. Design and implement multiplexer and demultiplexer using logic gates.

    (100)

    11. Design and verify 4-bit asynchronous (ripple) counter.

    (100)

    12. Design and implement 3-bit synchronous up/down counter.

    (100)

    13. Design and implement 4-bit shift register under serial-in serial-out mode.

    (100)

    14. Design and implement 4-bit shift register under serial-in parallel-out mode.

    (100)

    15. Design and implement 4-bit shift register under parallel-in serial-out mode.

    (100)

    16. Design and implement 4-bit shift register under parallel-in parallel-out mode. (100)

    17. Perform the simulation of half adder and full adder combinational circuits using
    VHDL or Verilog HDL.
    (100)

    18. Perform the simulation of half subtractor and full subtractor combinational circuits
    using VHDL or Verilog HDL.
    (100)

    19. Perform the simulation of 4-bit asynchronous (ripple) counter using VHDL or
    Verilog HDL.
    (100)

    20. Perform the simulation of 4-bit Synchronous up/down counter using VHDL or
    Verilog HDL.
    (100)

    ************

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