library ieee;

use ieee.std_logic_1164.all;
entity G_XOR is
port(
A
:
B
:
X
:
);
end entity G_XOR;

in
in
out

std_logic;
std_logic;
std_logic

architecture behaviour of G_XOR is

signal A_Neg
:
std_logic;
signal B_Neg
:
std_logic;
signal And_1
:
std_logic;
signal And_2
:
std_logic;
begin
A_Neg <= not(A);
B_Neg <= not(B);
And_1
<= A_Neg and B;
And_2
<= B_Neg and A;
X
<= And_1 or And_2;
end architecture behaviour;