Xilinx

VLSI LAB RECORD
SEMESTER 2
1. LED BLINK
AIM
To design led blink using Xilinx and simulate it in a FPGA kit.
SOFTWARE USED
Xilinx
PROCEDURE
1. The verilog module source code and test bench for led blink circuit are written.
2. It is implemented in Xilinx and simulated in VLSI trainer kit.
3. The output was viewed and verified.
PROGRAM
module led(a,clk,b);
input a,clk;
output reg b;
always@(posedge clk)
if(a==1)
begin
b=1;
end
else
b=0;
endmodule
TEST BENCH
module led_test_v;
reg a;
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wire b;
led uut (
.a(a),
.b(b)
);
Initial
begin
a = 1'b0;
#100;
a=1'b1;
#100;
end
endmodule
RESULT
A Led blink circuit was designed and output was observed in both Xilinx and trainer kit.
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VLSI LAB RECORD
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2. SEVEN SEGMENT DISPLAY
AIM
To design seven segment display using Xilinx and simulate it in a FPGA kit.
SOFTWARE USED
Xilinx
PROCEDURE
1. The verilog module source code for seven segment display is written.
PROGRAM
module sevenseg(clk,a,b,c);
input clk;
output reg [7:0]a,b,c;
begin
a=8'b01110111;
b=8'b00110000;
c=8'b01110111;
end
endmodule
RESULT
A Seven segment display was designed and output was observed in vlsi trainer kit.
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3. THERMOMETER DECODER
AIM
To design a thermometer decoder circuit using Xilinx and simulate it in a FPGA kit.
SOFTWARE USED
Xilinx
PROCEDURE
1. The verilog module source code for thermometer decoder circuit is written.
PROGRAM
module thermometerdecoder(a, clk, b );
input [1:0]a ;
input clk ;
output reg [3:0]b ;
always @(posedge clk)
begin
if (a==2'b11)
b=4'b1111;
else if(a==2'b10)
b=4'b0111;
else if(a==2'b01)
b=4'b0011;
else
b=4'b0001;
end
endmodule
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RESULT
A thermometer decoder circuit was designed and output was observed in vlsi trainer kit.
Dept. of ECE, FISAT
VLSI LAB RECORD
SEMESTER 2
4. DECODER
AIM
To design a decoder using Xilinx and simulate in FPGA kit.
SOFTWARE USED
Xilinx
PROCEDURE
1. The verilog module source code and test bench for decoder circuit are written.
PROGRAM
module decoder1(a,b,y0,y1,y2,y3);
input a,b;
output reg y0,y1,y2,y3;
always@(a,b)
begin
if(a==0&&b==0)
begin
y0=1;
y1=0;
y2=0;
y3=0;
end
if(a==0&&b==1)
begin
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y0=0;
y1=1;
y2=0;
y3=0;
end
if(a==1&&b==0)
begin
y0=0;
y1=0;
y2=1;
y3=0;
end
if(a==1&&b==1)
begin
y0=0;
y1=0;
y2=0;
y3=1;
end
end
endmodule
TEST BENCH
module decoder_test_v;
// Inputs
reg a;
reg b;
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// Outputs
wire y0;
wire y1;
wire y2;
wire y3;
// Instantiate the Unit Under Test (UUT)

decoder1 uut (
.a(a),
.b(b),
.y0(y0),
.y1(y1),
.y2(y2),
.y3(y3)
);
initial begin
a = 0;
b = 0;
#100;
a = 0;
b = 1;
#100;
a = 1;
b = 0;
#100;
a = 1;
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b = 1;
#100;
end
endmodule
RESULT
A decoder circuit was designed and output was observed in both Xilinx and trainer kit.
5. CLOCK DIVIDER
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VLSI LAB RECORD
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AIM
To design a clock divider using Xilinx and simulate it in a FPGA kit.
SOFTWARE USED
Xilinx
PROCEDURE
1. The verilog module source code for clock divider circuit is written.
PROGRAM
module clkdivider(clk,out);
input clk;
reg [24:0]count=25'b0;
output reg [1:0]out;
begin
count =count+1;
out[0]=count[24];
out[1]=count[23];
end
endmodule
RESULT
A clock divider circuit was designed and output was observed in vlsi trainer kit.
6. COUNTER
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AIM
To design a counter using Xilinx.
SOFTWARE USED
Xilinx
PROCEDURE
1. The verilog module source code for counter circuit was generated using IP core
generator ,its top module and test bench were written.
2. It is implemented in Xilinx.
IP CORE PROGRAM
`timescale 1 ns/1 ps
module counter2ip (
clk, q
);
input clk;
output [15 : 0] q;
// synopsys translate_off
wire \BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carryxortop_rt_2 ;
wire \BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carrychaingen[1].carrymux_rt_3 ;
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wire \BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carrychaingen[8].carrymux_rt_10;
wire \BU2/N0 ;
wire \BU2/q_thresh1 ;
wire NLW_VCC_P_UNCONNECTED;
wire NLW_GND_G_UNCONNECTED;
wire [15 : 0] NlwRenamedSig_OI_q;
wire [0 : 0] \BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum ;
wire [14 : 0] \BU2/U0/the_addsub/no_pipelining.the_addsub/carry_simple ;
wire [15 : 0] \BU2/U0/q_next ;
assign
q[15] = NlwRenamedSig_OI_q[15],
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q[0] = NlwRenamedSig_OI_q[0];
VCC VCC_0 (
.P(NLW_VCC_P_UNCONNECTED)
);
GND GND_1 (
.G(NLW_GND_G_UNCONNECTED)
);
INV \BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum_not00001_INV_0 (
.I(NlwRenamedSig_OI_q[0]),
.O(\BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum [0])
);
defparam \BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carryxortop_rt .INIT = 4'h2;
LUT1 \BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carryxortop_rt (
.I0(NlwRenamedSig_OI_q[15]),
.O(\BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carryxortop_rt_2 )
);
defparam \BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carrychaingen[1].carrymux_rt
.INIT = 4'h2;
LUT1 \BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carrychaingen[1].carrymux_rt (
.O(\BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carrychaingen[1].carrymux_rt_3 )
);
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.INIT = 4'h2;
);
.INIT = 4'h2;
);
.INIT = 4'h2;
);
.INIT = 4'h2;
);
.INIT = 4'h2;
);
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.INIT = 4'h2;
);
.INIT = 4'h2;
);
.INIT = 4'h2;
);
defparam
\BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carrychaingen[10].carrymux_rt .INIT =
4'h2;
);
defparam
4'h2;
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);
defparam
4'h2;
);
defparam
4'h2;
);
defparam
4'h2;
);
MUXCY \BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carrymux0 (
.CI(\BU2/N0 ),
.DI(\BU2/q_thresh1 ),
.S(\BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum [0]),
.O(\BU2/U0/the_addsub/no_pipelining.the_addsub/carry_simple [0])
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);
XORCY \BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carryxor0 (
.CI(\BU2/N0 ),
.LI(\BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum [0]),
.O(\BU2/U0/q_next [0])
);
XORCY \BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carryxortop (
.CI(\BU2/U0/the_addsub/no_pipelining.the_addsub/carry_simple [14]),
.LI(\BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carryxortop_rt_2 ),
.O(\BU2/U0/q_next [15])
);
MUXCY \BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carrychaingen[1].carrymux (
.DI(\BU2/N0 ),
.S(\BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carrychaingen[1].carrymux_rt_3 ),
);
XORCY \BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carrychaingen[1].carryxor (
.LI(\BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carrychaingen[1].carrymux_rt_3 ),
);
.DI(\BU2/N0 ),
);
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);
.DI(\BU2/N0 ),
);
);
.DI(\BU2/N0 ),
);
);
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.DI(\BU2/N0 ),
);
);
.DI(\BU2/N0 ),
);
);
.DI(\BU2/N0 ),
);
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);
.DI(\BU2/N0 ),
);
);
.DI(\BU2/N0 ),
);
);
MUXCY \BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carrychaingen[10].carrymux
(
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.DI(\BU2/N0 ),
);
.LI(\BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carrychaingen[10].carrymux_rt_12
),
.O(\BU2/U0/q_next [10])
);
.DI(\BU2/N0 ),
);
),
.O(\BU2/U0/q_next [11])
);
(
.DI(\BU2/N0 ),
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);
),
.O(\BU2/U0/q_next [12])
);
(
.DI(\BU2/N0 ),
);
),
.O(\BU2/U0/q_next [13])
);
(
.DI(\BU2/N0 ),
);
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),
.O(\BU2/U0/q_next [14])
);
defparam \BU2/U0/q_i_0 .INIT = 1'b0;
FDE \BU2/U0/q_i_0 (
.C(clk),
.CE(\BU2/q_thresh1 ),
.D(\BU2/U0/q_next [0]),
.Q(NlwRenamedSig_OI_q[0])
);
FDE \BU2/U0/q_i_1 (
.C(clk),
.D(\BU2/U0/q_next [1]),
);
FDE \BU2/U0/q_i_2 (
.C(clk),
.D(\BU2/U0/q_next [2]),
);
FDE \BU2/U0/q_i_3 (
.C(clk),
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.D(\BU2/U0/q_next [3]),
);
FDE \BU2/U0/q_i_4 (
.C(clk),
.D(\BU2/U0/q_next [4]),
);
FDE \BU2/U0/q_i_5 (
.C(clk),
.D(\BU2/U0/q_next [5]),
);
FDE \BU2/U0/q_i_6 (
.C(clk),
.D(\BU2/U0/q_next [6]),
);
FDE \BU2/U0/q_i_7 (
.C(clk),
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.D(\BU2/U0/q_next [7]),
);
FDE \BU2/U0/q_i_8 (
.C(clk),
.D(\BU2/U0/q_next [8]),
);
FDE \BU2/U0/q_i_9 (
.C(clk),
.D(\BU2/U0/q_next [9]),
);
FDE \BU2/U0/q_i_10 (
.C(clk),
.D(\BU2/U0/q_next [10]),
);
.C(clk),
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.D(\BU2/U0/q_next [11]),
);
.C(clk),
.D(\BU2/U0/q_next [12]),
);
.C(clk),
.D(\BU2/U0/q_next [13]),
);
.C(clk),
.D(\BU2/U0/q_next [14]),
);
.C(clk),
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.D(\BU2/U0/q_next [15]),
);
VCC \BU2/XST_VCC (
.P(\BU2/q_thresh1 )
);
GND \BU2/XST_GND (
.G(\BU2/N0 )
);
// synopsys translate_on
endmodule
// synopsys translate_off
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;

parameter TOC_WIDTH = 0;
wire GSR;
wire GTS;
wire PRLD;
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reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals -------------wire JTAG_TDO_GLBL;

wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_USER_TDO1_GLBL = 1'bz;

assign (weak1, weak0) GSR = GSR_int;

assign (weak1, weak0) GTS = GTS_int;
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assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
// synopsys translate_on
TOP MODULE
module counter2iptop(clk,q);
input clk;
output wire [15:0] q;
counter2ip uut(clk,q);
endmodule
TEST BENCH
module counter2ip_test_v;
// Inputs
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reg clk;
// Outputs
wire [15:0] q;
counter2iptop uut (
.clk(clk),
.q(q));
always #10 clk=~clk;
initial begin
// Initialize Inputs
clk = 0;
end
endmodule
OUTPUT
RESULT
A counter circuit was designed and output was observed in xilinx.
7. CLOCK MULTIPLIER
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AIM
To design a clock multiplier using Xilinx.
SOFTWARE USED
Xilinx
PROCEDURE
1. The verilog module source code for clock multiplier circuit was generated using IP core
IP CORE PROGRAM
`timescale 1ns / 1ps
module clkm_ip(CLKIN_IN,
CLKFX_OUT,
CLKFX180_OUT,
CLKIN_IBUFG_OUT);
input CLKIN_IN;
output CLKFX_OUT;
output CLKFX180_OUT;
output CLKIN_IBUFG_OUT;
wire CLKFX_BUF;
wire CLKFX180_BUF;
wire CLKIN_IBUFG;
wire GND_BIT;
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assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
.O(CLKFX_OUT));
BUFG CLKFX180_BUFG_INST (.I(CLKFX180_BUF),
.O(CLKFX180_OUT));
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
DCM_SP DCM_SP_INST (.CLKFB(GND_BIT),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(),
.CLKFX(CLKFX_BUF),
.CLKFX180(CLKFX180_BUF),
.CLK0(),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(),
.PSDONE(),
.STATUS());
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defparam DCM_SP_INST.CLK_FEEDBACK = "NONE";

defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0;
defparam DCM_SP_INST.CLKFX_DIVIDE = 4;
defparam DCM_SP_INST.CLKFX_MULTIPLY = 2;
defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam DCM_SP_INST.CLKIN_PERIOD = 100.000;
defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE";
defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW";
defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW";
defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE";
defparam DCM_SP_INST.FACTORY_JF = 16'hC080;
defparam DCM_SP_INST.PHASE_SHIFT = 0;
defparam DCM_SP_INST.STARTUP_WAIT = "FALSE";
endmodule
TOP MODULE
module clkm_top(CLKIN_IN,
CLKFX_OUT,
CLKFX180_OUT,
CLKIN_IBUFG_OUT);
input CLKIN_IN;
output CLKFX_OUT;
clkm_ip dut(CLKIN_IN,
CLKFX_OUT,
CLKFX180_OUT,
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CLKIN_IBUFG_OUT);
endmodule
TEST BENCH
module clkm_test_v;
// Inputs
reg CLKIN_IN;
// Outputs
wire CLKFX_OUT;
wire CLKFX180_OUT;
wire CLKIN_IBUFG_OUT;
clkm_top uut (
.CLKIN_IN(CLKIN_IN),
.CLKFX_OUT(CLKFX_OUT),
.CLKFX180_OUT(CLKFX180_OUT),
.CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT)
);
initial begin
CLKIN_IN = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always begin #50; CLKIN_IN=~CLKIN_IN; end
endmodule
BLACK BOX
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OUTPUT
RESULT
A clock multiplier circuit was designed and output was observed in xilinx.
8. CLOCK DIVIDER
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AIM
To design a clock multiplier using Xilinx.
SOFTWARE USED
Xilinx
PROCEDURE
1. The verilog module source code for clock divider circuit was generated using IP core
generator, its top module and test bench were written.
IP CORE PROGRAM
`timescale 1ns / 1ps
module clkdiv_ip(CLKIN_IN,
CLKFX_OUT,
CLKFX180_OUT,
CLKIN_IBUFG_OUT);
input CLKIN_IN;
output CLKFX_OUT;
wire CLKFX_BUF;
wire CLKFX180_BUF;
wire CLKIN_IBUFG;
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wire GND_BIT;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
.O(CLKFX_OUT));
BUFG CLKFX180_BUFG_INST (.I(CLKFX180_BUF),
.O(CLKFX180_OUT));
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
DCM_SP DCM_SP_INST (.CLKFB(GND_BIT),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(),
.CLKFX(CLKFX_BUF),
.CLKFX180(CLKFX180_BUF),
.CLK0(),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(),
.PSDONE(),
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.STATUS());
defparam DCM_SP_INST.CLK_FEEDBACK = "NONE";
defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0;
defparam DCM_SP_INST.CLKFX_DIVIDE = 4;
defparam DCM_SP_INST.CLKFX_MULTIPLY = 2;
defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam DCM_SP_INST.CLKIN_PERIOD = 100.000;
defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE";
defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW";
defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW";
defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE";
defparam DCM_SP_INST.FACTORY_JF = 16'hC080;
defparam DCM_SP_INST.PHASE_SHIFT = 0;
defparam DCM_SP_INST.STARTUP_WAIT = "FALSE";
endmodule
TOP MODULE
module clkdiv_top(CLKIN_IN,
CLKFX_OUT,
CLKFX180_OUT,
CLKIN_IBUFG_OUT);
input CLKIN_IN;
output CLKFX_OUT;
clkdiv_ip dut(CLKIN_IN,
CLKFX_OUT,
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CLKFX180_OUT,
CLKIN_IBUFG_OUT);
endmodule
TEST BENCH
module clkdiv_test_v;
// Inputs
reg CLKIN_IN;
// Outputs
wire CLKFX_OUT;
wire CLKFX180_OUT;
wire CLKIN_IBUFG_OUT;
clkm_top uut (
.CLKIN_IN(CLKIN_IN),
.CLKFX_OUT(CLKFX_OUT),
.CLKFX180_OUT(CLKFX180_OUT),
.CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT)
);
initial begin
CLKIN_IN = 0;
#100;
end
always begin #50; CLKIN_IN=~CLKIN_IN; end
endmodule
BLACK BOX
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OUTPUT
RESULT
A clock divider circuit was designed and output was observed in xilinx.
9. FIFO
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SEMESTER 2
AIM
To design FIFO using Xilinx.
SOFTWARE USED
Xilinx
PROCEDURE
1. The verilog module source code for FIFO circuit was generated using IP core
generator, its top module and test bench were written.
IP CORE PROGRAM
`timescale 1ns/1ps
module fifog(
clk,
din,
rd_en,
rst,
wr_en,
dout,
empty,
full);
input clk;
input [15 : 0] din;
input rd_en;
input rst;
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input wr_en;
output [15 : 0] dout;
output empty;
output full;
// synthesis translate_off
FIFO_GENERATOR_V3_3 #(
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(16),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(16),
.C_ENABLE_RLOCS(0),
.C_FAMILY("spartan3"),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
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.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("1kx18"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1022),
.C_PROG_FULL_THRESH_NEGATE_VAL(1021),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(100),
.C_RD_PNTR_WIDTH(10),
.C_UNDERFLOW_LOW(0),
.C_USE_ECC(0),
.C_USE_FIFO16_FLAGS(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
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.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_FREQ(100),
.C_WR_PNTR_WIDTH(10),
.C_WR_RESPONSE_LATENCY(1))
inst (
.CLK(clk),
.DIN(din),
.RD_EN(rd_en),
.RST(rst),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_CLK(),
.RD_RST(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.ALMOST_EMPTY(),
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.ALMOST_FULL(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.PROG_FULL(),
.VALID(),
.RD_DATA_COUNT(),
.UNDERFLOW(),
.WR_ACK(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of fifog is "black_box"
endmodule
TOP MODULE
module fifo_top(
clk,
din,
rd_en,
rst,
wr_en,
dout,
empty,
full);
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input clk;
input [15 : 0] din;
input rd_en;
input rst;
input wr_en;
output [15 : 0] dout;
output empty;
output full;
fifog m(clk,din,rd_en,rst,wr_en,dout,empty,full);
endmodule
TEST BENCH
module fifo_test_v;
// Inputs
reg clk;
reg [15:0] din;
reg rd_en;
reg rst;
reg wr_en;
// Outputs
wire [15:0] dout;
wire empty;
wire full;
fifo_top uut (
.clk(clk),
.din(din),
.rd_en(rd_en),
.rst(rst),
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.wr_en(wr_en),
.dout(dout),
.empty(empty),
.full(full)
);
initial begin
clk = 0;
din = 0;
rd_en = 0;
rst = 0;
wr_en = 0;
#100;
wr_en =1;
din=1'b1;
#100;
din=3'b101;
#100;
din=5'b11111;
#100;
din=1'b0;
#100;
din=2'b10;
#100;
din=4'b1011;
#100;
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wr_en=0;
#150;
rd_en=1;
end
always begin
#50;
clk = ~clk;
end
endmodule
BLACK BOX
OUTPUT
Dept. of ECE, FISAT
48
VLSI LAB RECORD
SEMESTER 2
RESULT
A FIFO circuit was designed and output was observed in xilinx.
10. SRAM
Dept. of ECE, FISAT
49
VLSI LAB RECORD
SEMESTER 2
AIM
To design a SRAM using Xilinx.
SOFTWARE USED
Xilinx
PROCEDURE
1. The verilog module source code for SRAM circuit was generated using IP core
IP CORE PROGRAM
`timescale 1ns/1ps
module sram_ip(addra, addrb, clka, clkb, dina, dinb, douta, doutb, wea, web);
input [3 : 0] addra;
input [3 : 0] addrb;
input clka;
input clkb;
input [15 : 0] dina;
input [15 : 0] dinb;
output [15 : 0] douta;
output [15 : 0] doutb;
input wea;
input web;
// synthesis translate_off
BLKMEMDP_V6_3 #(
.c_addra_width(4),
.c_addrb_width(4),
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.c_default_data("0"),
.c_depth_a(16),
.c_depth_b(16),
.c_enable_rlocs(0),
.c_has_default_data(1),
.c_has_dina(1),
.c_has_dinb(1),
.c_has_douta(1),
.c_has_doutb(1),
.c_has_ena(0),
.c_has_enb(0),
.c_has_limit_data_pitch(0),
.c_has_nda(0),
.c_has_ndb(0),
.c_has_rdya(0),
.c_has_rdyb(0),
.c_has_rfda(0),
.c_has_rfdb(0),
.c_has_sinita(0),
.c_has_sinitb(0),
.c_has_wea(1),
.c_has_web(1),
.c_limit_data_pitch(18),
.c_mem_init_file("mif_file_16_1"),
.c_pipe_stages_a(0),
.c_pipe_stages_b(0),
.c_reg_inputsa(0),
.c_reg_inputsb(0),
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.c_sim_collision_check("NONE"),
.c_sinita_value("0"),
.c_sinitb_value("0"),
.c_width_a(16),
.c_width_b(16),
.c_write_modea(0),
.c_write_modeb(0),
.c_ybottom_addr("0"),
.c_yclka_is_rising(1),
.c_yclkb_is_rising(1),
.c_yena_is_high(1),
.c_yenb_is_high(1),
.c_yhierarchy("hierarchy1"),
.c_ymake_bmm(0),
.c_yprimitive_type("16kx1"),
.c_ysinita_is_high(1),
.c_ysinitb_is_high(1),
.c_ytop_addr("1024"),
.c_yuse_single_primitive(0),
.c_ywea_is_high(1),
.c_yweb_is_high(1),
.c_yydisable_warnings(1))
inst (
.ADDRA(addra),
.ADDRB(addrb),
.CLKA(clka),
.CLKB(clkb),
.DINA(dina),
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.DINB(dinb),
.DOUTA(douta),
.DOUTB(doutb),
.WEA(wea),
.WEB(web),
.ENA(),
.ENB(),
.NDA(),
.NDB(),
.RFDA(),
.RFDB(),
.RDYA(),
.RDYB(),
.SINITA(),
.SINITB());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of sram_ip is "black_box"
Endmodule
TOP MODULE
module sram_top(addra, addrb, clka, clkb, dina, dinb, douta, doutb, wea, web);
input [3 : 0] addra;
input [3 : 0] addrb;
input clka;
input clkb;
input [15 : 0] dina;
input [15 : 0] dinb;
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output [15 : 0] douta;

output [15 : 0] doutb;
input wea;
input web;
sram_ip dut(addra, addrb, clka, clkb, dina, dinb, douta, doutb, wea, web);
endmodule
TEST BENCH
module sram_test_v;
// Inputs
reg [3:0] addra;
reg [3:0] addrb;
reg clka;
reg clkb;
reg [15:0] dina;
reg [15:0] dinb;
reg wea;
reg web;
// Outputs
wire [15:0] douta;
wire [15:0] doutb;
sram_top uut (
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
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.douta(douta),
.doutb(doutb),
.wea(wea),
.web(web)
);
initial begin
addra = 0;
addrb = 0;
clka = 0;
clkb = 0;
dina = 0;
dinb = 0;
wea = 0;
web = 0;
#100;
wea=1;
#100;
addra=4'b1001;
dina = 5'b10101;
#100;
addra=4'b1010;
dina = 5'b11111;
#100;
wea = 0;
#100;
addra=4'b1001;
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#100;
addra=4'b1010;
end
always begin
#50
clka=~clka;
end
endmodule
BLACK BOX
OUTPUT
Dept. of ECE, FISAT
56
VLSI LAB RECORD
SEMESTER 2
RESULT
A SRAM circuit was designed and output was observed in xilinx.
Dept. of ECE, FISAT
57

Xilinx

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VLSI LAB RECORD

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2. SEVEN SEGMENT DISPLAY

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// Instantiate the Unit Under Test (UUT)

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module glbl ();

parameter ROC_WIDTH = 100000;

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//-------- JTAG Globals -------------wire JTAG_TDO_GLBL;

reg JTAG_USER_TDO1_GLBL = 1'bz;

assign (weak1, weak0) GSR = GSR_int;

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assign (weak1, weak0) PRLD = PRLD_int;

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defparam DCM_SP_INST.CLK_FEEDBACK = "NONE";

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