MULTISTAGE AMPLIFIER

Cascaded Connection
Output of one stage is connected
to the input of another
stage.
Amplifier 1
Vin 1

Gain = AV1

Amplifier 2
Vo 1

Gain = AV2

Overall gain AV = VO2 / Vin 1 = Av1 AV2

Vo 2

Cascaded BJT Amplifier

VCC

VCC

RC2

RC1

Q2

R1

C2

Q1
Vi

C1

R2
RE1

Cs1
Gain AV2 =

Gain AV1 =

R3

V1o

V1o
RC1 || RL1

V1
re1

R4

V2o

RE2

V2 o
RC 2 || RL 2

V1o
re 2

Cs2

VCC

VCC

R
R C1 || R 3 || R 4 ||R 2 * re2
A v1
R
R
R
C2
r
e1
Q
A
C1

C2

V1O

R C2R || R L
r
A

e2
R
v2
R
C
re2 C
Qv2
1

C1
Vi

R2

V2O

C2

E2

E1

s2

s1

RC1
b

R1

Ib1

1Ib1

Ic1
V1O

R3

Ib2

RC2
V2O

2Ib2

Overall
gain,
A v A * A v2
r
R
Vi

i1

R4

ri2
v1
e

RL

Input Impedance, Zi R 1 || R 2 || 2 * re2

Output Impedance, Z o R C2 || ro
RC1
b

Vi

R1

Ib1

ri1

R2
e

1Ib1

RC2
Ic1
V1O

R3
R4

Ib2

ri2
e

V2O

2Ib2

RL

20V

+20V

1.5K

2.2K

V1O

15K

Q1
10f

Vi

4.7K

V2O

22K

Q2
C2

6.8K

1K

1K
20f

Draw the (i) Input and (ii) output voltage waveshape for
different values of Vi (a) 25V (b) 1mV (c) X mV, where X is
last two digits of your Roll No.

20f

Cascaded
FET
Amplifier
Overall gain
AV1AV2 = (-g
m1RD1)(-gm2RD2)
VDD
VDD

AV2 = -gm2RD2

AV1 = -gm1RD1
RD1

Vi

Q1
Ci

RG1

Rs1

Vo1

RD2
Q2

C2

RG2

Rs2

Cs1

Impedance
ZO = RD2
Input ImpedanceOutput
Zin = R
G1

Vo2

Cs2

Darlington Connection
Two transistors are connected in
such a way that emitter current of
one is fed to the base of another, so
that the overall current gain is the
product of their individual current
gains.
It is also known as superbeta
transistor

Overall = 1 2

IB1

IE1 = (1+ 1 ) IB1

Q1
IE1

IE2 = (1+ 2 ) IB2

IE2 = (1+ 2 ) (1+ 1 ) IB1
IE2 2 1 IB1

Q2
IE2

2N999 npn darlington transistor

VBE = 1.8V at IC = 100mA
D = 4000

at IC = 10mA

D = 7000

at IC = 100mA

Maximum D = 70,000

at IC = 100mA

DC bias of Darlington Circuit

VCC VBE
IB
RB D RE
I E D 1 I B D I B
VE I E RE

VCC
IC

RB
IB

D
VBE

IE

RE

VB VE VBE

DC bias of Darlington Circuit

18 1.6
IB
2.56 A
3.3M 8000 * 390R
3.3M

I E 8000 * 2.56. 20.48mA

VE 20.48mA * 390R 8V
VB 8 1.6 9.6V

18V
IC

IB

D
IE

VBE
VBE = 1.6V
D =8000

390R

AC analysis of Darlington Circuit

VCC

Ii
IC

RB

Vi
Ci

Ib

Vi

RB

DIb

ri

Ib

RE

D = 8000
Ci

VBE = 1.6V
IE

RE

VO

VO

AC Input Impedance of Darlington

Circuit
Ii

Ib

Vi

RB

D =8000
ri = 5K

D I b

ri
RE

VO

Vi Vo
Ib
ri
Vo I b D I b RE

Vi I b ri 1 D RE I b ri D RE

Vi
Z i RB || ri D RE
Ii

AC Current Gain of Darlington Circuit

Ii

Ib

Vi

RB

Io
Ai
Ii

D I b

ri

Io Ib D Ib D Ib

VO

RE

Io

Vi I b ri D RE

RB
Ib
Ii
ri D RE RB

Io Io Ib
RB
Ai
D
Ii Ib Ii
RB D RE

RB
Ib
Ii
D RE RB

AC Output Impedance of Darlington Circuit

ri
V
O

Ib
VS

ZO

RE
D I b

RB

ri

Vo Vo
Io
D Ib
RE ri

IO

RE
D I b

RL

Vo
Zo
Io

VO

Vo
Vo Vo
Io
D
RE ri
ri

Vo
1
Zo

1 1 D
Io

RE ri ri

AC Voltage gain of Darlington Circuit

ri
V
AV

Ib
VS

Vi I b ri Vo

RE
D I b

VO

Vi

Vo I b D I b RE

Vo RE D RE I b
Vi I b ri RE D RE

Vi
RE D RE
Vo
ri RE D RE

Vo
RE D RE
AV

1
Vi ri RE D RE

Summery of Darlington connection

Super beta transistor, D = 1 2.
High current gain, can amplify very small signal.
Increased input impedance.
Reduced output impedance.
Unity voltage gain.

CMOS Circuit

Complementary Metal Oxide

Semiconductor Field Effect Transistor
VDD = 5V
VGS = -5V

VDD = 5V
VGS = 0V

pMOS

pMOS

G
D
D

i
Vi =V0V

nMOS

Vo = 0V

Vi = 5V

CMOS is used
as
S
V = 0V
an inverter
GS

VV
o =
o 5V

nMOS
S

VGS = 5V

Current source
VDD =10V
= 24V

IL = 10A
RL = 2
1
IS = 10A

IDSS= 8 mA
VP = - 5 V

VGS
I D I DSS 1
VP

IL = 8 mA
RRLL=1K
= 5K
2K
VO = ?

BJT Current source

VCC

RL
IC
VB

R1
R2

IE

RE

-VEE

R1
VEE
VB
R1 R2

VE VB 0.7
VE (VEE )
IE
IC
RE

BJT - Zener Current source

VCC

RL
IC
VB

R1

VZ

IE

RE

-VEE

VZ VBE
IE
IC
RE

Current
Mirror
Circuit
V
CC

IX

RX

IL

IC

Q1

2IB

IB

IB
V1

IE
IL1

RL1

RL

IE
IE
IB

IC I E

IC

I X IC 2I B

Q2

2I E
I X IE

IE

2
I E I E
I X