Full adder:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fa is
Port ( a : in bit;
b : in bit;
cin : in bit;
s : out bit;
cout : out bit);
end fa;
architecture Behavioral of fa is
begin
s<= (a xor b) xor cin;
cout <= (a and b) or (cin and (a xor b));
end Behavioral;
Adder4bit:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity adder4bit is
Port ( ci : in bit;
a0 : in bit;
a1 : in bit;
a2 : in bit;
a3 : in bit;
b0 : in bit;
b1 : in bit;
b2 : in bit;
b3 : in bit;
q0 : out bit;
q1 : out bit;
q2 : out bit;
q3 : out bit;
c : out bit);
end adder4bit;

architecture Behav of adder4bit is

signal s1,s2,s3 : bit ;
component fa is
port
(
a : in bit;
b : in bit;
cin : in bit;
s : out bit;
cout : out bit);

end component;
begin
M0: fa port map
(
a => a0,
b => b0,
cin => ci,
s => q0,
cout => s1
);
M1: fa port map
(
a => a1,
b => b1,
cin => s1,
s => q1,
cout => s2
);
M2: fa port map
(
a => a2,
b => b2,
cin => s2,
s => q2,
cout => s3
);
M4: fa port map
(
a => a3,
b => b3,
cin => s3,
s => q3,
cout => c
);
end Behav;

Test_4bit:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY test_4bit IS
END test_4bit;
ARCHITECTURE behavior OF test_4bit IS
COMPONENT adder4bit
PORT(
ci : IN bit;
a0 : IN bit;
a1 : IN bit;
a2 : IN bit;
a3 : IN bit;

b0 : IN bit;
b1 : IN bit;
b2 : IN bit;
b3 : IN bit;
q0 : OUT bit;
q1 : OUT bit;
q2 : OUT bit;
q3 : OUT bit;
c : OUT bit
);
END COMPONENT;
--Inputs
signal ci : bit := '0';
signal a0 : bit := '0';
signal a1 : bit := '0';
signal a2 : bit := '0';
signal a3 : bit := '0';
signal b0 : bit := '0';
signal b1 : bit := '0';
signal b2 : bit := '0';
signal b3 : bit := '0';
--Outputs
signal q0 : bit;
signal q1 : bit;
signal q2 : bit;
signal q3 : bit;
signal c : bit;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
uut: adder4bit PORT MAP (
ci => ci,
a0 => a0,
a1 => a1,
a2 => a2,
a3 => a3,
b0 => b0,
b1 => b1,
b2 => b2,
b3 => b3,
q0 => q0,
q1 => q1,
q2 => q2,
q3 => q3,
c => c
);

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
ci <= '0';
a0 <='0';
a1<='0';
a2 <='0';
a3<='0';
b0 <='0';
b1<='0';
b2 <='0';
b3<='1';
wait for 100 ns;
ci <= '0';
a0 <='0';
a1<='0';
a2 <='1';
a3<='1';
b0 <='0';
b1<='0';
b2 <='0';
b3<='0';
wait for 100 ns;
ci <= '0';
a0 <='0';
a1<='0';
a2 <='0';
a3<='1';
b0 <='1';
b1<='0';
b2 <='0';
b3<='0';
wait for 100 ns;
ci <= '0';
a0 <='1';
a1<='1';
a2 <='1';
a3<='1';
b0 <='0';
b1<='0';
b2 <='0';
b3<='0';
wait for 100 ns;
wait;
end process;
END;
Output: