Unsigned Multiplication

module unsignmul(a, b,clk,temp,ans);

input [7:0]a;
input [7:0]b;
input clk;
output reg [20:0]ans;
output reg[20:0]temp;
integer i=0;
integer j=0;
always@( posedge clk)
begin
ans=20'b00000000000000000000;

for(i=0;i<=7;i=i+1)
begin
temp=20'b0000000000000000000;
for(j=0;j<=7;j=j+1)
begin
temp[j]=b[i] & a[j];
$display("a=%b,b=%b,temp=%b,ans=%b,i=%d,j=%d",a,b,temp,ans,i,j);
end
temp=temp<<i;
ans=ans+temp;

end
end

endmodule
 UNSIGNMUL Project Status
Project File: unsignmul.ise Current State: Synthesized
 Errors:
Module Name: unsignmul No Errors

 Warnings:
Target Device: xc3s500e-4ft256 255 Warnings

 Updated:
Product Version: ISE, 8.1i Thu 1. Oct 17:54:13 2009
 
Device Utilization Summary (estimated values)
Logic Utilization Used Available Utilization
Number of Slices 34 4656 0%
Number of 4 input LUTs 57 9312 0%
Number of bonded IOBs 59 190 31%
Number of GCLKs 1 24 4%