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VLSI MANUAL
STEPS OF EXECUTION
1. Source ams.cshrc file

2. Open pyxis using the command dmgr_ic

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3. File -> New -> Project

Enter Project Path
Path to Library. i.e browse for
/home/user/PDK/generic13

4. Click on Add Standard Libraries

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5. By selecting the Project Hierarchy -> Right Click -> New

Library

6. Select New Library -> Right Click on Project Navigator ->

New Schematic

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7. After Blank Schematic Window Opens , Add Instance ->

8. generic13/symbols pmos, nmos, resistance/capacitance

genericlib - vdd, vss, ground etc
sourcelib dc/ac/pulse voltage/current sources etc

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9. Schematic Diagram with appropriate Ports

10. Click on Save & Check.

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11. Add -> Generate Symbol -> Choose Shape

12. Customize Pinlist

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13 Save & Check the Generated Symbol

14 In the Project Navigator -> Right Click -> New Schematic

(For Test Circuit)

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15 Select the Schematic Instance

16 Finish the Test Circuit -> Save

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17 Enter Simulation Mode

18 New Design Configuration

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19 Choose Setup Environment

20 Viewer -> Select Start EZwave Automatically

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21 Setup Simulations -> Analysis -> Transient

22 Setup Simulations -> Analysis -> DC

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23 Choose DC Source from the Test Circuit

24 Setup Simulations -> Libraries -> Typical

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25 Unselect include_all

26 Setup Simulation -> Forces -> From Schematic -> Press

Ctrl & Choose Input and Output

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27 Setup Simulation -> Output -> (Choose Inputs and

Outputs) Add

28 Save -> Run

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29 Select Schematic & in Project Hierarchy -> Right Click ->

New -> Layout

30 Choose OK to launch Layout Editor

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31 Setup -> Toolbar -> SDL Toolbar

Pick and Place Components from SDL Toolbar

32 Pick and Place Ports from SDL Toolbar

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33 Setup -> Windows -> Object Editor

Add Device -> $gb_p ->psub, nwell for nmos, pmos

34 IRoute for connectivity using appropriate layers.

Add -> Text on Ports -> M1 -> OK

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35 Save the Layout

36 Tools -> Calibre DRC -> Run DRC

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37 Tools -> Calibre LVS -> Run LVS

38 Tick Mark and Smiley Indicates No LVS Errors

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39 Tools -> Calibre PEX -> Input -> Browse *.src.net

Input -> Netlist -> Enable Export from Schematic -> Run PEX

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INVERTER
Schematic

Symbol

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Test Circuit

Transient Analysis

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DC Analysis

AC Analysis

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Layout

DRC Report

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LVS Report

PEX Netlist
* File: schematic.pex.netlist
* Program "Calibre xRC"
* Version "v2012.4_25.21"
*
.global VDD VSS
.include "schematic.pex.netlist.pex"
.subckt schematic GND OUT IN
*
* IN IN
* OUT OUT
* GND GND
* VDD VDD
M2 N_OUT_M2_d N_IN_M2_g N_GND_M2_s N_GND_M2_b NMOS L=1.3e-07 W=2e-06
M1 N_OUT_M1_d N_IN_M1_g N_VDD_M1_s N_VDD_M1_b PMOS L=1.3e-07 W=2e-06
*
.include "schematic.pex.netlist.SCHEMATIC.pxi"
*
.ends
*
*

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COMMON DRAIN
Schematic

Symbol

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Test Circuit

Transient Analysis

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DC Analysis

Layout

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DRC Report

LVS Report

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PEX Netlist
* File: cd.pex.netlist
* Program "Calibre xRC"
* Version "v2012.4_25.21"
*
.global VDD VSS
.include "cd.pex.netlist.pex"
.subckt cd OUT IN GND
*
* GND GND
* IN IN
* VDD VDD
* OUT OUT
R1 N_OUT_R1_pos N_GND_R1_neg RNPOLYHI w=2e-06 l=1e-05
M1 N_VDD_M1_d N_IN_M1_g N_OUT_M1_s N_OUT_M1_b NMOS L=1.3e-07 W=2e-06
*
.include "cd.pex.netlist.CD.pxi"
*
.ends
*
*

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COMMON SOURCE
Schematic

Symbol

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Test Circuit

Transient Analysis

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DC Analysis

AC Analysis

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Layout

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DIFFERENTIAL AMPLIFIER
Schematic

Symbol

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Test Circuit

Transient Analysis

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DC Analysis

AC Analysis

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Layout

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OPERATIONAL AMPLIFIER
Schematic

Symbol

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Test Circuit

Transient Analysis

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DC Analysis

AC Analysis

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Layout

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R-2R DAC
Schematic

Symbol

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Test Circuit

Transient Analysis

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Layout

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