Allen and Holberg - CMOS Analog Circuit Design

SECTION 7 - COMPARATORS

Page VII.0-1

Allen and Holberg - CMOS Analog Circuit Design

Page VII.0-1

VII. COMPARATORS
Contents
VI.1
VI.2
VI.3
VI.4
VI.5

Comparators Models and Performance

Development of a CMOS Comparator
Design of a Two-Stage CMOS Comparator
Other Types of Comparators
Improvement in Comparator Performance
A. Hysteresis
B. Autozeroing
VI.6 High Speed Comparators
Organization
Chapter 10
D/A and A/D
Converters

Chapter 11
Analog Systems

SYSTEMS

Chapter 7
CMOS
Comparators

Chapter 8
Simple CMOS
OTA's

Chapter 9
High Performance
OTA's

COMPLEX

CIRCUITS
Chapter 5
CMOS
Subcircuits

Chapter 6
CMOS Amplifiers

SIMPLE

Chapter 2
CMOS
Technology

DEVICES

Chapter 3
CMOS Device
Modeling

Chapter 4 Device
Characterization

Allen and Holberg - CMOS Analog Circuit Design

Page VII.1-1

VII.1 - CHARACTERIZATION OF
COMPARATORS
What is a Comparator?
A comparator is a circuit which compares two analog signals and
outputs a binary signal based on the comparsion. (It can be an op amp
without frequency compensation.)
Characterization of Comparators
We shall characterize the comparator by the following aspects:
Resolving capability
Speed or propagation time delay
Maximum signal swing limits
Input offset voltage
Other Considerations
Noise
Power
Etc.

Allen and Holberg - CMOS Analog Circuit Design

Page VII.1-2

VOLTAGE COMPARATORS

Definition of a Comparator
VA
VB

VOUT
-

Noninverting
VOUT
VOH

VOUT =

V O H

V OL

when VA VB

VA - VB
when V A < V B

VOL

Inverting
VOUT

VOUT =

V O L

V OH

when VA VB

VOH

when V A V B

VA - VB
VOL

Allen and Holberg - CMOS Analog Circuit Design

Page VII.1-3

COMPARATOR PERFORMANCE

1. Speed or propagation time delay.

The amount of time between the time when VA - V B = 0 and the
output is 50% between initial and final value.
2. Resolving capability.
The input change necessary to cause the output to make a transition
between its two stable states.
3. Input common mode range.
The input voltage range over which the comparator can detect
V A = VB .
4. Output voltage swing (typically binary).
5. Input offset voltage.
The value of V OUT reflected back to the input when VA is physically
connected to V B.

Allen and Holberg - CMOS Analog Circuit Design

Page VII.1-4

APPROACHES TO THE DESIGN OF VOLTAGE

COMPARATORS
Open Loop
Use of a high-gain differential amplifier.
V OH - V O L
Gain =
resolution of the comparator
Regenerative
Use of positive feedback to detect small differences between two
voltages, VA and VB. I.e., sense amplifiers in digital memories.
Open Loop - Regenerative
Use of low gain, high speed comparator cascaded with a latch.
Results in comparators with very low propagation time delay.
Charge Balancing
Differential charging of a capacitor. Compatible with switched
capacitor circuit techniques.

Type

Offset Voltage
(Power supply)

Resolution

Speed (8 bit)

Open-loop

1-10 mV

300V (5V)

10 MHz

Regenerative
Charge
Balancing

0.1 mV

50V (5V)

50 MHz

0.1 mV

5mV (5V)

30 MHz

Allen and Holberg - CMOS Analog Circuit Design

Page VII.1-5

COMPARATOR MODELS - OPEN LOOP

Zero Order Model

VOUT
VOH

VP - VN

VOL

Model
VP
+

+
fo VP - VN

VN

fo( V P

V O H
- VN ) =
V OL

VO

for ( V P - V N ) 0

for ( V P - V N ) 0

Allen and Holberg - CMOS Analog Circuit Design

Page VII.1-6

COMPARATOR MODELS - CONT'D

First Order Model

Transfer Curve
VOUT
VOH
VIL

VP - VN

VIH
VOL

Model
VP
+

+
f1 VP - VN

VN

VO

V O H for ( V P - V N ) VIH
f1( V P - V N ) = AV( V P - V N ) f o r V I L ( V P - V N ) V I H
V OL for ( V P - V N ) VIL

Allen and Holberg - CMOS Analog Circuit Design

Page VII.1-7

COMPARATOR MODELS - CONT'D

First Order Model with Offset
Transfer Curve
VOUT
VOH

VOS
VIL

VP - VN

VIH
VOL
First Order Model with Offset
+-VOS
VP

V'P
+

+
f1 V'P - V'N
-

V'N

VN

Time Response of Noninverting, first order model

VOH
v = VOH + VOL
2

VOUT
VOL
VIH
VP - VN

VO

v = VIH + VIL
2

tP
VIL
Time

Allen and Holberg - CMOS Analog Circuit Design

Page VII.2-1

VII.2 - DEVELOPMENT OF A CMOS

COMPARATOR
SIMPLE INVERTING COMPARATOR
VDD
vN

M2
I2
IB
M1

VBIAS

vO

VSS
Fig. 7.2-1 Simple inverting comparator
VIN

VDD

vO

vN

VTRP

Fig. 7.2-2 DC transfer curve of a simple comparator

Low gain Poor resolution

VTRP = f V D D + process parameters

Allen and Holberg - CMOS Analog Circuit Design

Page VII.2-2

CALCULATION OF THE TRIP POINT, VTRP

vO

t.

VDD

VDD

vO = V IN + VT2

c
2a

t.

a
2s

VIN

M2
vO

VBIAS

M1

M1 sat.
M1 act.

VBIAS - VT1

VSS
Operating RegionsvDS1 v GS1 - VT

VSS
VSS

VIN
vN

VTRP

VDD

vO - VSS V BIAS - VSS - VT1

v O V BIAS - V T 1

vSD2 vSG2 - VT2

V DD - vO VDD - vIN - VT2

v O v I N + VT2

Trip PointAssume both M1 and M2 are saturated, solve and equate drain
currents for VTRP. Assume 0.
K N W1
2
iD1 = 2 L V BIAS - V SS - V T 1
1
K P W2
2
iD2 = 2 L V D D - v I N - VT2

iD1=iD2

vIN = VTRP = VDD- VT2 -

KN( W1/L1)
KP( W2/L2) ( V BIAS - V SS - V T 1)

W1
W2
I.e. V DD = -VSS = 5V, VBIAS = -2V and KN L = KP L
1
2
VTRP = 5-1-(-2+5-1) = 4-2 = 2V

Allen and Holberg - CMOS Analog Circuit Design

Page VII.2-3

COMPARATOR USING A DIFFERENTIAL AMPLIFIER

VDD

M3

M4
vO
M1

vP

M2

VBIAS

vN

M5

vO
VOH = VDD
VOH'
M1 & M2 in
saturation
VOL'
VOL
VSS
-1

+1

Gain is still low for a comparator

vP - vN
Av

Allen and Holberg - CMOS Analog Circuit Design

Page VII.2-4

DERIVATION OF OUTPUT SWING LIMITS

VDD

vP > vN

M3
I1
vP

M4
I2

M1

M2

vO
vN

1. Current in M1 increases and

current in M2 decreases.
2. Mirroring of M3-M4 will
cause vO to approach VDD .
3. VOH' = VDD - VDS4(sat)

ISS

VBIAS

VOH ' = VDD -

I4
4

VOH ' = VDD -

I5
Kp'( W4/L4)

M5
VSS

vP < vN

V O H ' = VD D -

I5
Kp'( W3/L3)

Assume vN is a fixed DC voltage

1. vO starts to decrease, M3-M4 mirror
is valid so that I1 = I2 = ISS/2 .
2. VOL ' = vN - VGS2 + VDS2
when M2 becomes non-sat. we have
VDS2(sat) = VGS2 - VT so that

4. Finally, vO V DD causing the

mirror M3-M4 to no longer be
valid and V OH V DD.
(I2 = I4 = 0 , I3 = I1 = I5)

V OL ' = v N - V T 2
3. For further decrease in vO, M2 is nonsat
and therefore the VGS2 can increase
allowing the sources of M1 and M2 to
fall(as v P falls).
4. Eventually M5 becomes non-sat and I5
starts to decrease to zero. M2 becomes a
switch and v O tracks V S2(VDS5) all the
way to VSS.
V OL = V SS .

I 1 still equals I2 due to mirror

Allen and Holberg - CMOS Analog Circuit Design

Page VII.2-5

TWO-STAGE COMPARATOR
Combine the differential amplifier stage with the inverter stage.
Sufficient gain.
Good signal swing.

VDD
M3

M4
M6

vN

M1

M2

I8

M8

M5

VSS

vP

vO

M7

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-1

VII.3 - DESIGN OF A TWO-STAGE CMOS

COMPARATOR
DC BALANCE CONDITIONS FOR TWO-STAGE
COMPARATOR

Try to keep all devices in saturation - more gain and wider signal
swings.

Based on gate-source and DC current relationship. I.e. if M1 and M2

are two matched devices and if VGS1 = VGS2, then ID1 = I D2 or vice
versa.
W1
Let S1 = L ,
1
M1 and M2 matched gives S 1 = S2.
M3 and M4 matched gives S 3 = S4.
also, I 1 = I2 = 0.5I5.
From gate-source matching, we have
S7
S6
VGS5 = VGS7 I7 = I5 and I 6 = I4 Assume
S5
S4
VGS4 =VGS6
For balance conditions, I6 must be equal to I7, thus
I 5 S7 S6
.
I4 S5 = S4
Since

I5
I4 = 2, then DC balance is achieved under the following:
S6
S
. 7 VDG4 = 0 M4 is saturated.
=
2
S4
S5

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-2

SYSTEMATIC OFFSET ERROR

VDD =10V
+

KN = 24.75 A/V2
KP = 10.125 A/V2
VTN = -VTP = 1V
N = 0.015V -1
P = 0.020V -1

+
2V
20 2V
10
M3
- M6 40
M4

20
10

I8

20
10

vN
M1

Find VOS to make i6 = i 7

vP

M5

VSS =0V

(2) Find how much vGS6 must be reduced to make i6 = i 7

vGS6 = vGS6(2.115i4) - vGS6(2.057i4)
2L6

KPW6 i 4 2.115 - 2.057 = 14.11 mV

(3) Reflecting vGS6 into the input

KN( W2/L2)
2

= 89.9

I5
2 + 4
vGS6
14.1 mV
= 0.157 mV
VOS = A (diff) = 89.9
v
A v(diff) =

vO =5V

10
10 3V

M7

(1) Find the mismatch between i6 and i 7

i7 1 + N v D S 7 W7/L7 1 + (0.015)(5)
i5 = 1 + N v D S 5 W5/L5 = 1 + (0.015)(3) (1) = 1.029
i6 1 + P v D S 6 W6/L6 1 + (0.02)(5)
i4 = 1 + P v D S 4 W4/L4 = 1 + (0.02)(2) (2) = 2.115
i5 = 2i4
i7 = (1.029)(2)i4 = 2.057i4 and i6 = 2.115i4

vGS6 =

i6
i7

M2
20A

M8

10

20
10

10
10

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-3

DESIGNING FOR COMMON MODE INPUT RANGE

VDD
+
VSG3
M3
I5/2

VG1

vG1 (min) = VSS + VDS5 + VGS1

VDG1
-

+ M1
VGS1
-

v G1 (min) = V SS + V DS5 + V T1 (max) +

+
VDS1
-

vG1 (max) = VDD - VSG3 - VDG1(sat)

+

I5

VBIAS

v G1 (max) = V D D -

VDS5
VSS

I5
21

M5

I5
23 - VT3(max) + V T1 (min)

where V DG1(sat) = -VT1

Example
Design M1 through M4 for a CM input range 1.5 to 9 Volts when VDD =
10 V, ISS = 40A, and VSS = 0V. Table 3.1-2 parameters with |VTN,P| =
0.4 to 1.0 Volts,
I5
vG1(min) = VSS + VDS5 +
1 + VT1(max)
40A
+ 1 (assumed VDS5 0.1V- it probably more
1.5 = 0 + 0.1 +
1
reasonable to assume 1 is already defined and find 5)
1 =

KNW 1
2
L1 = 250 A/V

vG1(max) = VDD 3 =

W1 W 2
L1 = L2 = 14.70

I5
3 - |VT3(max)| + VT1(min)

K PW 3
2
L3 = 250 A/V

W3 W 4
L3 = L4 = 31.25

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-4

GAIN OF THE TWO-STAGE COMPARATOR

+

+
gm1vid

r ds2

r ds4

v1 gm6v1
-

r ds6

r ds7

vid = vP - vN
gm1

ds2 + g ds4

Av = g

2
Av =

gm6

g ds6 + g ds7

W1 W6
KNKP L L
1 6

( 2 + 4) ( 6 + 7)

vout

I1I6

W6
W1
Using L = 5, L = 5, N = 0.015V-1 , P = 0.02V-1
1
6
and Table 3.1-2 values;
2 (17)(8)(5)(5) . -6 95199.10-6
Av =
10 =
(0.015+0.02)2 I1I6
I1I6
Assume I1 = 10 A and I6 = 100 A
Av = 3010
V OH - VOL
= Resolution = 5 mV (assume)
Av
5 .
then VOH - V OL =
1000 3000 = 15 Volts

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-5

PROPAGATION DELAY OF THE TWO-STAGE

COMPARATOR
VDD
signal swing
less than the
M4 output

M3

vN

VGS6 +
-

M1

M2

vP
CL1

VBIAS

M6
i6 key node
vO
i7
CL2

M5

M7

i5
VSS
V GS6 = VDD - v P + V D G 2
dv
iC = C dt , t =

v
CI

t2+ = C L2

K P W6 V
2 L6 ( D D

t+2

VTRP3
V
VDD
SS
VTRP3

V TRP3 - V S S
- v P - V D G 2 - |V T6 | ) 2 -

V DD - V TRP3

t2- = CL2 W L
7 5 i
L7 W5 5

t-2

Slew rate =

isource/sink
CLi

I7

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-6

CALCULATION OF COMPARATOR PROPAGATION DELAY

Find the total propagation delay of
the comparator shown when the input
vP goes from -1 to +1 in 2ns. Assume
the trip point of the output(next stage)
is zero.
Total delay = 1st stage + 2nd stage
delay
delay

+5V
10
10

M3

40
10
C L1=0.3pF

M4
vDO

vN

M1

M2
20
10

vP

VTRP2 = VDD - VGS6, VGS6 = |VT6 | +

CL2=
10pF

I7 =40A

I5=20A

t = t1 + t2
( v DO (t 0 ) - V TRP2)
t1 =
CL1 ,
I5
vDO(t0) = 5 because vP = -1V

M6
I6

-5V

2I7
KP'( W6/L6)

2.40
= 2.58 V VTRP2 = 5 - 2.58 = 2.42 V
8.4
0.3pF
= 38.7ns
t1 = (5 - 2.42)
20A
CL2
CL2
t2 = v O (t 0 ) - 0
=5

I 6 - I 7
I 6 - I 7
KP6' W6
I6 = 2 L V D D - V D O (min) - VT6 2

6
[VDO(min) is an optimistic assumption based on vDS2 0]
VGS6 = 1 +

VDO(min) vDS2(0) - vGS1 + vN = -VT1 -

I5
= -1.77
KN.2

8.10-6
2
2 (4)(5 - (-1.77) -1) = 533 A
10 pF
t2 = 5 (533 - 40) A = 101 ns

I6 =

t = t1 + t2 139 ns
Second order consideration: Charging of Csb of M1 and M2

vO

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-7

SIMULATION OF THE PROPAGATION DELAY

5v
+5V
10
10

M3

M4
(6)

vN

M1

3v
2.42v

M8

20
10

M2

M6

CL1

40
10
(9)

vP

vO

CL2

10
10

M7
-5V
1v

vP

0v

tprop=167 ns

20
10

V(9)

Actual
-1 v
V(6)

-1.54v

COMPARATOR PROPAGATION DELAY

VDD 10 0 DC 5V
VSS 11 0 DC -5V
VN 1 0 DC 0V
VP 2 0 PULSE(-1 1 0N 1N 1N 500N 1U)
M1 3 1 5 5 MNMOS W=20U L=10U
M2 6 2 5 5 MNMOS W=20U L=10U
M3 3 3 10 10 MPMOS W=10U L=10U
M4 6 3 10 10 MPMOS W=10U L=10U
M5 5 8 11 11 MNMOS W=10U L=10U
M6 9 6 10 10 MPMOS W=40U L=10U
M7 9 8 11 11 MNMOS W=20U L=10U
M8 8 8 11 11 MNMOS W=10U L=10U
CL1 6 0 0.3PF
CL2 9 0 10PF
IS 0 8 DC 20UA
.MODEL MNMOS NMOS VTO=1 KP=17U
+LAMBDA=0.015 GAMMA=0.8 PHI=0.6
.MODEL MPMOS PMOS VTO=-1 KP=8U
+LAMBDA=0.02 GAMMA=0.4 PHI=0.6
.TRAN 2N 300N
.PRINT TRAN V(6) V(9) V(2)
.PROBE
.END

Approx.

-3 v

-5 v
0ns

50ns

100ns

150ns

Time

200ns

250ns

300ns

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-8

SMALL SIGNAL PERFORMANCE

vin
-

+
gm1
-

gm2
R1

C1

R2

C2

vout
-

vout(s)
A o p1 p2
=
vin(s)
( s + p 1) ( s + p 2)
1
p1 = R C
1 1
1
p2 =
R2C2
Ao = gm1gm2R1R2

Example - (Fig 7.3-4)

1
1
=
10A = 3.33M
ds2 + g ds4
1
p1 =
(0.3pF)(3.33M) = 1Mrps

I5 = 20A R1 = g

1
1
=
40A(.03) = 833K
ds6 + g ds7
1
p2 =
(10pF)(833K) = 120Krps

I7 = 40A R2 = g

g m1 = 26s, gm2 = 50.6s A o = 1099

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-9

TWO-STAGE, CMOS COMPARATOR

General Schematic
VDD
M3

M4
M6
M1

vN

M2

I8

M5

M8

vP

vO

M7

VSS
Key Relationships for Design:

i D = (v G S - V T ) 2
2
or
v DS (sat) =
Also,
gm =
where
KW
= L

2I D

2iD(sat)

iD (sat) = 2 [vDS(sat)]2

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-10

COMPARATOR DESIGN PROCEDURE

1. Set the output current to meet the slew rate requirements.
dV
i = C dt
2. Determine the minimum sizes for M6 and M7 for the proper ouput
voltage swing.
vDS (sat) =

2ID

3. Knowing the second stage current and minimum device size for M6,
calculate the second stage gain.
A2 =

-g m6
g ds6 + g ds7

4. Calculate the required first stage gain from A2 and gain specifications.
5. Determine the current in the first stage based upon proper mirroring
and minimum values for M6 and M7. Verify that Pdiss is met.
6. Calculate the device size of M1 from A1 and I DS1.
A1 = g

-g m1
ds1 + g ds3

and

gm1 =

2K'W/L
IDS1

7. Design minimum device size for M5 based on negative CMR requirement using the following (IDS1 = 0.5IDS5):
vG1(min) = VSS + VDS5 +
where VDS5 =

IDS5
1 + VT1(max)

2IDS5
5 = VDS5(sat)

8. Increase either M5 or M7 for proper mirroring.

9. Design M4 for proper positive CMR using:
vG1(max) = VDD -

IDS5
3 - VTO3 (max) + VT1

10. Increase M3 or M6 for proper mirroring.

11. Simulate circuit.

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-11

DESIGN OF A TWO-STAGE COMPARATOR

Specifications:
Lambda = 0.05V-1 (L = 5 m)

Avo > 66 dB
Pdiss < 10 mW

VDD = 10 V

CL = 2 pF

VSS = 0 V

tprop < 1 s

K'W
Recall that = L

CMR = 4-6 V
Output swing is VDD - 2V and VSS + 2V
1). For t prop << 1 s choose slew rate at 100 V/s
dvOUT
. -12
. -6
dt = ( 2 10 ) ( 100 10 ) = 200 A

I7 = CL

2). Size M6 and M7 to get proper output swing,

M7:
2V > vDS7(sat) =

2I7
7 =

W7
2(200A)

L7 > 5.88
17.0A/V 2( W7/L7)

M6:
2V > vDS6(sat) =

2( IOUT+I7)
=
6

-g m6
-1

=
3). A 2 = g

ds6 + g ds7
N + P

W6
2(400A)

L6 > 12.5
8.0A/V 2( W6/L6)

2KP'W6
I6L6 -10

4). A vo = A 1A2 = 66 dB 2000 A1 = 200

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-12

COMPARATOR DESIGN - CONT'D

S4
5). Assuming vGS4 = v GS6, then I4 =
S6 I6
1
choose S 4 = 1 which gives I4 = 12.5 (200A) = 16.0 A
S5
200A
Assume S5 = 1 which gives I 5 =
I
=
7
S7
5.88 = 34 A
1
and I4 = I5 = 17 A
2
W
to keep L ratios greater than 1.
Choose I 4 = 17 A
W4 W 6 17
I5 = 34 A
L4 = L6 200 = 1.06 1.0
Pdiss = 10( I 7 + I 5 ) = 2.34 mW < 10 mW
1
6). A1 = +
1
4
W1
L = 200
1

2KN'W1
W1
I
2 4 = 200

=
(
+

)A
[
1
4
1
]
I4L 1
L1
2KN'
(Good for noise)

7). V DS5 = vG1(min) - VSS V DS5 = 4 - 0 VDS5 =

8). S5 =

2I5
5 =

I5
1 - VT1(max)

(34)
-1 = 2.90 V
2(17.0)(200)
W5
2(34)
L > 0.48
(17)S5
5

I5
W5
34
S
=
(5.88)
=
1.0

7
I7
200
L5 = 1 . 0

Allen and Holberg - CMOS Analog Circuit Design

Page VI.3-13

COMPARATOR DESIGN - CONT'D

9). VG1(max) = VDD 3 =

I5
3 - VTO3 (max) + VT1(min)
I5

V D D - V G1 (max) - VTO3 (max) + V T1 (min) 2

34 A
= 2.76.10 -6
( 1 0 - 6 - 1 + 0 . 5) 2
W3 (2.76)(2)
W3 W 4
L =
=
0.69
8
L3 = L4 > 0.69
3
W4
(Previously showed L > 1.06 so no modification is necessary)
4
=

10). Summary
W
Wdrawn = (L - 1.6)
L
Design Ratios

W1
L1
W3
L3
W5
L5
W6
L6
W7
L7

W2
= L = 200
2
W4
= L = 1.0
4
= 1.0
= 12.5
= 5.88

W1
L1
W3
L3
W5
L5
W6
L6
W7
L7

Actual Values with 5m

Proper Mirroring

minimum geometry

and LD = 0.8m

W 2 1000
= L = 5
2
W4 5
= L =5
4
= 1.0
62.5
= 5
30
= 5

(Need to adjust for proper mirroring)

680
5
3.4 5
5
5
3.4 5
5
5
60
5
30
5

S6
S7
=
2
S4
S5

Allen and Holberg - CMOS Analog Circuit Design

Page VII.4-1

VII.4 - OTHER TYPES OF COMPARATORS

FOLDED CASCODE CMOS COMPARATOR
Circuit Diagram
VDD

MP3

MP4

MP12

MP13

MP8

MP6

MN25

MN1

MN2

vOUT

MN10

MN11

MN9

MN5

v1

v2

MN24

MN7

V SS

Small Signal Model

1
gm12
gm1 v2

i1

1
gm13

+
i2
i2

gm2 v1

i1

rout

vout
-

where
R out (rds5gm11rds11)||((rds4||rds2)gm13rds13) =
=g

1
ds5gds11 (gds2+gds4)gds13
gm11 +
gm13

The small signal voltage gain is

vout = r out (i2-i1) = (gm2 +gm1 )Rout vin = g

where vin = v1 - v2.

gm1 +gm2
vin
ds5gds11 (gds2+gds4)gds13
gm11 +
gm13

Allen and Holberg - CMOS Analog Circuit Design

Page VII.4-2

FOLDED CASCODE CMOS COMPARATOR - CONTINUED

Frequency Response
Small signal modelC1

i1

gm1 v2

gm12 gm2 v1

i2

C2
1

gm13

C3

i2

i1

rout

vout
-

where
C1 = C GS12 + C BS12 + C DG3 + C BD3
C2 = C GS13 + C BS13 + C DG4 + C BD4
and

C3 = CDG11 + CBD11 + CDG13 + CBD13 + CLoad

AVD03
AVD(s) s +
3

where
1
3 =
routC3
Typical performanceW 1 W 2 W 11 W 13
ID1 = ID2 = 50A and ID3= I D4 = 100A,
L1 = L2 = L11 = L13
=1, assume C 3 0.5pF, and using the values of Table 3.1-2 gives:
gm1 = gm2 = gm11 =41.2S
gds5 = gds11 = 0.5S

gm13 = 28.3S

gds4 = gds13 = 0.25S

Therefore, rout = 121M, 3 = 16.553krps, and AVD0 = 4,978

resulting in a gain-bandwidth of 13.11MHz.
C3V
0.5pFx10V
Delay = T = I
= 100A = 50nS
max

Allen and Holberg - CMOS Analog Circuit Design

Page VII.4-3

OPEN LOOP COMPARATOR - MC 14575

BIAS

M1

M6
M8

M10
vO

M2

M3

M9

M11

M7
M4

M5

Performance (ISET = 50 A)
Rise time
= 100 ns into 50 pF
Fall time
Propagation delay = 1 s
Slew rate = 2.7 Volts/s
Loop Gain = 32,000

Comments
The inverter pair of M8-M9 and M10-M11 are for the purpose of
providing an output drive capability and minimizing the propagation delay.

Allen and Holberg - CMOS Analog Circuit Design

Page VII.4-4

CLAMPED CMOS VOLTAGE COMPARATOR

VDD

VDD

M6

M8

BIAS

VPB

M1

vO
-

+
M3

M2
M9

M4

VNB

M5

M7

VSS

Drain of M2 and M3 clamped to the gate voltages of M4 and M5.

M6 and M7 provide a current, push-pull output drive capability

similiar to the current , push-pull CMOS OP amp.

Comparator is really a voltage comparator with a current output.

Allen and Holberg - CMOS Analog Circuit Design

Page VII.6-1

VII.5 - COMPARATORS WITH HYSTERESIS

HYSTERESIS
Why Hysteresis?
Eliminates "chattering" when the input is noisy.
Comparator with no Hysteresis
vin

Comparator
threshold

Time

Comparator
output

Comparator with Hysteresis

vin
vout
VTRP+
VTRPTime
vin
VTRP-

VTRP+ comparator
output

Allen and Holberg - CMOS Analog Circuit Design

Page VII.6-2

VOLTAGE COMPARATORS USING EXTERNAL FEEDBACK

Inverting
vOUT
VOH

vB
vA

vOUT

VREFR2
R1 +R2
VOHR2
R1 +R2

R2

R1
+
V
- REF

VOL

vB

VOLR2
R1 +R2

Noninverting
vOUT
R2
vIN

VOH

R1

vA +
vB

VREF R1 +R2
R2

vOUT

vIN

+
- VREF

R1 V
R2 OL

VOL
R1 V
R2 OH

Allen and Holberg - CMOS Analog Circuit Design

Page VII.6-3

COMPARATORS WITH INTERNAL FEEDBACK

Cross-Coupled Bistable
VDD
M3

M10 M11

M4

M8

M6

M1

M2
vO

BIAS

M5

M9

M7
VSS

(1). Positive feedback gives hysteresis.

(2). Also speeds up the propagation delay time.

1.0V
-600m

2.0V

3.0V

4.0V

5.0V

6.0V

-400m

-200m

0m

200m

EXAMPLE 7.4-1 COMPARATOR WITH HYSTERESIS

400m

600m

Allen and Holberg - CMOS Analog Circuit Design

Page VII.6-4

Allen and Holberg - CMOS Analog Circuit Design

Page VII.6-5

AUTO ZEROING OF VOLTAGE COMPARATORS

Model of the Comparator Including Offset

+
-

IDEAL

VOS

Auto Zero Scheme-First Half of Cycle

+
-

IDEAL

CAZ

VOS

Auto Zero Scheme-Second Half of Cycle

VIN

+
VOS

+
VOS

IDEAL

+
0V
-

+
V
- OS

Allen and Holberg - CMOS Analog Circuit Design

Page VII.6-6

GENERALIZED AUTO ZERO CONFIGURATION

1

vIN+

+
1

vIN-

VOS

+ CAZ

IDEAL
+

VOS

Good for inverting or noninverting when the other terminal is not

on ground.

vOUT

Allen and Holberg - CMOS Analog Circuit Design

Page VII.6-7

Noninverting Auto-Zeroed Comparator

1

vOUT

vIN

+
CAZ
2

Inverting Auto-Zeroed Comparator

1

2
CAZ
-

vIN

vOUT
1

Use nonoverlapping, two-phase clock.

Allen and Holberg - CMOS Analog Circuit Design

Page VII.6-1

VII.6 - HIGH SPEED COMPARATORS

Concept
Question: For a given input change, what combination of first-order openloop comparators and a latch gives minimum propagation delay?

C1

vIN
-

C2

C3

Cn

Latch

Q
Q

n first-order, open-loop comparators

with identical gains, A
Concept:
voltage
High
Output
Level

= input voltage
change
Latch

tn-1 )e-t/ ]
v out = An[1 - (1 + (n-1)!

v out = A(1-et/ )

A5
A4
A3

5
4
3
v out = A2[1 - (1 + t)e -t/ )]
2
v out = A(1-e-t/ )
n=1

A2
A
t3

tL

Propagation delay time = t3 + tL for n=3

Answer:
tp(min) occurs when n=6 and A=2.72=e
Implementation:
n=3 and A6 gave nearly the same result with less area.

Time

Allen and Holberg - CMOS Analog Circuit Design

Page VII.6-2

HIGH SPEED COMPARATORS-CONT'D

Conceptual Implementation-

+
vIN
-

Latch

Q
Q

VDD

Q
FB

Reset
Q
FB

VB1

Offset and level shifting-

vIN

VB2
VSS

vIN-VOS
+ -

+
VOS

LATCH

Allen and Holberg - CMOS Analog Circuit Design

Page VII.7-1

VII.7 - COMPARATOR SUMMARY

Key performance parameters:
Propagation time delay
Resolving capability
Input common mode swing
Input offset voltage
Types of comparators:
Open loop
Regenerative
Open loop and regenerative
Charge balancing
Open loop comparator needs differential input and second stage
Systemative offset error is offset (using perfectly matched transistors)
that is due to current mirror errors.
For fast comparators, keep all node swings at a minimum except for the
output (current comparators?).
Key design equations:
iD =

KW
2
2L (vGS-VT) ,

vDS(sat) =

2iD
K(W/L) , and gm =

2KWID
L

Positive feedback is used for regenerative comparators.

Use autozeroing to remove offset voltages (charge injection is limit).
Fastest comparators using low-gain, fast open loop amplifiers cascaded
with a latch.