library IEEE;

library IEEE.STD_LOGIC_1164.all;
entity DEBOUNCE is
port(
C:
R:
SW:
DEB:
);
end DEBOUNCE;

in STD_LOGIC;
in STD_LOGIC;
in STD_LOGIC;
out STD_LOGIC;

--clock
--reset sincrono
--entrada con rebotes
--salida filtrada

entity EDGE is
port(
R: in STD_LOGIC;
CLK: in STD_LOGIC;
Level: in STD_LOGIC; --entrada con rebotes
Tick: out STD_LOGIC; --salida filtrada
);
end EDGE;
entity TOP is
Port ( GCK: in STD_LOGIC;
SW : in STD_LOGIC_VECTOR (7 downto 0);
BTN : in STD_LOGIC_VECTOR (3 downto 0);
LED : out STD_LOGIC_VECTOR (7 downto 0);
CAT : out STD_LOGIC_VECTOR (7 downto 0);
AN : out STD_LOGIC_VECTOR (3 downto 0));
end TOP;
architecture Behavioral of TOP is
signal DEB_SAL,EDGE_SAL: STD_LOGIC;
begin
--LED<= SW;
CAT<= SW;
AN<= not BTN;
Inst_CB4_0:
PORT MAP(
C
CLR
L
CE
D0
D1
D2
D3
Q0
Q1
Q2
Q3
TC
CEO
);

entity CB4CLE(BlackBox)
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>

GCK ,
BTN(0),
BTN(1),
BTN(3),
SW(0),
SW(1),
SW(2),
SW(3),
LED(0),
LED(1),
LED(2),
LED(3),
open,
open --Conectado al siguiente CE_sal

Inst_CB4_1: entity CB4CLE(BlackBox)

PORT MAP(
C => GCK ,

CLR
L
CE
D0
D1
D2
D3
Q0
Q1
Q2
Q3
TC
CEO

=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>
=>

BTN(0),
BTN(1),
EDGE_SAL,
SW(4),
SW(5),
SW(6),
SW(7),
LED(4),
LED(5),
LED(6),
LED(7),
open,
open

);
Inst_DEB: entity DEBOUNCE(Behav)
PORT MAP(
C
=> GCK,
R
=> BTN(0), -- reset sincrono
SW => BTN(3), -- entrada con rebotes
DEB => DEB_SAL -- salida filtrada
);
Inst_EDGE: entity
PORT MAP(
R
CLK
Level
Tick
);
end Behavioral;

EDGE(BlackBox)
=>
=>
=>
=>

BTN(0),
GCK,
DEB_SAL, --entrada
EDGE_SAL --salida