Note: The RAM has inverting outputs so this switch

has also been inverted to enter the correct data.

UP = Logic 0 input = Logic 1 Output fromRAM
DOWN = Logic 1 input = Logic 0 output fromRAM
(Observe W-Bus indicators for correct value)
Note: This extra switch was added to
isolate the output of the Program Counter
fromthe W-bus when entering data, otherwise
a logic contention will occur.
Note: The 555 timer circuit has been substituted with
a virtual clock source to speed up the simulation.
Memory Address Register
Note: These pull-up resistors are necessary
because t he out put s of t he 74LS89 ( substi t ute
for the 74LS189) are open collector.
Ring Counter
Instruction Decoder Control Matrix
C
p

E
p

L
m

C
E

L
i
E
i
L
a

E
a

S
u

E
u

L
b

L
o

T
1

T
2

T
3

T
4

T
5

T
6

J
1
Q
3
CLK
12
K
4
Q
2
R

1
3

U36:A
74LS107
J
8
Q
5
CLK
9
K
11
Q
6
R

1
0

U36:B
74LS107
J
1
Q
3
CLK
12
K
4
Q
2
R

1
3

U38:A
74LS107
J
8
Q
5
CLK
9
K
11
Q
6
R

1
0

U38:B
74LS107
J
1
Q
3
CLK
12
K
4
Q
2
R

1
3

U37:A
74LS107
J
8
Q
5
CLK
9
K
11
Q
6
R

1
0

U37:B
74LS107
T6
T5
T4
T3
T2
T1
1 2
U31:A
3 4
U31:B
5 6
U31:C
13 12
U31:D
CLK
CLR
1
2
4
5
6
U32:A
9
10
12
13
8
U32:B
1
2
4
5
6
U33:A
9
10
12
13
8
U33:B
1
2
4
5
6
U34:A
1
1

1
0

U35:E
1
3

1
2

U35:D
1 2
U35:A
3 4
U35:B
5 6
U35:C
9 8
U35:F
HLT
1

2

3

4

5

6

1
0

9

8

1
3

1
2

1
1

1

2

4

5

6

U44:A
Cp Ep
1

2

U47:A
Lm
U39:D
1

2

3

4

5

6

1
0

9

8

1
3

1
2

1
1

U40:D
1

2

3

4

5

6

1
0

9

8

1
3

1
2

1
1

U41:D
1

2

3

4

5

6

1
0

9

8

1
3

1
2

1
1

U42:D
1

2

3

4

5

6

1
0

9

8

U43:C
9

1
0

1
2

1
3

8

U44:B
1

2

1
3

1
2

U45:A
3

4

5

6

U45:B
1

2

3

U46:A
4

5

6

U46:B
3

4

U47:B
5

6

U47:C
9

8

U47:F
1
1

1
0

U47:E
1
3

1
2

U47:D
1

2

U48:A
3

4

U48:B
CE Li Ei La Ea S u Eu Lb Lo
LDA
ADD
SUB
OUT
1
2
13
12
U25:A
CLR
CLR
SW5 START
CLEAR
SW6
Clear/St art
Si ngl e Step
LOW
HIGH
SW7
Manual/ Auto
Manual
Aut o
HLT
13
12
11
U26:D
CLK
CLK
1 2
U27:A
3 4
U27:B
5 6
U27:C
1
2
3
U24:A
4
5
6
U24:B
7400
10
9
8
U24:C
13
12
11
U24:D
7400
VCC
VCC
VCC
U25:B(C)
INIT=LOW
START=0
COUNT=-1
CLOCK=1
4
5
6
U26:B
1
2
3
U26:A
VCC
VCC
VCC
3
4
5
6
U25:B
HLT
I7 I6 I5 I4
?

?

?

?

?

?

?

?

?

?

?

?

?

?

?

?

?

?

J
1
Q
3
CLK
12
K
4
Q
2
R

1
3

U1:A
74LS107
J
8
Q
5
CLK
9
K
11
Q
6
R

1
0

U1:B
74LS107
J
1
Q
3
CLK
12
K
4
Q
2
R

1
3

U2:A
74LS107
J
8
Q
5
CLK
9
K
11
Q
6
R

1
0

U2:B
74LS107
2

3

1
U3:A
5

6

4
U3:B
9

8

10
U3:C
1
2

1
1

13
U3:D
74LS126
Cp
CLK
CLR
ENpc
D
0

1
4

Q
0

3

D
1

1
3

Q
1

4

D
2

1
2

Q
2

5

D
3

1
1

Q
3

6

C
L
K

7

O
E
1

1

O
E
2

E
1

E
2

2

9

1
0

M
R

1
5

U4
74LS173
1
A

2

1
Y

4

1
B

3

2
A

5

2
Y

7

2
B

6

3
A

1
1

3
Y

9

3
B

1
0

4
A

1
4

4
Y

1
2

4
B

1
3

A
/ B

E

1

1
5

U5
74LS157
2-1 Multiplexer
CLK
Lm
W4 W3 W2 W1 W0 W5 W6 W7
ENmar
ADR3
ADR2
ADR1
ADR0
D
1

4

D
2

6

D
3

1
0

D
4

1
2

A
2

1
4

A
3

1
3

M
E

2

W
E

3

Q
1

5

Q
2

7

Q
3

9

Q
4

1
1

A
0

1

A
1

1
5

U6
74LS89
16 X 4-bit RAM
D
1

4

D
2

6

D
3

1
0

D
4

1
2

A
2

1
4

A
3

1
3

M
E

2

W
E

3

Q
1

5

Q
2

7

Q
3

9

Q
4

1
1

A
0

1

A
1

1
5

U7
74LS89
16 X 4-bit RAM
D4
D5
D6
D7
D0
D1
D2
D3
WEr am
ENram
WEr am
ENram
D
0

1
4

Q
0

3

D
1

1
3

Q
1

4

D
2

1
2

Q
2

5

D
3

1
1

Q
3

6

C
L
K

7

O
E
1

1

O
E
2

E
1

E
2

2

9

1
0

M
R

1
5

U8
74LS173
Instruction
Regi st er
( OPCode)
D
0

1
4

Q
0

3

D
1

1
3

Q
1

4

D
2

1
2

Q
2

5

D
3

1
1

Q
3

6

C
L
K

7

O
E
1

1

O
E
2

E
1

E
2

2

9

1
0

M
R

1
5

U9
74LS173
Instruction
Regi st er
( Address)
CLK CLK
Ei
Li
Li
CLR
I 7

I 6

I 5

I 4

VCC
D
0

1
4

Q
0

3

D
1

1
3

Q
1

4

D
2

1
2

Q
2

5

D
3

1
1

Q
3

6

C
L
K

7

O
E
1

1

O
E
2

2

E
1

9

E
2

1
0

M
R
U11
74LS173
Accumul ator
D
0

1
4

Q
0

3

D
1

1
3

Q
1

4

D
2

1
2

Q
2

5

D
3

1
1

Q
3

6

C
L
K

7

O
E
1

1

O
E
2

2

E
1

9

E
2

1
0

M
R
U10
74LS173
Accumul ator
2 3
1

5 6
4

9 8
1
0

12 11
1
3

U12:D
74LS126
Accumul ator
Out put
2 3
1

5 6
4

9 8
1
0

12 11
1
3

U13:D
74LS126
Accumul ator
Out put
Ea
A
0

5

A
1

3

A
2

1
4

A
3

1
2

B
0

6

B
1

2

B
2

1
5

B
3

1
1

C
0

7

C
4

9

S
0

4

S
1

1

S
2

1
3

S
3

1
0

U16
74LS283
Full Adder
(MSB)
A
0

5

A
1

3

A
2

1
4

A
3

1
2

B
0

6

B
1

2

B
2

1
5

B
3

1
1

C
0

7

C
4

9

S
0

4

S
1

1

S
2

1
3

S
3

1
0

U17
74LS283
Full Adder
(LSB)
1
5

1
5

La
CLK
La
CLK
Ea
1

2

3

4

5

6

9

8

1
2

1
1

U15:D
74LS86
1

2

3

4

5

6

9

8

1
2

1
1

U14:D
74LS86
S u Carry
1
0

S u
1
3

S u
1
3

1
0

1
2

1
1

13
U19:D
74LS126
9

8

10
5

6

4
2

3

1
1
2

1
1

13
U18:D
74LS126
9

8

10
5

6

4
2

3

1
Carry
D
0

1
4

Q
0

3

D
1

1
3

Q
1

4

D
2

1
2

Q
2

5

D
3

1
1

Q
3

6

C
L
K

7

O
E
1

1

O
E
2

2

E
1

9

E
2

1
0

M
R
U20
74LS173
B Regi st er
(MSB)
D
0

1
4

Q
0

3

D
1

1
3

Q
1

4

D
2

1
2

Q
2

5

D
3

1
1

Q
3

6

C
L
K

7

O
E
1

1

O
E
2

2

E
1

9

E
2

1
0

M
R
U21
74LS173
B Regi st er
(LSB)
D
0

1
4

Q
0

3

D
1

1
3

Q
1

4

D
2

1
2

Q
2

5

D
3

1
1

Q
3

6

C
L
K

7

O
E
1

1

O
E
2

2

E
1

9

E
2

1
0

M
R

1
5

U22
74LS173
Out put Regi st er
D
0

1
4

Q
0

3

D
1

1
3

Q
1

4

D
2

1
2

Q
2

5

D
3

1
1

Q
3

6

C
L
K

7

O
E
1

1

O
E
2

2

E
1

9

E
2

1
0

M
R

1
5

U23
74LS173
Out put Regi st er
CLK
Lo
CLK
Lo
Lb
CLK
1
5

Lb
CLK
1
5

O
P
0

O
P
1

O
P
2

O
P
3

O
P
4

O
P
5

O
P
6

O
P
7

A
D
R
3

A
D
R
2

A
D
R
1

A
D
R
0

SW2
Progr am/ Run
VCC
CE
ENram
ENmar
O
N

O
F
F

4

8

7

6

5
SW1
Address
Swit ch
O
F
F

O
N

9

SW3
OPCode / Dat a
Swi t ches
D
7

8

D
6

7

D
5

6

D
4

5

D
3

4

D
2

3

D
1

2

1

D
0

SW4
Write
Memory
VCC
WEr am
W
7

W
6

W
5

W
4

W
3

W
2

W
1

W
0

?

?

?

?

?

?

?

?

O
P
0

O
P
1

O
P
2

O
P
3

O
P
4

O
P
5

O
P
6

O
P
7

1

2

3

SW8
Progr am/ Run
ENpc
Ep
Eu
1
6

1
5

1
4

1
3

1
2

1
1

1
0

ADR3
ADR2
ADR1
ADR0
D7
D6
D5
D4
D3
D2
D1
D0
VCC
CLR CLR