Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR

Topics
Basic fabrication steps.
Transistor structures.
Basic transistor behavior.
Latch up.
Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR
Our technology
We will study a generic 180 nm technology.
Assume 1.2V supply voltage.
Parameters are typical values.
Parameter sets/Spice models are often
available for 180 nm, harder to find for 90
nm.
Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR
Fabrication services
Educational services:
U.S.: MOSIS
EC: EuroPractice
Taiwan: CIC
Japan: VDEC
Foundry = fabrication line for hire.
Foundries are major source of fab capacity
today.
Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR
Fabrication processes
IC built on silicon substrate:
some structures diffused into substrate;
other structures built on top of substrate.
Substrate regions are doped with n-type and
p-type impurities. (n+ = heavily doped)
Wires made of polycrystalline silicon
(poly), multiple layers of aluminum (metal).
Silicon dioxide (SiO
2
) is insulator.
Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR
Simple cross section
substrate
n+ n+
p+
substrate
metal1
poly
SiO
2

metal2
metal3
transistor
via
Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR
Photolithography
Mask patterns are put on wafer using photo-
sensitive material:
Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR
Process steps
First place tubs to provide properly-doped
substrate for n-type, p-type transistors:
p-tub p-tub
substrate
Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR
Process steps, contd.
Pattern polysilicon before diffusion regions:
p-tub p-tub
poly poly
gate oxide
Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR
Process steps, contd
Add diffusions, performing self-masking:
p-tub p-tub
poly poly
n+ n+ p+ p+
Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR
Process steps, contd
Start adding metal layers:
p-tub p-tub
poly poly
n+ n+ p+ p+
metal 1 metal 1
vias
Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR
Transistor structure
n-type transistor:
Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR
0.25 micron transistor (Bell Labs)
poly
silicide
source/drain
gate oxide
Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR
Transistor layout
n-type (tubs may vary):
w
L
Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR
Drain current characteristics
Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR
Drain current
Linear region (V
ds
< V
gs
- V
t
):
I
d
= k (W/L)(V
gs
- V
t
)(V
ds
- 0.5

V
ds
2
)
Saturation region (V
ds
>= V
gs
- V
t
):
I
d
= 0.5k (W/L)(V
gs
- V
t
)
2

Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR
180 nm transconductances
Typical values:
n-type:
k
n
= 170 A/V
2

V
tn
= 0.5 V
p-type:
k
p
= 30 A/V
2

V
tp
= -0.5 V
Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR
Current through a transistor
Use 180 nm parameters. Let W/L = 3/2.
Measure at boundary between linear and
saturation regions.
V
gs
= 0.7V:
I
d
= 0.5k(W/L)(V
gs
-V
t
)
2
= 5.3 A
V
gs
= 1.2V:
I
d
= 62 A
Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR
Basic transistor parasitics
Gate to substrate, also gate to source/drain.
Source/drain capacitance, resistance.
Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR
Basic transistor parasitics, contd
Gate capacitance C
g
. Determined by active
area.
Source/drain overlap capacitances C
gs
, C
gd
.
Determined by source/gate and drain/gate
overlaps. Independent of transistor L.
C
gs
= C
ol
W
Gate/bulk overlap capacitance.
Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR
Latch-up
CMOS ICs have parastic silicon-controlled
rectifiers (SCRs).
When powered up, SCRs can turn on,
creating low-resistance path from power to
ground. Current can destroy chip.
Early CMOS problem. Can be solved with
proper circuit/layout structures.
Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR
Parasitic SCR
circuit I-V behavior
Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR
Parasitic SCR structure
Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR
Solution to latch-up
Use tub ties to connect tub to power rail. Use
enough to create low-voltage connection.
Modern VLSI Design 4e: Chapter 2 Copyright 2009 Prentice Hall PTR
Tub tie layout
metal (V
DD
)
p-tub
p+