Low power VLSI Designs for 2_1 Mux with 180nm Technology

S.No
1
2
3
4
5
6
7
8
9

Design Name
Conventional Inverter
Forced Stack
Forced Stack*
Sleep Tranisistor
Sleep Tranisistor*
Sleepy Stack
Sleepy Stack*
Biased Sleep
Biased Sleep*

Static Power

Dyanmic Power

Propagation Delay

1.31E-10
4.53E-11
3.11E-11
3.72E-11
2.12E-11
5.75E-11
4.11E-11
3.05E-11
1.03E-11

1.48E-05
5.23E-06
3.98E-06
7.81E-06
6.89E-06
8.14E-06
7.16E-06
6.51E-06
1.36E-06

2.63E-10
3.97E-10
6.03E-10
3.29E-10
4.22E-10
3.17E-10
3.48E-10
2.74E-10
2.98E-10

Low power VLSI Designs for 2_1 Mux with 130nm Technology
S.No
1
2
3
4
5
6
7
8
9

Design Name
Conventional Inverter
Forced Stack
Forced Stack*
Sleep Tranisistor
Sleep Tranisistor*
Sleepy Stack
Sleepy Stack*
Biased Sleep
Biased Sleep*

Static Power

Dyanmic Power

Propagation Delay

7.07E-09
1.70E-10
4.16E-11
1.69E-10
2.27E-11
3.12E-10
4.80E-11
1.69E-10
1.28E-11

8.27E-06
5.06E-06
3.32E-06
3.57E-06
3.49E-06
3.72E-06
3.25E-06
3.57E-06
1.19E-06

2.58E-10
3.73E-10
5.31E-10
3.24E-10
3.74E-10
3.12E-10
3.24E-10
2.69E-10
2.74E-10

Low power VLSI Designs for 2_1 Mux with 90nm Technology
S.No
1
2
3
4
5
6
7
8
9

Design Name
Conventional Inverter
Forced Stack
Forced Stack*
Sleep Tranisistor
Sleep Tranisistor*
Sleepy Stack
Sleepy Stack*
Biased Sleep
Biased Sleep*

Low power V

Static Power

Dyanmic Power

Propagation Delay

S.No

5.82E-08
1.90E-09
1.47E-10
1.81E-09
1.32E-10
3.45E-09
2.72E-10
2.32E-10
1.76E-11

3.57E-06
8.77E-07
6.97E-07
1.64E-06
1.60E-06
1.51E-06
1.10E-06
1.10E-06
6.12E-07

2.56E-10
3.71E-10
4.97E-10
3.16E-10
3.73E-10
3.09E-10
3.19E-10
2.63E-10
2.65E-10

1
2
3
4
5
6
7
8
9

Low power VLSI Designs for Inverter with 90nm Technology

S.No

Design Name

Static Power

Dyanmic Power

Propagation Delay
tphl

tplh

tp

1
2
3
4
5
6
7
8
9

Conventional Inverter
Forced Stack
Forced Stack*
Sleep Tranisistor
Sleep Tranisistor*
Sleepy Stack
Sleepy Stack*
Biased Sleep
Biased Sleep*

6.38E-09
2.09E-10
1.61E-11
1.99E-10
1.45E-11
3.79E-10
2.99E-11
2.54E-11
1.93E-12

1.27E-06
3.11E-07
2.47E-07
5.83E-07
5.67E-07
5.35E-07
3.90E-07
3.90E-07
2.17E-07

3.84E-11
6.68E-11
1.03E-10
6.76E-11
7.52E-11
3.78E-11
3.98E-11
3.04E-11
1.36E-11

Low power VLSI Designs for 2_1 Mux with 90nm Technology
S.No

Design Name

Static Power

Dyanmic Power

Propagation Delay

1
2
3
4
5
6
7

Conventional Inverter
Forced Stack
Forced Stack*
Sleep Tranisistor
Sleep Tranisistor*
Sleepy Stack
Sleepy Stack*

1.00E+00
3.23E-02
2.48E-03
3.06E-02
2.21E-03
5.86E-02
4.62E-03

1.00E+00
2.41E-01
1.92E-01
4.56E-01
4.42E-01
4.20E-01
3.03E-01

1.00E+00
1.49E+00
1.99E+00
1.26E+00
1.49E+00
1.28E+00
1.23E+00

Biased Sleep

3.90E-03

3.01E-01

1.04E+00

Biased Sleep*

2.98E-04

1.68E-01

1.08E+00

6.85E-11
8.80E-11
1.04E-10
6.42E-11
8.02E-11
9.11E-11
9.31E-11
7.93E-11
9.68E-11

#####
#####
#####
#####
#####
#####
#####
#####
#####

Low power VLSI Designs for 2_1 Mux with 90nm Technology
Design Name
Conventional Inverter
Forced Stack
Forced Stack*
Sleep Tranisistor
Sleep Tranisistor*
Sleepy Stack
Sleepy Stack*
Biased Sleep
Biased Sleep*

Static Power

Dyanmic Power

Propagation Delay

1.00E+00
3.23E-02
2.48E-03
3.06E-02
2.21E-03
5.86E-02
4.62E-03
3.90E-03
2.98E-04

1.00E+00
2.41E-01
1.92E-01
4.56E-01
4.42E-01
4.20E-01
3.03E-01
3.01E-01
1.68E-01

1.00E+00
1.49E+00
1.99E+00
1.26E+00
1.49E+00
1.28E+00
1.23E+00
1.04E+00
1.08E+00

(A) Inverter
Conventional Inverter
Forced Stack
Forced Stack*
Sleep Tranisistor
Sleep Tranisistor*
Sleepy Stack
Sleepy Stack*
Biased Sleep
Biased Sleep*

(B) 2:1 Multiplexer

Conventional Inverter
Forced Stack
Forced Stack*
Sleep Tranisistor
Sleep Tranisistor*
Sleepy Stack
Sleepy Stack*
Biased Sleep
Biased Sleep*

Static Power

Dyanmic Power

Propagation Delay

1.00E+00
3.27E-02
2.52E-03
3.12E-02
2.27E-03
5.93E-02
4.68E-03
3.98E-03
3.02E-04

1.00E+00
2.45E-01
1.95E-01
4.60E-01
4.48E-01
4.22E-01
3.08E-01
3.08E-01
1.71E-01

1.00E+00
1.45E+00
1.94E+00
1.23E+00
1.45E+00
1.21E+00
1.24E+00
1.03E+00
1.03E+00

Static Power

Dyanmic Power

Propagation Delay

1.00E+00
3.23E-02
2.48E-03
3.06E-02
2.21E-03
5.86E-02
4.62E-03
3.90E-03
2.98E-04

1.00E+00
2.41E-01
1.92E-01
4.56E-01
4.42E-01
4.20E-01
3.03E-01
3.01E-01
1.68E-01

1.00E+00
1.49E+00
1.99E+00
1.26E+00
1.49E+00
1.28E+00
1.23E+00
1.04E+00
1.08E+00

Low power VLSI Designs for 2_1 Mux with 180nm Technology
S.No

Design Name

Static Power

Dyanmic Power

Propagation Delay

1
2
3
4
5
6
7
8

Conventional Inverter
Forced Stack
Forced Stack*
Sleep Tranisistor
Sleep Tranisistor*
Sleepy Stack
Sleepy Stack*
Biased Sleep

1.31E-10
4.53E-11
3.11E-11
3.72E-11
2.12E-11
5.75E-11
4.11E-11
3.05E-11

1.48E-05
5.23E-06
3.98E-06
7.81E-06
6.89E-06
8.14E-06
7.16E-06
6.51E-06

2.63E-10
3.97E-10
6.03E-10
3.29E-10
4.22E-10
3.17E-10
3.48E-10
2.74E-10

Biased Sleep*

1.03E-11

1.36E-06

2.98E-10

Low power VLSI Designs for 2_1 Mux with 130nm Technology
S.No

Design Name

1
2
3
4
5
6

Conventional Inverter
Forced Stack
Forced Stack*
Sleep Tranisistor
Sleep Tranisistor*
Sleepy Stack

Sleepy Stack*

Biased Sleep

Biased Sleep*

Static Power

Dyanmic Power

Propagation Delay

7.07E-09
1.70E-10
4.16E-11
1.69E-10
2.27E-11
3.12E-10
4.80E-11

8.27E-06
5.06E-06
3.32E-06
3.57E-06
3.49E-06
3.72E-06
3.25E-06

2.58E-10
3.73E-10
5.31E-10
3.24E-10
3.74E-10
3.12E-10
3.24E-10

1.69E-10
1.28E-11

3.57E-06
1.19E-06

2.69E-10
2.74E-10

Low power VLSI Designs for 2_1 Mux with 90nm Technology
S.No

Design Name

Static Power

Dyanmic Power

Propagation Delay

1
2
3
4

Conventional Inverter
Forced Stack
Forced Stack*
Sleep Tranisistor

5.82E-08
1.90E-09
1.47E-10
1.81E-09

3.57E-06
8.77E-07
6.97E-07
1.64E-06

2.56E-10
3.71E-10
4.97E-10
3.16E-10

5
6
7
8
9

Sleep Tranisistor*
Sleepy Stack
Sleepy Stack*
Biased Sleep
Biased Sleep*

1.32E-10
3.45E-09
2.72E-10
2.32E-10
1.76E-11

1.60E-06
1.51E-06
1.10E-06
1.10E-06
6.12E-07

3.73E-10
3.09E-10
3.19E-10
2.63E-10
2.65E-10

1.49E+01

1.37E+00

1.17E+00

1.55E+01

1.80E+00

8.31E-01

90nm
5.82E-08
1.90E-09
1.47E-10
1.81E-09
1.32E-10
3.45E-09
2.72E-10
2.32E-10
1.76E-11

1.03E-11

1.28E-11

1.76E-11

180nm

130nm

90nm

Conventional Inverter

1.48E-05

8.27E-06

3.57E-06

Forced Stack

5.23E-06

5.06E-06

8.77E-07

Forced Stack*
Sleep Tranisistor
Sleep Tranisistor*
Sleepy Stack
Sleepy Stack*
Biased Sleep
Biased Sleep*
Minimum Power

3.98E-06
7.81E-06
6.89E-06
8.14E-06
7.16E-06
6.51E-06
1.36E-06

3.32E-06
3.57E-06
3.49E-06
3.72E-06
3.25E-06
3.57E-06
1.19E-06

6.97E-07
1.64E-06
1.60E-06
1.51E-06
1.10E-06
1.10E-06
6.12E-07

1.36E-06

1.19E-06

6.12E-07

Propagation Delay
Conventional Inverter
Forced Stack
Forced Stack*
Sleep Tranisistor
Sleep Tranisistor*
Sleepy Stack
Sleepy Stack*
Biased Sleep
Biased Sleep*
Minimum Delay

180nm
2.63E-10
3.97E-10
6.03E-10
3.29E-10
4.22E-10
3.17E-10
3.48E-10
2.74E-10
2.98E-10

130nm
2.58E-10
3.73E-10
5.31E-10
3.24E-10
3.74E-10
3.12E-10
3.24E-10
2.69E-10
2.74E-10

90nm
2.56E-10
3.71E-10
4.97E-10
3.16E-10
3.73E-10
3.09E-10
3.19E-10
2.63E-10
2.65E-10

2.63E-10

2.58E-10

2.56E-10

MAX
5.82E-08

MIN
1.31E-10

1.90E-09
1.47E-10
1.81E-09
1.32E-10
3.45E-09
2.72E-10
2.32E-10
1.76E-11

4.53E-11
3.11E-11
3.72E-11
2.12E-11
5.75E-11
4.11E-11
3.05E-11
1.03E-11

MAX
1.48E-05

MIN
3.57E-06

5.23E-06
3.98E-06

8.77E-07
6.97E-07

7.81E-06
6.89E-06
8.14E-06
7.16E-06
6.51E-06
1.36E-06

1.64E-06
1.60E-06
1.51E-06
1.10E-06
1.10E-06
6.12E-07

MAX

MIN

2.63E-10
3.97E-10
6.03E-10

2.56E-10
3.71E-10
4.97E-10

3.29E-10
4.22E-10
3.17E-10
3.48E-10
2.74E-10
2.98E-10

3.16E-10
3.73E-10
3.09E-10
3.19E-10
2.63E-10
2.65E-10

STATIC POW
POWER IN WATTS

130nm
7.07E-09
1.70E-10
4.16E-11
1.69E-10
2.27E-11
3.12E-10
4.80E-11
1.69E-10
1.28E-11

1.00E-07
1.00E-08
1.00E-09
1.00E-10
1.00E-11

DYNAMIC POW
POWER IN WATTS

Dynamic Power

180nm
1.31E-10
4.53E-11
3.11E-11
3.72E-11
2.12E-11
5.75E-11
4.11E-11
3.05E-11
1.03E-11

1.60E-05
1.40E-05
1.20E-05
1.00E-05
8.00E-06
6.00E-06
4.00E-06
2.00E-06
0.00E+00

TIME IN SECONDS

Static Power
Conventional Inverter
Forced Stack
Forced Stack*
Sleep Tranisistor
Sleep Tranisistor*
Sleepy Stack
Sleepy Stack*
Biased Sleep
Biased Sleep*
Minimum Power

6.00E-10
5.50E-10
5.00E-10
4.50E-10
4.00E-10
3.50E-10
3.00E-10
2.50E-10

STATIC POWER DISSIPATION

180nm

130nm

90nm

DYNAMIC POWER DISSIPATION

180nm

130nm

90nm

PROPAGATION DELAY
180nm

130nm

90nm

Low power VLSI Designs for Inverter with 180nm Technology

S.No
1
2
3
4
5
6
7
8
9

Design Name
Conventional Inverter
Forced Stack
Forced Stack*
Sleep Tranisistor
Sleep Tranisistor*
Sleepy Stack
Sleepy Stack*
Biased Sleep
Biased Sleep*

Static Power

Dyanmic Power

1.43E-11
4.96E-12
3.41E-12
4.08E-12
2.32E-12
6.30E-12
4.51E-12
3.34E-12
1.13E-12

5.23E-06
1.85E-06
1.41E-06
2.77E-06
2.44E-06
2.88E-06
2.54E-06
2.31E-06
4.81E-07

Propagation Delay
tphl
1.21E-11
3.37E-11
8.47E-11
6.86E-11
1.96E-11
1.14E-10
1.61E-11
1.62E-11
1.03E-11

tplh
9.73E-11
1.32E-10
1.67E-10
6.85E-11
1.56E-10
1.81E-11
1.29E-10
9.81E-11
1.19E-10

tp
5.47E-11
8.26E-11
1.26E-10
6.86E-11
8.78E-11
6.61E-11
7.25E-11
5.71E-11
6.47E-11

Low power VLSI Designs for Inverter with 130nm Technology

S.No

Design Name

Static Power

Dyanmic Power

Propagation Delay

1
2
3
4
5
6
7

Conventional Inverter
Forced Stack
Forced Stack*
Sleep Tranisistor
Sleep Tranisistor*
Sleepy Stack
Sleepy Stack*

7.76E-10
1.86E-11
4.56E-12
1.86E-11
2.49E-12
3.42E-11
5.26E-12

2.93E-06
1.79E-06
1.18E-06
1.26E-06
1.24E-06
1.32E-06
1.15E-06

tphl
1.21E-11
3.37E-11
8.47E-11
6.86E-11
1.96E-11
1.14E-10
1.61E-11

tplh
9.53E-11
1.22E-10
1.37E-10
6.65E-11
1.36E-10
1.61E-11
1.19E-10

tp
5.37E-11
7.76E-11
1.11E-10
6.76E-11
7.78E-11
6.51E-11
6.75E-11

Biased Sleep

1.86E-11

1.26E-06

1.62E-11

9.61E-11

5.61E-11

Biased Sleep*

1.41E-12

4.21E-07

1.53E-11

9.91E-11

5.72E-11

Low power VLSI Designs for Inverter with 90nm Technology

S.No

Design Name

Static Power

Dyanmic Power

Propagation Delay

1
2
3
4
5

Conventional Inverter
Forced Stack
Forced Stack*
Sleep Tranisistor
Sleep Tranisistor*

6.38E-09
2.09E-10
1.61E-11
1.99E-10
1.45E-11

1.27E-06
3.11E-07
2.47E-07
5.83E-07
5.67E-07

tphl
3.84E-11
6.68E-11
1.03E-10
6.76E-11
7.52E-11

6
7
8
9

Sleepy Stack
Sleepy Stack*
Biased Sleep
Biased Sleep*

3.79E-10
2.99E-11
2.54E-11
1.93E-12

5.35E-07
3.90E-07
3.90E-07
2.17E-07

3.78E-11
3.98E-11
3.04E-11
1.36E-11

tplh
6.85E-11
8.80E-11
1.04E-10
6.42E-11
8.02E-11

tp
5.34E-11
7.74E-11
1.04E-10
6.59E-11
7.77E-11

9.11E-11
9.31E-11
7.93E-11
9.68E-11

6.44E-11
6.64E-11
5.48E-11
5.52E-11

Static Power
Conventional Inverter
Forced Stack
Forced Stack*
Sleep Tranisistor
Sleep Tranisistor*
Sleepy Stack
Sleepy Stack*
Biased Sleep
Biased Sleep*
Minimum Power

180nm
1.43E-11
4.96E-12
3.41E-12
4.08E-12
2.32E-12
6.30E-12
4.51E-12
3.34E-12
1.13E-12

130nm
7.76E-10
1.86E-11
4.56E-12
1.86E-11
2.49E-12
3.42E-11
5.26E-12
1.86E-11
1.41E-12

90nm
6.38E-09
2.09E-10
1.61E-11
1.99E-10
1.45E-11
3.79E-10
2.99E-11
2.54E-11
1.93E-12

1.13E-12

1.41E-12

1.93E-12

Dynamic Power
Conventional Inverter
Forced Stack
Forced Stack*
Sleep Tranisistor
Sleep Tranisistor*
Sleepy Stack
Sleepy Stack*
Biased Sleep
Biased Sleep*
Minimum Power

180nm
5.23E-06
1.85E-06
1.41E-06
2.77E-06
2.44E-06
2.88E-06
2.54E-06
2.31E-06
4.81E-07

130nm
2.93E-06
1.79E-06
1.18E-06
1.26E-06
1.24E-06
1.32E-06
1.15E-06
1.26E-06
4.21E-07

90nm
1.27E-06
3.11E-07
2.47E-07
5.83E-07
5.67E-07
5.35E-07
3.90E-07
3.90E-07
2.17E-07

4.81E-07

4.21E-07

2.17E-07

Propagation Delay
Conventional Inverter
Forced Stack
Forced Stack*
Sleep Tranisistor
Sleep Tranisistor*
Sleepy Stack
Sleepy Stack*
Biased Sleep
Biased Sleep*
Minimum Delay

180nm
5.47E-11
8.26E-11
1.26E-10
6.86E-11
8.78E-11
6.61E-11
7.25E-11
5.71E-11
6.47E-11

130nm
5.37E-11
7.76E-11
1.11E-10
6.76E-11
7.78E-11
6.51E-11
6.75E-11
5.61E-11
5.72E-11

90nm
5.34E-11
7.74E-11
1.04E-10
6.59E-11
7.77E-11
6.44E-11
6.64E-11
5.48E-11
5.52E-11

5.47E-11

5.37E-11

5.34E-11

MAX
6.38E-09
2.09E-10
1.61E-11
1.99E-10
1.45E-11
3.79E-10
2.99E-11
2.54E-11
1.93E-12

MAX
5.23E-06
1.85E-06
1.41E-06
2.77E-06
2.44E-06
2.88E-06
2.54E-06
2.31E-06
4.81E-07

MAX
5.47E-11
8.26E-11
1.26E-10
6.86E-11
8.78E-11
6.61E-11
7.25E-11
5.71E-11
6.47E-11

6.64E-11
5.34E-11

80.39289
3.90E-07

2.99E-11

2.17E-07

1.93E-12

MIN

STATIC POWER DISSIPATION

180nm
POWER IN WATTS

1.43E-11
4.96E-12
3.41E-12
4.08E-12
2.32E-12
6.30E-12
4.51E-12
3.34E-12
1.13E-12

130nm

90nm

1.00E-08
1.00E-09
1.00E-10
1.00E-11
1.00E-12

MIN

MIN

DYNAMIC POWER DISSIPATION

180nm
POWER IN WATTS

1.27E-06
3.11E-07
2.47E-07
5.83E-07
5.67E-07
5.35E-07
3.90E-07
3.90E-07
2.17E-07

130nm

90nm

1.00E-05

1.00E-06

1.00E-07

5.34E-11
7.74E-11
1.04E-10
6.59E-11
7.77E-11
6.44E-11
6.64E-11
5.48E-11
5.52E-11

PROPAGATION DELAY
TIME IN SECONDS

180nm
1.30E-10
1.20E-10
1.10E-10
1.00E-10
9.00E-11
8.00E-11
7.00E-11
6.00E-11
5.00E-11

130nm

90nm

Static Power
Conventional Inverter
Forced
Stack

180nm
1.43E-11
4.96E-12

130nm
7.76E-10
1.86E-11

Sleep

5.06E-12

2.49E-12

4.51E-12
2.50E-12

3.86E-12
2.51E-12

2.00E-11
4.47E-11
1.89E-11

Dynamic Power
Conventional Inverter
Forced
Stack
Sleep
Tranisistor
Sleepy
Stack
Biased
Sleep

180nm
5.23E-06
1.57E-06
2.44E-06
2.54E-06
2.44E-06

130nm
2.93E-06
5.90E-07
1.11E-06
1.15E-06
1.11E-06

Propagation Delay
Conventional Inverter
Forced
Stack
Sleep
Tranisistor
Sleepy
Stack
Biased
Sleep

180nm
7.184E-11
7.988E-11
6.681E-11
7.113E-11
1.454E-11

130nm
4.09E-11
7.24E-11
5.83E-11
5.62E-11
5.88E-11

Sleepy
Biased

Tranisistor
Stack
Sleep

90nm
2.19E-08
3.12E-10

45nm
1.12E-09
8.05E-12
5.21E-13

32nm
4.22E-12
5.34E-13

1.28E-12
5.37E-13

5.18E-13
1.73E-12
4.91E-13

90nm
5.93E-06
1.02E-06
2.06E-06
2.15E-06
2.06E-06

45nm
1.31E-06
1.86E-07
5.12E-07
5.17E-07
5.12E-07

32nm
2.13E-07
1.08E-07
1.88E-07
1.87E-07
1.87E-07

90nm
2.66E-11
5.21E-11
4.85E-11
4.63E-11
8.77E-11

45nm
2.94E-11
9.15E-11
6.05E-11
5.99E-11
6.05E-11

32nm
2.8086E-10
4.1084E-10
3.7446E-10
3.6518E-10
3.7431E-10

37.2

Active Leakage Active Leakage

Power
Power
Power
Power
3.90E-07 2.99E-11 2.17E-07 1.93E-12
1.10E-06 2.72E-10 6.12E-07 1.76E-11

3.90E-07 0.000039 2.99E-11

0.00011 2.72E-10
1.10E-06
1.49E-04

2.99E-09 2.17E-07 0.0000217

2.72E-08 6.12E-07 0.0000612
3.02E-08
8.29E-05

1.49E-04 3.02E-08
4.47E+00 0.077347

4.47 0.077347 4.547347

8.29E-05 1.953E-09
2.487 0.0050036

2.487 0.0050036 2.492003586

4.55
1.23
30.2439

1.93E-12
1.76E-11

2.49
1.827309

1.93E-10
1.76E-09
1.95E-09

Abbreviations
AUC
BSIM
CMOS
DIBL
EDA
ITRS
MATLAB
MLV
MTCMOS
PTM
SOI
SPICE
Vds
Vgs
Vth
W/L

Full Form
Area Under Curve
Berkeley Short Channel IGFET Model
Complementary Metal Oxide Semiconductor
Drain Induced Barrier Lowering
Electronic Design Automation
International Technology Roadmap for semiconductors
Matrix Laboratory
Minimum Leakage Vector
Multi Theshold CMOS
Predective Technology Model
Silicon on Insulator
Simulation Program with Intergerated Circuit Emphasis
Drain to Source Voltage
Gate to Source Voltage
Threshold Voltage of MOS Transistor
Width/Length ratio of MOS transistor