KECE 463

VLSI
Signal Processing
Laboratory
KECE 463
VLSI Design and Experiment
Lecture 6
KECE 463
VLSI
Signal Processing
Laboratory
2
Assign Statements (continuous assignment)
- Operator types
- Examples
How to reduce clock cycle ?
Pipelining !
negedge
CLOCK
Data combinational
logic
Summary from last Lecture
KECE 463
VLSI
Signal Processing
Laboratory
3
How to reduce clock cycle ?
Pipelining !
# 6 # 3
# 3
a
b
c
# 6 # 3
# 3
a
b
c
Summary from last Lecture
KECE 463
VLSI
Signal Processing
Laboratory
4
Clock Cycle !
Set up & Hold Time !
negedge
CLOCK
Data
combinational
logic
combinational
logic
4.5 ns
7.0 ns
What is the factor
that decide the system clock cycle ?
KECE 463
VLSI
Signal Processing
Laboratory
5
Pipelining 18 bit Ripple Carry Adder
Summary from last Experiments
Clock cycle ?
KECE 463
VLSI
Signal Processing
Laboratory
7. Behavioral Modeling
6
assign statement
KECE 463
VLSI
Signal Processing
Laboratory
7
Summary of this Lecture
Behavioral Modeling
Structured Procedures - initial, always
Blocking & Non-blocking assignments , Timing Control
Conditional Statements - if ,
Multi-way Branching - case , Loops --- next class
How to make a multiplier ?
How to verify the functionality ?
KECE 463
VLSI
Signal Processing
Laboratory
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7. Behavioral Modeling
Very similar to Programming language
- Be careful ! - Always consider the HARDWARE !
7.1 Structured Procedures
KECE 463
VLSI
Signal Processing
Laboratory
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7.1 Structured Procedures
Used for Stimulus not generally used inside module
KECE 463
VLSI
Signal Processing
Laboratory
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7.1 Structured Procedures
Generally used inside combinational or sequential modules.
KECE 463
VLSI
Signal Processing
Laboratory
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7.2 Procedural Assignments
KECE 463
VLSI
Signal Processing
Laboratory
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7.2 Procedural Assignments
Think about Flops !
KECE 463
VLSI
Signal Processing
Laboratory
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7.2 Procedural Assignments
Think about Hardware ! Feedback ?
KECE 463
VLSI
Signal Processing
Laboratory
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7.2 Procedural Assignments
KECE 463
VLSI
Signal Processing
Laboratory
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7.3 Timing Control
?
KECE 463
VLSI
Signal Processing
Laboratory
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7.3 Timing Control
KECE 463
VLSI
Signal Processing
Laboratory
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7.3 Timing Control
<
<
<
<
Think about Flops : RTL
KECE 463
VLSI
Signal Processing
Laboratory
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7.4 Conditional Statements
KECE 463
VLSI
Signal Processing
Laboratory
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7.4 Conditional Statements
KECE 463
VLSI
Signal Processing
Laboratory
20
Summary Behavioral Modeling
Behavioral Modeling
Structured Procedures - initial, always
Blocking & Non-blocking assignments
Timing Control
Conditional Statements - if
KECE 463
VLSI
Signal Processing
Laboratory
21
Process Variations
With Technology Scale down
KECE 463
VLSI
Signal Processing
Laboratory
22
Process Variations
Design Compiler (Synopsys)
lec25dscc25_FF
lec25dscc25_SS
lec25dscc25_TT
Power Grid
Clock !
KECE 463
VLSI
Signal Processing
Laboratory
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Process Variations
V
th
of Transistors varies !
KECE 463
VLSI
Signal Processing
Laboratory
24
Experiment in two weeks ago
0
1
out
Carry Select Adder (16 bit)
a[4] b[4] a[5] b[5] a[6] b[6] a[7] b[7]
sum[4]
sum[5] sum[6] sum[7]
sum[8]
Ripple Carry Adder (16 bit)
KECE 463
VLSI
Signal Processing
Laboratory
Can we speed up the
carry-select-adder ?
Square Root Carry-Select-Adder !
25
KECE 463
VLSI
Signal Processing
Laboratory
Todays Experiment
26
KECE 463
VLSI
Signal Processing
Laboratory
27
Experiments (Multiplier)
12x12 Ripple Carry Multiplier
Think about
Critical Path !!!
KECE 463
VLSI
Signal Processing
Laboratory
How can you be sure that
your Verilog is functionally
working ?
28
KECE 463
VLSI
Signal Processing
Laboratory
29
Test vector verification
Testbench
vector_input_x.dat Generated by C or Matlab
reg [11:0] input_vector_x [0:1023];
reg [11:0] input_vector_y [0:1023];
reg [23:0] output_vector [0:1023];
initial
begin
readmemh ( ./vector_input_x.dat , input_vector_x);
readmemh ( ./vector_input_y.dat , input_vector_y);
readmemh ( ./vector_output.dat , output_vector);
for ( i = 0 ; i < 1024 ; i = i +1)
begin
# 10 data_in_x = input_vector_x [ i];
data_in_y = input_vector_y [ i];
# time
if (z == output_vector[i]) vector_match = 1;
writememh ( ./vector_output.dat , input_vector);
end
end
test_bench
data_in
data_out
module
vector_input_y.dat
vector_output.dat
KECE 463
VLSI
Signal Processing
Laboratory
30
Experiment
Make your OWN Verilog Code !
Practice Design Complier ! Clock change
When you design, always think about Critical Path !
Find the MAXIMUM clock cycle
& corresponding Area