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entity macunit is
clk1,rst1 : in STD_LOGIC;
end macunit;
component pipo
clock : in STD_LOGIC;
rst : in STD_LOGIC;
end component;
component multiplier
end component;
begin
end Behavioral;
entity multiplier is
end multiplier;
component and1
c : out STD_LOGIC);
end component;
component hadder
end component;
component fulladd
end component;
component or1
c1 : out STD_LOGIC);
end component;
begin
n(0)<= r(0);
end Behavioral;
entity and1 is
c : out STD_LOGIC);
end and1;
begin
c<= a and b;
end Behavioral;
entity or1 is
c1 : out STD_LOGIC);
end or1;
begin
c1<= a1 or b1;
end Behavioral;
entity hadder is
end hadder;
begin
su<= i xor j;
ca<= i and j;
end Behavioral;
entity fulladd is
end fulladd;
component and1
c : out STD_LOGIC);
end component;
begin
end Behavioral;
entity pipo is
clock : in STD_LOGIC;
rst : in STD_LOGIC;
end pipo;
component dff
port(data,clk,reset : in STD_LOGIC;
end component;
begin
end Behavioral;
entity dff is
end dff;
begin
process(clk)
begin
end if;
end process;
end Behavioral;
(a)
(b)