A

D
C
L
A
T
C
H
2:1
MUX.
Block diagram of digital Modulation & Demodulation techniques
SW8
SW7
SW5
SW4
I/P
Nibble
4 B I/P
data
Switches
0
1
Voice/
ADC
DECODER
logic for
PSK ,QPSK,
QAMetc
similar
to flowchart
for 16QAM
demodulation,
involving phase
AND/OR
amplitude
Socket
17
7 4
4
TP2 TP3
4
Lower
nibble
Upper
nibble
4
Modulation
Scheme select switch
8
2:1
MUX.
4
4
L
A
T
C
H
D
A
C
8
4
UL Sel
SW3
SW3
0
1
Voice/ADC
Socket
16
4 BIT
4 BIT
Recovered i/p data on
L17(MSB) -L20(LSB)
+
Scheme select on
L14(MSB) -L16(LSB)
7
LSB
LSB
sel
7
LSB
ADC
I/P
sel
LSB
I/P
Nibble
I/P
Nibble
SW3
Data
I/P
7
4
4
MUX
2:1
/ UL
el S ect
SOC
EOC
Received
modulated
data
Decoder
Latch
(H)
Decoder
Latch
(L)
1-7
socket 19
Mod
sel
MUX
2:1
ADC
I/P
sel
LSB NU
MUX
2:1
Demod
P
I
S
O
SIPO
1:2
SIPO
1:4
SIPO
1:1 1
2
4
A (A &A/2)
P (0&180)
A (A &A/2)
P (0&180)
Sin Q Sin Q Sin Q
Sin i
1
1
1 7
7
1
7
7
Mux
2:1
Binary
Adder
Scaling
Divide
by 2
Modulated carrier o/p
5V
Gnd
Socket
19
0
1
scheme
Modula
tion
Demodu
lation
0
1
2:1
MUX.
sel
Non
differen
tial
0
1
Differen
tial
1
1
Q D
Q/
D
F/F
CK
SOCKET 4
Differential
data block
Socket
14,15,18
8
7
7
0
1
2:1
MUX.
sel
Non
differen
tial
0
1
Differen
tial
2:1
MUX.
sel
1
Q
D
Q/
D
F/F
CK
SOCKET 4
1
Differential
data block
Enable
S
I
P
O
PISO
2:1
PISO
4:1
PISO
1:1
1
1
Amplitude
comparator
Phase
comparator
2
Socket 12
FromRef TTL sini
or EXT TTL
clockfromcarrier FG
7
7
7
7
Enable
Socket
15
1
Socket
18
scheme
0
0
1
PSK
QPSK
16QAM
MSK
Socket
14
0
1
1
0
0
0
0
0
0
1
0
1
8PSK
1
1
0
0
1
1 1 1
8QAM
GSK
Reference
TTL sin i
3
7
3
3
1
4
Sini psk
sinQother
1
Socket8 Socket9
Socket11
ADC
Control
Data
clk
1.2
MHz
Clk
E
E
E
GMSK
111
1
3
E
E
E
Tp5
Tp6
7
2
2
SIPO
1:1
1:2
1:4
1:1
1:3
1:3
1:1
1:1
Select
4