La 5831p Unlocked

A
Compal confidential
Low Cost Los Angeles 10AL+
NBWAE LA-5831P Schematics Document

Mobile AMD S1G2
RS780MN & RS780MC / SB700
2009-08-12 Rev. 1.0
Compal Secret Data
Security Classification
2009-02-12
Issued Date
Title
Compal Electronics, Inc.

Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
http://hobi-elektronika.net
A
2009-02-12
Deciphered Date
Date:
Rev
1.0
LA-5831P
Wednesday, August 12, 2009
Sheet
E
of
44
Compal Confidential
Fan Control
Thermal Sensor
ADM1032ARMZ
Dual Channel
uFCPGA-638 Package
File Name : LA-5831P
Memory BUS(DDRII)
AMD S1G2 CPU
page 5
Model Name : NBWAE
Clock Generator
page 7
SLG8SP626
page 16
1.8V DDRII 667/800MHZ
page 5,6,7.8
200pin DDRII-SO-DIMM X2
Hyper Transport Link 2.6GHz

16X16
CRT
page 9,10
BANK 0, 1, 2, 3
ATI
page 17
RTL8103E LAN 10/100M
RS780MN
RS780MC
LCD Conn.
page 18
PCIe port 3
RJ45
page 26
page 26
PCIe 4x
1.5V 2.5GHz(250MB/s)
PCIe Mini Card WLAN

HDMI Conn.
PCIe Port 2
PCIE-Express 4X
USB Port 8
page 19
page 27
page 11,12,13,14.15
A-Link Express II
4X PCI-E
USB/B Right
USB/B Left
USB port 0,1
USB port 2
page 25
USB
page 25
3IN1 Card Reader

RTS5159-VDD
5V 480MHz
Int. Camera
USB port 9
page 18
USB port 4
ATI
page 28
SB700
SATA port 1
5V 1.5GHz(150MB/s)
SATA port 3
5V 1.5GHz(150MB/s)
SATA HDD
page 25
SATA ODD
page 25
page 20,21,22,23,24
3
HD Audio
LPC BUS
3.3V 24.576MHz/48Mhz
3.3V 33 MHz
HDA Codec
ALC272
MDC 1.5 Conn

Debug Port
page 31
ENE KB926D3
page 31
page 29
page 32
RTC CKT.
page 20
RJ11
NBWAE Sub-boards
Power On/Off CKT.
page 33
DC/DC Interface CKT.

4
page 34
Power Circuit DC/DC
Touch Pad
page 33
Power/B
LS-4574P
page 31
SPI ROM
page 31
page 31
MIC Conn
page 30
page 30
page 30
page 30
SPK Conn
page 30
33
page 25
page 35,36,37,38
39,40,41.42
Compal Secret Data
2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Custom
Date:
AMP.
TPA6017
Int. MIC Conn HP Conn
page 33
Cap Sensor/B
LS-5822P page
USB/B
LS-5821P
Int.KBD
Block Diagram
Rev
1.0
LA-5831P
Sheet
E
of
44
DESIGN CURRENT 100mA
B+
+3VL
+5VL
+5VALW
DESIGN CURRENT 5A
+5VS
Ipeak=5A, Imax=3.5A, Iocp min=7.9
SUSP#
N-CHANNEL
SI4800BDY
D
+3VALW
SUSP#
TPS51125RGER
N-CHANNEL
DESIGN CURRENT 5A
+3VS
SI4800BDY
UMA_ENVDD
P-CHANNEL
AO-3413
DESIGN CURRENT 1.0A
+LCD_VDD
DESIGN CURRENT 2A
+1.5VS
+3V_LAN
+2.5VS
SUSP
LDO
APL5331KAC
WOL_EN#
P-CHANNEL
AO-3413
C
LDO
APL5508
POK
+1.2VALW
VLDT_EN
DESIGN CURRENT 4.5A
N-CHANNEL
+1.2V_HT
IRF8113PBF
TPS51124RGER
+NB_CORE (+1.1VS)
SUSP#
CPU_VCORE_ENABLE
Ipeak=18A, Imax=12.6A, Iocp min=30
Ipeak=18A, Imax=12.6A, Iocp min=30
ISL6265
DESIGN CURRENT 4A
+CPU_CORE0
+CPU_CORE1
+VDDNB
SYSON
+1.8V
SUSP#
TPS51117RGYR
N-CHANNEL
DESIGN CURRENT 1A
+1.8VS
DESIGN CURRENT 2A
+0.9V
IRF8113PBF
SYSON#
LDO
APL5331KAC
Compal Secret Data
2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Date:
Custom
4
Power Map
Rev
1.0
LA-5831P
Sheet
1
of
44
Voltage Rails
O : ON
Platform
X : OFF
CPU
S1G2
S1G2
S1G3
S1G3
PUMA@
TIGRIS@
NB
RS780MC
RS780MN
RS880MC
RS880M
SB
SB700
SB700
SB710
SB710
+5VS
power
plane
+3VS
+2.5VS
+1.8VS
State
B+
+5VALW
+1.8V
+3VL
+3VALW
+0.9V
+5VL
+1.2VALW
+RTCVCC
+1.5VS
@ : just reserve , no build
+1.1VS
+1.2V_HT
BTO (Build-To-Order)
+VDDNB
+3V_LAN
Option Table
+CPU_CORE_0
+CPU_CORE_1
Function
Description
Modem
(R)
HDMI
(Y)
Explain
S0
S1
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery

don't exist
BTO
MDC@
CAMERA & MIC
HDMI@
(X)
CAMERA
MIC
CAM@
MIC@
SMBUS Control Table

SOURCE
INVERTER
BATT
HDMI
CEC
CPU
THERMAL
SENSOR
EC_SMB_CK1
SB700 SM Bus0 Address
SB700 SM Bus1 Address

HEX
Address
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
KB926
Device
HEX
Address
Power
Device
+3VS
DDR SO-DIMM 0
A0 H
1010 0000 b
+3VALW
WLAN/WIMAX
I2C_DATA
RS780MC
+3VS
DDR SO-DIMM 1
A4 H
1010 0100 b
DDC_CLK0
RS780MN
+3VS
Clock Generator
D2 H
1101 0010 b
DDC_DATA0
RS780MC
DDC_CLK1
RS780MN
I2C_CLK
DDC_DATA1
SCL0
Power
+3VL
Device
HEX
Smart Battery
Address
16 H
0001 011X b
SCL1
KB926 SM Bus2 Address

Power
+3VS
Device
HEX
Address
CPU_ADM1032-1
98 H
1001 100X b
LCD
DDC
ROM
HDMI
DDC
ROM
NEW
CARD
V
V
RS780MC
SB700
SDA1
SCL2
WLAN
RS780MN
SB700
SDA0
KB926 SM Bus1 Address
I / II
CLK
GEN
KB926
Power
SODIMM
V
V
SB700
SDA2
SCL3
SB700
SDA3
KB926 ESB Address

4
Power
Device
+3VL
Cap. Sensor
HEX
Address
Virtual I2C
Compal Secret Data
2009-02-12
Issued Date
Title
Custom
A
2009-02-12
Deciphered Date
Date:
Notes List
Rev
1.0
LA-5831P
Sheet
E
of
44
+1.2V_HT
VLDT CAP.
Near CPU Socket
250 mil
1
PUMA@
C1
4.7U_0805_10V4Z
TIGRIS@
C1
10U_0805_10V6K
PUMA@
C2
4.7U_0805_10V4Z
TIGRIS@
C2
10U_0805_10V6K
C3
0.22U_0603_16V4Z
C4
0.22U_0603_16V4Z
C5
180P_0402_50V8J
C6
180P_0402_50V8J
<11> H_CADIP[0..15]
<11> H_CADIN[0..15]
H_CADIP[0..15]
H_CADOP[0..15]
H_CADIN[0..15]
H_CADON[0..15]
+1.2V_HT
VLDT=500mA
< From NB >
H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
H_CADOP[0..15]
<11>
H_CADON[0..15]
<11>
JCPUA
HT LINK
D1
D2
D3
D4
VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3
E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5
L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15
<11>
<11>
<11>
<11>
H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1
J3
J2
J5
K5
<11>
<11>
<11>
<11>
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
N1
P1
P3
P4
VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3
AE2
AE3
AE4
AE5
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
+VLDT_B
PUMA@
C7
2 4.7U_0805_10V4Z
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
< VLDT_A & VLDT_B : HyperTransport I/O ring power >
TIGRIS@
C7
10U_0805_10V6K
< To NB >
Y1
W1
Y4
Y3
H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1
<11>
<11>
<11>
<11>
R2
R3
T5
R5
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
<11>
<11>
<11>
<11>
6090022100G_B
< FAN Control Circuit : Vout = 1.6 x Vset >

+5VS
1A
D1
< From EC ><32> EN_DFAN1
10U_0805_10V4Z
1SS355_SOD323-2
U6
1
2
3
4
D2
EN
VIN
VOUT
VSET
GND
GND
GND
GND
8
7
6
5
C9
@
BAS16_SOT23-3
1
2
3
1000P_0402_25V8J
4
5
1
2
3
R12
GND
GND
10K_0402_5%
2
10U_0805_10V4Z
+3VS
JFAN @
+FAN1
1
1
C192
C183
1
+FAN1
ACES_85204-0300N
FAN_SPEED1 <32>
2
APL5607KI-TRG_SO8
4
2009-02-12
2009-02-12
Deciphered Date
Title

AMD CPU S1G3 HT I/F
Custom
A
Compal Secret Data
Issued Date
< To EC >
C8
@
0.01U_0402_25V7K
Date:
Rev
1.0
LA-5831P
Sheet
E
of
44
< Processor DDR2 Memory Interface >
+1.8V
< DDR2 VREF is 0.5 ratio >
< PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH >

DDR_A_CLK0
< From/To SO_DIMMB >

1
C10
C14
R1
DDR_A_CLK#0 2
1K_0402_1%
1.5P_0402_50V9C
DDR_B_CLK#0 2
1.5P_0402_50V9C
+MCH_REF
R2
1K_0402_1%
1
C12
0.1U_0402_16V7K
DDR_A_CLK1
C13
DDR_B_CLK1
1
C11
C15
1000P_0402_25V8J
DDR_A_CLK#1 2
1.5P_0402_50V9C
DDR_B_CLK#1 2
+0.9V
1.5P_0402_50V9C
+0.9V
JCPUB
Place them close to CPU within 1"
+1.8V
R4 1
R3 1
2 39.2_0402_1%
2 39.2_0402_1%
T2
MEM_P
MEM_N
<10> DDR_A_ODT0
VTT1
VTT2
VTT3
VTT4
AF10
AE10
MEMZP
MEMZN
H16
PAD
< To SO_DIMMA > <10> DDR_A_ODT1
D10
C10
B10
AD10
DDR_A_ODT0
DDR_A_ODT1
T19
V22
U21
V19
< To SO_DIMMA > <10> DDR_CS1_DIMMA#
DDR_CS0_DIMMA# T20
DDR_CS1_DIMMA# U19
U20
V20
<10> DDR_CKE0_DIMMA
DDR_CKE0_DIMMA J22
DDR_CKE1_DIMMA J20
<10> DDR_CS0_DIMMA#
< To SO_DIMMA > <10> DDR_CKE1_DIMMA
<10> DDR_A_CLK0
< To SO_DIMMA > <10> DDR_A_CLK#0

<10> DDR_A_CLK1
<10> DDR_A_CLK#1
< To SO_DIMMA > <10> DDR_A_MA[15..0]

3
<10> DDR_A_BS#0
< To SO_DIMMA > <10> DDR_A_BS#1

<10> DDR_A_BS#2
< To SO_DIMMA >
<10> DDR_A_RAS#
<10> DDR_A_CAS#
<10> DDR_A_WE#
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
N19
N20
E16
F16
Y16
AA16
P19
P20
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2
R20
R23
J21
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
R19
T22
T24
MEM:CMD/CTRL/CLK VTT5
VTT6
VTT7
VTT8
VTT9
RSVD_M1
MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1
MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1
MA_CKE0
MA_CKE1
MA_CLK_H0
MA_CLK_L0
MA_CLK_H1
MA_CLK_L1
MA_CLK_H2
MA_CLK_L2
MA_CLK_H3
MA_CLK_L3
VTT_SENSE
MEMVREF
RSVD_M2
MB0_ODT0
MB0_ODT1
MB1_ODT0
MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
MB_CKE0
MB_CKE1
MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1
MB_CLK_H2
MB_CLK_L2
MB_CLK_H3
MB_CLK_L3
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
MA_BANK0
MA_BANK1
MA_BANK2
MB_BANK0
MB_BANK1
MB_BANK2
MA_RAS_L
MA_CAS_L
MA_WE_L
MB_RAS_L
MB_CAS_L
MB_WE_L
W10
AC10
AB10
AA10
A10
< VTT regulator voltage >
Y10
VTT_SENSE
W17
+MCH_REF
B18
W26
W23
Y26
DDR_B_ODT0
DDR_B_ODT1
V26
W25
U22
DDR_CS0_DIMMB#
DDR_CS1_DIMMB#
J25
H26
DDR_CKE0_DIMMB
DDR_CKE1_DIMMB
P22
R22
A17
A18
AF18
AF17
R26
R25
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1
P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
R24
U26
J26
DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2
U25
U24
U23
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
JCPUC
<9> DDR_B_D[63..0]
DDR_B_CLK0
1
PAD
T1
PAD
T3
DDR_B_ODT0 <9>
DDR_B_ODT1 <9>
< To SO_DIMMB >
DDR_CS0_DIMMB# <9>
DDR_CS1_DIMMB# <9> <
To SO_DIMMB >
DDR_CKE0_DIMMB <9>
DDR_CKE1_DIMMB <9> <
To SO_DIMMB >
DDR_B_CLK0 <9>
DDR_B_CLK#0 <9>
DDR_B_CLK1 <9>
DDR_B_CLK#1 <9>
< To SO_DIMMB >

<9> DDR_B_DM[7..0]
DDR_B_MA[15..0] <9>
< To SO_DIMMB >
< To SO_DIMMB >
DDR_B_BS#0 <9>
DDR_B_BS#1 <9>
DDR_B_BS#2 <9>
< To SO_DIMMB >
DDR_B_RAS# <9>
DDR_B_CAS# <9>
DDR_B_WE# <9>
< To SO_DIMMB >
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7
MEM:DATA
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
A12
B16
A22
E25
AB26
AE22
AC16
AD12
DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7
C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12
< From/To SO_DIMMB >
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
6090022100G_B
G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
E12
C15
E19
F24
AC24
Y19
AB16
Y13
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_D[63..0]
<10>
< From/To SO_DIMMA >
DDR_A_DM[7..0]
<10>
< To SO_DIMMA >
DDR_A_DQS0 <10>
DDR_A_DQS#0 <10>
DDR_A_DQS1 <10>
DDR_A_DQS#1 <10>
DDR_A_DQS2 <10>
DDR_A_DQS#2 <10>
DDR_A_DQS3 <10>
DDR_A_DQS#3 <10>
DDR_A_DQS4 <10>
DDR_A_DQS#4 <10>
DDR_A_DQS5 <10>
DDR_A_DQS#5 <10>
DDR_A_DQS6 <10>
DDR_A_DQS#6 <10>
DDR_A_DQS7 <10>
DDR_A_DQS#7 <10>
< From/To SO_DIMMA >
Compal Secret Data
2009-02-12
Issued Date
Title

AMD CPU S1G3 DDRII I/F
Custom
A
2009-02-12
Deciphered Date
Date:
Rev
1.0
LA-5831P
Sheet
E
of
44
JCPUD
< Close to CPU >
+CPU_CORE_0
1
R487
10_0402_5%
R486
10_0402_5%
PUMA@
R489
10_0402_5%
R488
10_0402_5%
F8
F9
VDDA1
VDDA2
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
A9
A8
CLKIN_H
CLKIN_L
LDT_RST#
H_PWRGD
LDT_STOP#
CPU_LDT_REQ_R#
B7
A7
F10
C6
CPU_VDD0_RUN_FB_L
Un-Mount R488 & R489 For Caspian
+CPU_CORE_1
+2.5VDDA
CPU_VDD0_RUN_FB_H
< Sideband-Temperature Sensor Interface Clock & Data>
AF4
AF5
AE6
CPU_VDD1_RUN_FB_H
< Sideband-Temperature Sensor Interface interrupt >
PUMA@
CPU_VDD1_RUN_FB_L
< Compensation Resistor to VSS >

< Compensation Resistor to VLDT >
R13
R14
+1.2V_HT
2 44.2_0402_1%
2 44.2_0402_1%
1
1
<42> CPU_VDD0_RUN_FB_H
<42> CPU_VDD0_RUN_FB_L
< 200-MHz PLL Reference Clock >

1
<16> CLK_CPU_BCLK
C20
2 3900P_0402_50V7K
CPU_CLKIN_SC_P
< Debug ready >
T9
T10
T11
T12
T19
< JTAG debug port >
R8
169_0402_1%
Address:100_1100
CPU_VDD0_RUN_FB_H
CPU_VDD0_RUN_FB_L
F6
E6
CPU_VDD1_RUN_FB_H
CPU_VDD1_RUN_FB_L
Y6
AB6
PAD
PAD
PAD
PAD
PAD
2
<16> CLK_CPU_BCLK#
R6
P6
CPU_TEST23_TSTUPD
C21
2 3900P_0402_50V7K
CPU_HTREF0
CPU_HTREF1
CPU_CLKIN_SC_N
Place close to CPU wihtin 1.5"
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
< Filtered PLL Supply Voltage >

+2.5VS
+2.5VDDA
VDDA=300mA
L1 1
2
2 FBM_L11_201209_300L_0805
1
C17
1
+ C16
@
100U_D2_10VM
2
C124
@
0.1U_0402_16V7K
4.7U_0805_10V4Z
+2.5VDDA
1
C18
3300P_0402_50V7K
C19
2 R25
0_0402_5%
THERMDC
THERMDA
VDDIO_FB_H
VDDIO_FB_L
VDD1_FB_H
VDD1_FB_L
VDDNB_FB_H
VDDNB_FB_L
TEST23
H10
G9
TEST18
TEST19
CPU_SVC
R23
1 1K_0402_5%
CPU_SVD
AF6 CPU_THERMTRIP#_R
AC7 CPU_PROCHOT#_1.8
R42
AA8
2
1
PUMA@
300_0402_5%
W7
W8
A3
A5
B3
B5
C1
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
< Thermal Sensor Trip output >

< HTC-active state indication or command >
+1.8V
1
< Thermal diode cathode & anode >
W9
Y9
PAD
PAD
E10
CPU_DBREQ#
TDO
AE9
< Debug request >
TEST17
TEST16
TEST15
TEST14
D7
E7
F7
C7
CPU_TEST17_BP3
CPU_TEST16_BP2
TEST7
TEST10
C3
K8
C4
TEST29_H
TEST29_L
C9
C8
RSVD10
RSVD9
RSVD8
RSVD7
RSVD6
< Differential feedback for VDDIO >

< VDDIO : DDR SDRAM I/O ring power supply>
< Differential feedback for VDDNB >
PAD T20
CPU_TEST28_H_PLLCHRZ_P
CPU_TEST28_L_PLLCHRZ_N
TEST8
T22
T21
CPU_VDDNB_RUN_FB_H <42>< Northbridge power supply >

CPU_VDDNB_RUN_FB_L <42>
J7
H8
TEST28_H
TEST28_L
TEST21
TEST20
TEST24
TEST22
TEST12
TEST27
TEST9
TEST6
< Serial VID Interface clock & data >
THERMDC_CPU
THERMDA_CPU
DBREQ_L
TEST25_H
TEST25_L
C2
AA6
CPU_SVC <42>
CPU_SVD <42>
CPU_VDDNB_RUN_FB_H
CPU_VDDNB_RUN_FB_L
PAD
PAD
T5
T6
PAD
PAD
T7
T8
route as differential
as short as possible
testpoint under package
R32
1 300_0402_5% +1.2V_HT
CPU_TEST10_ANALOGOUT 2
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N
PAD
PAD
T13
T14
H18
H19
AA7
D5
C5
6090022100G_B
0718 AMD --> 1K ohm
R22
1 1K_0402_5%
CPU_SVC
CPU_SVD
H6
G6
< Serial VID Interface clock & data >

+1.8VS
A6
A4
+1.8V sense no support
VDD0_FB_H
VDD0_FB_L
AD7
AB8
AF7
AE7
AE8
AC8
AF8
THERMTRIP_L
PROCHOT_L
MEMHOT_L
M11
W18
HT_REF0
HT_REF1
DBRDY
TMS
TCK
TRST_L
TDI
E9
E8
SVC
SVD
SIC
SID
ALERT_L
G10
AA9
AC9
AD9
AF9
0.22U_0603_16V4Z
For EMI
RESET_L
PWROK
LDTSTOP_L
LDTREQ_L
KEY1
KEY2
< HDT Connector >

JP3
< R41 Close to CPU > < R494 Close to CPU >
1
3
5
7
9
11
13
15
17
19
21
23
CPU_DBREQ#
+1.8VS
+1.8V
T23 PAD
R15
300_0402_5%
LDT_RST#
+1.8V
T24 PAD
LDT_RST#
C22
2
2
2
2
R493
510_0402_5%
R965
2 510_0402_5%
1
<12,20> LDT_STOP#
CPU_TEST25_H_BYPASSCLK_H
R966
510_0402_5%
CPU_TEST25_L_BYPASSCLK_L
TIGRIS@
R492
1
2 510_0402_5%
LDT_STOP#
C23
C25
+1.8V
< To power circuitry>
R10
10K_0402_5%
1
D12
2 CH751H-40PT_SOD323-2
D16
2 CH751H-40PT_SOD323-2
@
0.1U_0402_16V7K
0.01U_0402_25V7K
2
R5
300_0402_5%
< Thermal Sensor >
<36,38>
+3VS
1
Q3
CPU_THERMTRIP#_R
ENTRIP2
< To SB710 ACPI block>
H_THERMTRIP# <21>
C26
0.1U_0402_16V7K
MMBT3904_NL_SOT23-3
THERMDA_CPU
THERMDC_CPU
2 C27
2200P_0402_50V7K
3
4
< noise filter cap >
R30
PUMA@
CPU_LDT_REQ#
1
1
C24
4
@
330P_0402_50V7K
R967
2 0_0402_5%
Add R29 and R31 for Caspian

CPU_LDT_REQ_R#
TIGRIS@
R968
2
1 300_0402_5%
CPU_TEST20_SCANCLK2
TIGRIS@
R969
1
2 300_0402_5%
CPU_TEST23_TSTUPD
R26
1 300_0402_5%
CPU_TEST21_SCANEN
R28
2 300_0402_5%
CPU_TEST24_SCANCLK1
Un-Mount R27 For Caspian
< To SB700 CPU block>
@
CPU_PROCHOT#_1.8
R11
2 0_0402_5%
A
+VDDNB
VDD
SCLK
D+
SDATA
D-
ALERT#
THERM#
GND
EC_SMB_CK2
EC_SMB_DA2
Close to CPU
R484
1 10_0402_5% CPU_VDDNB_RUN_FB_H
R485
1 10_0402_5% CPU_VDDNB_RUN_FB_L
Compal Secret Data

2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title

AMD CPU S1G3 CTRL
Date:
EC_SMB_DA2 <32>
Custom
H_PROCHOT# <20>
EC_SMB_CK2 <32>
ADM1032ARM-1 ZREEL_MSOP8
< Differential feedback for VDDNB >
R9
2 300_0402_5%
< From EC >
U2
B
300_0402_5%
SAMTEC_ASP-68200-07
300_0402_5%
H_PWRGD
+1.8VS
+1.8V
LDT_RST#
R36
<12,20> CPU_LDT_REQ#
R494
2 0_0402_5%
220_0402_5%
220_0402_5%
220_0402_5%
220_0402_5%
NOTE: HDT TERMINATION IS REQUIRED FOR REV. Ax SILICON ONLY.
2
1
1
1
1
1
+1.8V
TIGRIS@
1
2
300_0402_5%
R40
R39
R38
R37
+1.8VS
R21
2 300_0402_5%
0.01U_0402_25V7K
+1.8VS
<20,42> H_PWRGD
@
@
@
@
+1.8V
Add R497 and R500 for Caspian
<20>
R41
@
2
4
6
8
10
12
14
16
18
20
22
24
26
Rev
1.0
LA-5831P
Sheet
E
of
44
JCPUE
+CPU_CORE_0
VDD decoupling : +CPU_CORE

+CPU_CORE_0
+CPU_CORE_0
330U_X_2VM_R6M
C30
+VDDNB
G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11
VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23
+1.8V
K16
M16
P16
T16
V16
VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
+CPU_CORE_0
C32
C33
C34
C35
C40
C41
C42
C28
330U_X_2VM_R6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
Under CPU Socket
Near CPU Socket
0.22U_0603_16V4Z
0.01U_0402_25V7K
180P_0402_50V8J
Under CPU Socket
+CPU_CORE_1
+CPU_CORE_1
330U_X_2VM_R6M
C31
+CPU_CORE_1
C36
C37
C38
C39
C43
C44
C45
C29
330U_X_2VM_R6M
Near CPU Socket
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
Under CPU Socket
0.22U_0603_16V4Z
0.01U_0402_25V7K
180P_0402_50V8J
Under CPU Socket
VDDIO decoupling : DDR SDRAM I/O ring power

+1.8V
C46
22U_0805_6.3V6M
C47
22U_0805_6.3V6M
C48
0.22U_0603_16V4Z
C49
0.22U_0603_16V4Z
C50
180P_0402_50V8J
C51
180P_0402_50V8J
Under CPU Socket

+1.8V
6090022100G_B
2
C55
0.22U_0603_16V4Z
C56
0.22U_0603_16V4Z
C57
0.22U_0603_16V4Z
@
C58
0.22U_0603_16V4Z
AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4
+1.8V
C60
0.01U_0402_25V7K
C61
0.01U_0402_25V7K
Between CPU Socket and DIMM
+1.8V
180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch>
C62
180P_0402_50V8J
C63
180P_0402_50V8J
C64
180P_0402_50V8J
C65
180P_0402_50V8J

+1.8V
Change to B2 size
1
1
C74
4.7U_0805_10V4Z
C75
4.7U_0805_10V4Z
C76
4.7U_0805_10V4Z
C77
4.7U_0805_10V4Z
+ C78
220U_B2_4VM_R45M
2
+0.9V
VTT decoupling.
C66
4.7U_0805_10V4Z
C67
4.7U_0805_10V4Z
C68
0.22U_0603_16V4Z
C69
0.22U_0603_16V4Z
C70
1000P_0402_25V8J
C71
1000P_0402_25V8J
C72
180P_0402_50V8J
C73
180P_0402_50V8J
Near CPU Socket Right side
+0.9V
1. Near Power Supply

2. Change to B2 size
+0.9V
+ C59
220U_B2_4VM_R45M
1
C79
4.7U_0805_10V4Z
C80
4.7U_0805_10V4Z
C81
0.22U_0603_16V4Z
C82
0.22U_0603_16V4Z
C83
1000P_0402_25V8J
C84
1000P_0402_25V8J
C85
180P_0402_50V8J
C86
180P_0402_50V8J
Near CPU Socket Left side

4
+VDDNB decoupling : Northbridge power
Add 22uF for Caspaian
+VDDNB
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
6090022100G_B
@
C52
22U_0805_6.3V6M
C53
22U_0805_6.3V6M
P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2
VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13
Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18
+1.8V
Athlon 64 S1 Processor Socket
C54
2009-02-12
Issued Date
22U_0805_6.3V6M
2 TIGRIS@
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
2009-02-12
Deciphered Date
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
Athlon 64 S1 Processor Socket
Compal Secret Data
Title

AMD CPU S1G3 PWR & GND
Custom
A
VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26
JCPUF
+CPU_CORE_1
Date:
Rev
1.0
LA-5831P
Sheet
E
of
44
DDR_B_D[0..63]
+1.8V
DDR_B_D[0..63]
+1.8V
DDR_B_DM[0..7]
<10> +V_DDR_MCH_REF
C104
1000P_0402_25V8J
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
DDR_B_D0
DDR_B_D1
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
<6>
+1.8V
+0.9V
DDR_B_MA[0..15] <6>
DDR_B_DQS#[0..7]
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
<6>
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
DDR_B_DM[0..7] <6>
DDR_B_DQS[0..7]
JDDRH
DDR_B_DQS#[0..7]
DDR_B_D4
DDR_B_D5
<6>
RP8
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_RAS#
1
2
3
4
DDR_B_DM0
8
7
6
5
C105 2
1 0.1U_0402_16V7K
C106 2
1 0.1U_0402_16V7K
C108 2
1 0.1U_0402_16V7K
C107 2
1 0.1U_0402_16V7K
C109 2
1 0.1U_0402_16V7K
C110 2
1 0.1U_0402_16V7K
C111 2
1 0.1U_0402_16V7K
C112 2
1 0.1U_0402_16V7K
C114 2
1 0.1U_0402_16V7K
C113 2
1 0.1U_0402_16V7K
C116 2
1 0.1U_0402_16V7K
C115 2
1 0.1U_0402_16V7K
C118 2
1 0.1U_0402_16V7K
C117 2
1 0.1U_0402_16V7K
47_0804_8P4R_5%
DDR_B_D6
DDR_B_D7
RP9
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_D12
DDR_B_D13
1
2
3
4
DDR_B_DM1
8
7
6
5
47_0804_8P4R_5%
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK0 <6>
DDR_B_CLK#0 <6>
RP10
DDR_CKE0_DIMMB 8
DDR_B_BS#2
7
DDR_B_MA15
6
DDR_CKE1_DIMMB 5
DDR_B_D14
DDR_B_D15
1
2
3
4
47_0804_8P4R_5%
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
2
DDR_B_DM3
DDR_B_D26
DDR_B_D27
<6> DDR_CKE0_DIMMB
<6> DDR_B_BS#2
DDR_CKE0_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
<6> DDR_B_BS#0
<6> DDR_B_WE#
<6> DDR_B_CAS#
<6> DDR_CS1_DIMMB#
<6> DDR_B_ODT1
DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS1_DIMMB#
DDR_B_ODT1
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
4
<10,16,21> SMB_CK_DAT0
<10,16,21> SMB_CK_CLK0
+3VS
SMB_CK_DAT0
SMB_CK_CLK0
1
DDR_B_D20
DDR_B_D21
RP11
DDR_B_MA3
DDR_B_MA8
DDR_B_MA12
DDR_B_MA9
DDR_B_DM2
DDR_B_D22
DDR_B_D23
1
2
3
4
47_0804_8P4R_5%
RP12
DDR_B_D28
DDR_B_D29
DDR_B_BS#0
DDR_B_MA10
DDR_B_MA1
DDR_B_MA5
DDR_B_DQS#3
DDR_B_DQS3
8
7
6
5
1
2
3
4
47_0804_8P4R_5%
DDR_B_D30
DDR_B_D31
RP13
DDR_CKE1_DIMMB
DDR_CS1_DIMMB#
DDR_B_ODT1
DDR_B_CAS#
DDR_B_WE#
DDR_CKE1_DIMMB <6>
DDR_B_MA15
DDR_B_MA14
8
7
6
5
1
2
3
4
47_0804_8P4R_5%
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
RP14
DDR_B_BS#1
DDR_CS0_DIMMB#
DDR_B_MA13
DDR_B_ODT0
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
1
2
3
4
8
7
6
5
47_0804_8P4R_5%
DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#
DDR_B_BS#1 <6>
DDR_B_RAS# <6>
DDR_CS0_DIMMB# <6>
DDR_B_ODT0
DDR_B_MA13
DDR_B_ODT0 <6>
DDR_B_D36
DDR_B_D37
DDR_B_DM4
3
For EMI
DDR_B_D38
DDR_B_D39
+1.8V
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_CLK1
DDR_B_CLK#1
DDR_B_CLK1 <6>
DDR_B_CLK#1 <6>
DDR_B_DM6
1 @
C120
1 @
C121
1 @
C122
1 @
C123
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
4
+3VS
C119
0.1U_0402_16V7K
P-TWO_A5692B-A0G16-P
@
DIMM0 STD H:9.2mm (Bot)
Compal Secret Data
2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title

DDRII SO-DIMM 0
Custom
A
8
7
6
5
0.1U_0402_16V7K
DDR_B_D50
DDR_B_D51
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
0.1U_0402_16V7K
DDR_B_DQS#6
DDR_B_DQS6
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
0.1U_0402_16V7K
DDR_B_D48
DDR_B_D49
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
0.1U_0402_16V7K
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DDR_B_D16
DDR_B_D17
Date:
Rev
1.0
LA-5831P
Sheet
E
of
44
+1.8V
R43
1K_0402_1%
1
DDR_A_D[0..63]
+V_DDR_MCH_REF
<9> +V_DDR_MCH_REF
2
0.1U_0402_16V7K
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
C95
1000P_0402_25V8J
DDR_A_MA[0..15]
R44
1K_0402_1%
C96
+1.8V
+1.8V
DDR_A_DQS#[0..7]
DDR_A_D[0..63]
<6>
DDR_A_DM[0..7] <6>
DDR_A_DQS[0..7]
<6>
DDR_A_MA[0..15] <6>
1
DDR_A_DQS#[0..7]
<6>
JDDRL
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
DDR_A_D0
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
<6> DDR_CKE0_DIMMA
DDR_A_BS#2
<6> DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
<6> DDR_A_BS#0
<6> DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
<6> DDR_A_CAS#
<6> DDR_CS1_DIMMA#
3
DDR_A_ODT1
<6> DDR_A_ODT1
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
4
DDR_A_DM7
DDR_A_D58
DDR_A_D59
SMB_CK_DAT0
SMB_CK_CLK0
<9,16,21> SMB_CK_DAT0
<9,16,21> SMB_CK_CLK0
+3VS
A
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDR_A_D4
DDR_A_D5
DDR_A_DM0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR_A_DM1
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_MA6
DDR_A_MA14
DDR_A_MA7
DDR_A_MA11
1
2
3
4
DDR_A_D30
DDR_A_D31
DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_BS#1
DDR_A_MA2
DDR_A_MA0
DDR_A_MA4
47_0804_8P4R_5%
RP3
1
8
2
7
3
6
4
5
DDR_A_MA5
DDR_A_MA8
DDR_A_MA9
DDR_A_MA12
47_0804_8P4R_5%
RP4
8
1
7
2
6
3
5
4
DDR_A_BS#0
DDR_A_MA10
DDR_A_MA3
DDR_A_MA1
47_0804_8P4R_5%
RP5
8
1
7
2
6
3
5
4
DDR_A_ODT1
DDR_CS1_DIMMA#
DDR_A_CAS#
DDR_A_WE#
47_0804_8P4R_5%
RP6
8
1
7
2
6
3
5
4
DDR_A_MA13
DDR_A_ODT0
DDR_A_RAS#
DDR_CS0_DIMMA#
47_0804_8P4R_5%
RP7
1
8
2
7
3
6
4
5
DDR_CKE1_DIMMA <6>
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
DDR_A_ODT0
DDR_A_MA13
DDR_A_BS#1 <6>
DDR_A_RAS# <6>
DDR_CS0_DIMMA# <6>
DDR_A_ODT0 <6>
8
7
6
5
47_0804_8P4R_5%
RP2
8
1
7
2
6
3
5
4
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D36
DDR_A_D37
C87
2 0.1U_0402_16V7K
C88
2 0.1U_0402_16V7K
C90
2 0.1U_0402_16V7K
C89
2 0.1U_0402_16V7K
C91
2 0.1U_0402_16V7K
C92
2 0.1U_0402_16V7K
C93
2 0.1U_0402_16V7K
C94
2 0.1U_0402_16V7K
C98
2 0.1U_0402_16V7K
C97
2 0.1U_0402_16V7K
C100 1
2 0.1U_0402_16V7K
C99
2 0.1U_0402_16V7K
C102 1
2 0.1U_0402_16V7K
C101 1
2 0.1U_0402_16V7K
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_CLK1
DDR_A_CLK#1
DDR_A_CLK1 <6>
DDR_A_CLK#1 <6>
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
4
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
PTI_A5652D-A0G16-P
@
DIMM0 STD H:5.2mm (Bot)
Compal Secret Data
2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Custom
Date:
47_0804_8P4R_5%
DDR_A_DM4
C103
0.1U_0402_16V7K
RP1
DDR_A_DM2
DDR_CKE1_DIMMA
+1.8V
+0.9V
DDR_A_CLK0 <6>
DDR_A_CLK#0 <6>
DDRII SO-DIMM 1
Rev
1.0
LA-5831P
Sheet
E
10
of
44
U3B
< To WLAN >

< To LAN >
<27>
<27>
<26>
<26>
PCIE_PTX_C_IRX_P2
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P3
PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P2
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P3
PCIE_PTX_C_IRX_N3
< From SB710 : x4 PCIE A-link >
<20>
<20>
<20>
<20>
<20>
<20>
<20>
<20>
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N
AE3
AD4
AE2
AD3
AD1
AD2
V5
W6
U5
U6
U8
U7
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N
AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
PART 2 OF 6
PCIE I/F GFX
D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3
PCIE I/F GPP
PCIE I/F SB
A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2
PCIE_ITX_PRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P3
PCIE_ITX_PRX_N3
C156
C157
C158
C159
1
1
1
1
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5
SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
SB_TX1N_C
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C
C162
C163
C164
C165
C166
C168
C169
C167
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
AC8
AB8
PCIE_CALRP
PCIE_CALRN
PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)
RS780M_FCBGA528
HDMI_TXD2+
HDMI_TXD2HDMI_TXD1+
HDMI_TXD1HDMI_TXD0+
HDMI_TXD0HDMI_CLK0+
HDMI_CLK0-
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
HDMI_TXD2+
HDMI_TXD2HDMI_TXD1+
HDMI_TXD1HDMI_TXD0+
HDMI_TXD0HDMI_CLK0+
HDMI_CLK0-
<19>
<19>
<19>
<19>
<19>
<19>
<19>
<19>
< If integrated GFX is used, some PCIE pairs are used as HDMI signal pairs >
RS880M Display Port Support (muxed on GFX)
DP0
GFX_TX0,TX1,TX2 and TX3 AUX0 and HPD0
DP1
GFX_TX4,TX5,TX6 and TX7 AUX1 and HPD1
PCIE_ITX_C_PRX_P2
PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_P3
PCIE_ITX_C_PRX_N3
<27>
<27><
<26>
<26><
To WLAN >
To LAN >
R55
R56
1
1
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
1.27K_0402_1%
2K_0402_1%
2
2
<20>
<20>
<20>
<20>
<20>
<20>
<20>
<20>
< To SB710 : x4 PCEI A-link>
< TX Impedance Calibration. Connect to GND >

< RX Impedance Calibration. Connect to VDDPCIE >
+1.1VS
RS780MCR3@
U3A
H_CADON[0..15]
H_CADOP[0..15]
<5>
H_CADON[0..15]
<5>
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
< From S1G3 CPU : x16 HT>
<5>
<5>
<5>
<5>
H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1
<5>
<5>
<5>
<5>
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
301_0402_1%1
Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
2 R57
PART 1 OF 6
AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N
H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1
T22
T23
AB23
AA22
HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
M22
M23
R21
R20
HT_RXCALP
HT_RXCALN
C23
A24
D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22
H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
H24
H25
L21
L20
H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1
M24
M25
P19
R18
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
B24
B25
HT_TXCALP
HT_TXCALN
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
HT_RXCALP
HT_RXCALN
HT_TXCALP
HT_TXCALN
RS780M_FCBGA528
0718 Place within 1"

layout 1:2
HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N
HYPER TRANSPORT CPU I/F
H_CADOP[0..15]
RS780MCR3@
H_CADIN[0..15]
H_CADIP[0..15]
<5>
H_CADIN[0..15]
<5>
< To S1G3 CPU : x16 HT>
H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1
<5>
<5>
<5>
<5>
H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1
<5>
<5>
<5>
<5>
R58
2 301_0402_1%
< Transmitter Calibration Resistor to HT_TXCALN >
0718 Place within 1"

layout 1:2
Compal Secret Data
2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title

RS780M HT / PCIE
Custom
A
H_CADIP[0..15]
Date:
Rev
1.0
LA-5831P
Sheet
E
11
of
44
UMA_CRT_R
<17> UMA_CRT_R
UMA_CRT_G
<17> UMA_CRT_G
UMA_CRT_B
<17> UMA_CRT_B
UMA_CRT_HSYNC
UMA_CRT_VSYNC
UMA_CRT_CLK
UMA_CRT_DATA
UMA_CRT_HSYNC
UMA_CRT_VSYNC
UMA_CRT_CLK
UMA_CRT_DATA
R65 1
2
R71
4.7K_0402_5%
1
RED(DFT_GPIO0)
REDb(NC)
GREEN(DFT_GPIO1)
GREENb(NC)
BLUE(DFT_GPIO3)
BLUEb(NC)
A11
B11
F8
E8
DAC_HSYNC(PWM_GPIO4)
DAC_VSYNC(PWM_GPIO6)
DAC_SCL(PCE_RCALRN)
DAC_SDA(PCE_TCALRN)
G14
+VDDA18HTPLL
H17
VDDA18HTPLL
+VDDA18PCIEPLL
D7
E7
VDDA18PCIEPLL1
VDDA18PCIEPLL2
NB_RESET#
2 0_0402_5%
NB_PWRGD
LDT_STOP#
CPU_LDT_REQ#
D8
A10
C10
C12
SYSRESETb
POWERGOOD
LDTSTOPb
ALLOW_LDTSTOP
CLK_NBHT
CLK_NBHT#
C25
C24
HT_REFCLKP
HT_REFCLKN
NB_OSC_14.318M
E11
F11
REFCLK_P/OSCIN(OSCIN)
REFCLK_N(PWM_GPIO3)
<16> NB_OSC_14.318M
NBGFX_CLK
NBGFX_CLK#
<16> NBGFX_CLK
<16> NBGFX_CLK#
<18> UMA_LCD_DDC_CLK
<18> UMA_LCD_DDC_DAT
<19> HDMIDAT_UMA
<19> HDMICLK_UMA
T2
T1
GFX_REFCLKP
GFX_REFCLKN
GPP_REFCLKP
GPP_REFCLKN
CLK_SBLINK_BCLK
CLK_SBLINK_BCLK#
V4
V3
GPPSB_REFCLKP(SB_REFCLKP)
GPPSB_REFCLKN(SB_REFCLKN)
UMA_LCD_DDC_CLK
UMA_LCD_DDC_DAT
HDMIDAT_UMA
HDMICLK_UMA
B9
A9
B8
A8
B7
A7
I2C_CLK
I2C_DATA
DDC_DATA0/AUX0N(NC)
DDC_CLK0/AUX0P(NC)
DDC_CLK1/AUX1P(NC)
DDC_DATA1/AUX1N(NC)
@
+3VS
R88 2
1 10K_0402_5%
B10
<15>
AUX_CAL
AUX_CAL
B18
A18
A17
B17
D20
D21
D18
D19
UMA_LCD_TXOUT0_A0+ <18>
UMA_LCD_TXOUT0_A0- <18>
UMA_LCD_TXCLK_ACLK+
UMA_LCD_TXCLK_ACLK-
B16
A16
D16
D17
A13
B13
+VDDLTP18
VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)
A15
B15
A14
B14
+VDDLT18
VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)
C14
D15
C16
C18
C20
E20
C22
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
E9
F7
G12
UMA_LCD_TXCLK_ACLK+ <18>
UMA_LCD_TXCLK_ACLK- <18>
UMA_ENVDD
UMA_ENBKL
UMA_ENVDD <18>
UMA_ENBKL <32>
2
< LVDS backlight enable >

2
1 100K_0402_5%
Reserve for INVT_PWM
MIS.
TMDS_HPD(NC)
HPD(NC)
SUS_STAT#(PWM_GPIO5)
THERMALDIODE_P
THERMALDIODE_N
TESTMODE
D9
D10
HPD
D12
SUS_STAT#
HPD
< HDMI hot-plug detection >
<19,21>
< Strap option pin or gate side-port memory IO >
SUS_STAT# <15,21>
AE8
AD8
D13
R80
2 1.8K_0402_5%
AUX_CAL(NC)
RS780MCR3@
RS780M_FCBGA528
< Dedicated power for the DAC which can affect display quality >
< Dedicated power for the DAC which can affect display quality >
+1.8VS
+3VS
2 300_0402_5% NB_PWRGD
R371 1
+1.8VS
1
< LVDS digital power enable >
R73
PAD T17
RSVD
C8
UMA_LCD_TXOUT0_A0+
UMA_LCD_TXOUT0_A0UMA_LCD_TXOUT0_A1+
UMA_LCD_TXOUT0_A1UMA_LCD_TXOUT0_A2+
UMA_LCD_TXOUT0_A2-
VDDLTP18(NC)
VSSLTP18(NC)
STRP_DATA
G11
Strap pin
TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5)
TXOUT_U3N(NC)
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)
U1
U2
<16> CLK_SBLINK_BCLK
<16> CLK_SBLINK_BCLK#
A22
B22
A21
B21
B20
A20
A19
B19
DAC_RSET(PWM_GPIO1)
PLLVDD(NC)
PLLVDD18(NC)
PLLVSS(NC)
<16> CLK_NBHT
<16> CLK_NBHT#
R72
4.7K_0402_5%
G18
G17
E18
F18
E19
F19
A12
D14
B12
1
2
C_Pr(DFT_GPIO5)
Y(DFT_GPIO2)
COMP_Pb(DFT_GPIO4)
+NB_PLLVDD
+NB_HTPVDD
R67 1
<15,20,26,27,31,32> PLT_RST#
<21> NB_PWRGD
<7,20> LDT_STOP#
<7,20> CPU_LDT_REQ#
+1.1VS
2 715_0402_1%
E17
F17
F15
TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
PART 3 OF 6
PM
<15,17>
<15,17>
<17>
<17>
AVDD1(NC)
AVDD2(NC)
AVDDDI(NC)
AVSSDI(NC)
AVDDQ(NC)
AVSSQ(NC)
CRT/TVOUT
+AVDDQ
F12
E12
F14
G15
H15
H14
PLL PWR
LVTM
+AVDD1
+AVDD2
U3C
AVDD=100mA
CLOCKs
L2
2 BLM18PG121SN1D_0603
L4
0_0603_5%
+AVDD1
1
+AVDD2
1
C170
2.2U_0603_6.3V4Z
C172
2.2U_0603_6.3V4Z
R62 1
2 140_0402_1% UMA_CRT_R
R63 1
2 150_0402_1% UMA_CRT_G
R64 1
2 150_0402_1% UMA_CRT_B
C198
0.1U_0402_16V7K
< DAC Bandgap Reference Voltage >

< 1.8V power for system PLLs >
< Power for integrated DVI/HDMI PLL macro >
+1.8VS
1
+1.8VS
L6
2 BLM18PG121SN1D_0603
+1.8VS
+AVDDQ
1
+NB_HTPVDD
L7
2 BLM18PG121SN1D_0603
1
C175
2
1
L3
1 BLM18PG121SN1D_0603
+VDDLTP18
1
C176
C171
2.2U_0603_6.3V4Z
2
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
< IO power for HyperTransport PLL >

< 1.1V Power for system PLLs >
+1.8VS
< 1.8V IO power for the integrated DVI/HDMI interface >
+VDDA18HTPLL
1
L10
2 BLM18PG121SN1D_0603
1
+1.1VS
+1.8VS
C179
+NB_PLLVDD
L9
2 BLM18PG121SN1D_0603
1
2.2U_0603_6.3V4Z
2
1
L5
1 BLM18PG121SN1D_0603
+VDDLT18
1
C178
C174
C173
< 1.8V IO power for PCI-E PLLs >
+1.8VS
1
C180
2.2U_0603_6.3V4Z
Compal Secret Data
2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
RS780M VEDIO/CLK GEN
Date:
0.1U_0402_16V7K
Custom
4.7U_0805_10V4Z
+VDDA18PCIEPLL
L11
2 BLM18PG121SN1D_0603
1
2.2U_0603_6.3V4Z
Rev
1.0
LA-5831P
Sheet
E
12
of
44
U3D
PAR 4 OF 6
MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)
AD16
AE17
AD17
MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)
W12
Y12
AD18
AB13
AB18
V14
MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)
V15
W14
MEM_CKP(NC)
MEM_CKN(NC)
AE12
AD12
SBD_MEM/DVO_I/F
AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14
MEM_COMPP(NC)
MEM_COMPN(NC)
RS780M_FCBGA528
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)
AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)
Y17
W18
AD20
AE21
MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)
W17
AE19
IOPLLVDD18(NC)
IOPLLVDD(NC)
AE23
AE24
IOPLLVSS(NC)
AD23
MEM_VREF(NC)
AE18
+1.8VS
+1.1VS
RS780MCR3@
Compal Secret Data
Issued Date
2008/04/14
Deciphered Date
2009/04/14
Title

RS780M SIDE PORT
Custom
Date:
Rev
1.0
LA-5831P
Sheet
13
of
44
0.1U_0402_16V7K
0.1U_0402_16V7K
Change L16, L18, L19 and L22

to bead for EMI
2A
2
+1.8VS
L22
FBMA-L11-201209-221LMA30T_0805
1
1
1
C235
C246
C236
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
< 1.8V IO power for PCI-E graphics, SB, and GPP interfaces >
1
0.1U_0402_16V7K
C237
0.1U_0402_16V7K
C238
0.1U_0402_16V7K
+VDDA18PCIE
C239
0.1U_0402_16V7K
VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13
J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10
VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15
< 1.8V IO transform power >

+1.8VS
1
C251
+1.8VS
L89
0_0603_5%
1U_0402_6.3V4Z
F9
G9
AE11
AD11
< 1.8V power for side-port memory interface >
C252
@
1U_0402_6.3V4Z
K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
C211
C212
10U_0805_10V4Z
10U_0805_10V4Z
C221
C222
C219
C220
VDD_CORE:GM=5A/PM=10A
1
+1.1VS
FBMA-L11-201209-121LMA40T_0805
PJP3
2
PAD-OPEN 4x4m
< Isolated power for side-port memory interface >
H11
H12
VDD33_1(NC)
VDD33_2(NC)
RS780M_FCBGA528
L90
< Core power >
AE10
AA11
Y11
AD10
AB10
AC10
VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)
VDD18_1
VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)
Change L90 to bead for EMI

+NB_CORE
C234
AE25
AD24
AC23
AB22
AA21
Y20
W19
V18
U17
T17
R17
P17
M17
330U_D2E_2.5VM
0.1U_0402_16V7K
+VDDHTTX
C229
C245
C228
10U_0805_10V4Z
0.1U_0402_16V7K
C233
< IO power for HyperTransport transmit interface >
+1.1VS
10U_0805_10V4Z
4.7U_0805_10V4Z
0.1U_0402_16V7K
C232
FBMA-L11-201209-221LMA30T_0805
1
1
C225
C226
C227
0.1U_0402_16V7K
0.1U_0402_16V7K
C244
L19
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_6.3V4Z
C231
0.1U_0402_16V7K
0.1U_0402_16V7K
2A
2
+1.2V_HT
1U_0402_6.3V4Z
10U_0805_10V4Z
VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7
C230
H18
G19
F20
E21
D22
B23
A23
0.1U_0402_16V7K
+VDDHTRX
C218
1U_0402_6.3V4Z
C217
1U_0402_6.3V4Z
C243
0.1U_0402_16V7K
C242
C223
0.1U_0402_16V7K
VDDA_12=2.5A
0.1U_0402_16V7K
FBMA-L11-201209-221LMA30T_0805
1
1
C214
C216
< IO power for HyperTransport receive interface >
C224
0.1U_0402_16V7K
L17
1
2
FBMA-L11-201209-221LMA30T_0805
+VDDA11PCIE
0.1U_0402_16V7K
C210
PART 5/6
A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9
VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17
C241
C215
0.1U_0402_16V7K
C208
VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7
0.1U_0402_16V7K
L18
J17
K16
L16
M16
P16
R16
T16
0.1U_0402_16V7K
4.7U_0805_10V4Z
< Main IO power for PCI-E graphics, SB, and GPP interfaces >
U3E
+VDDHT
0.1U_0402_16V7K
2A
< Digital IO power for HyperTransport interface >
C240
FBMA-L11-201209-221LMA30T_0805
1
1
1
C209
C206
C207
C247
L16
0.1U_0402_16V7K
0.1U_0402_16V7K
2A
2
+1.1VS
POWER
< 3.3V IO power >

+3VS
1
RS780MCR3@
C250
0.1U_0402_16V4Z
C253
0.1U_0402_16V4Z
U3F
VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27
L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
PART 6/6
GROUND
A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25
RS780M_FCBGA528
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2
AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15
RS780MCR3@
Compal Secret Data
2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title

RS780M PWR / GND
Custom
A
VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
Date:
Rev
1.0
LA-5831P
Sheet
E
14
of
44
< RS780 DFT_GPIO5 mux at CRT_VSYNC pull High to 3K >
< DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb >

Enables the Test Debug Bus using GPIO.
SI2: Change to 3K pull high

2
R101
3K_0402_5%
@ 2
R102
3K_0402_5%
<12,17> UMA_CRT_VSYNC
+3VS
1 : Enable (RX780, RS780)

0 : Disable (RX780, RS780)
PIN: RS740-->RS780_AUX_CAL; RX780-->NB_TV_C; RS780--> VSYNC#
< DFT_GPIO[4:2] : STRAP_PCIE_GPP_CFG[2:0] >
< RS780 use register to control PCI-E configure >
These pin straps are used to configure PCI-E GPP mode.

000 : 00001
001 : 00010
010 : 01011
011 : 00100
100 : 01010
101 : 01100
111 : 01011
< DFT_GPIO1 : LOAD_EEPROM_STRAPS >
< RS780 DFT_GPIO1 >
Selects Loading of STRAPS from EPROM

@ 1
<12> AUX_CAL
R104
150_0402_1%
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected
<12,21> SUS_STAT#
@ 2
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT
D4
1 CH751H-40PT_SOD323-2
PLT_RST# <12,20,26,27,31,32>
< DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb >
< RS780 use HSYNC to enable SIDE PORT (internal pull high) >
RX780: Enables the Test Debug Bus using PCIE bus

<12,17> UMA_CRT_HSYNC
R125
3K_0402_5%
+3VS
1 : Disable ( Can still be enabled using nbcfg register access )

0 : Enable
RS780: Enables Side port memory ( RS780 use HSYNC#)
1. Disable (RS780)
0 : Enable (RS780)
2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title

RS780M STRAPS
Custom
A
Compal Secret Data
Date:
Rev
1.0
LA-5831P
Sheet
E
15
of
44
+1.2V_HT
R167 1
R168 1
2 0_0805_5%
1
2 0_0805_5%
1
1
C452
22U_0805_6.3V6M
1
C453
0.1U_0402_16V4Z
1
C454
0.1U_0402_16V4Z
1
C455
0.1U_0402_16V4Z
1
C444
22U_0805_6.3V6M
1
C456
0.1U_0402_16V4Z
+3VS_CLK
+3VS
+VDDCLK_IO
C457
0.1U_0402_16V4Z
C445
0.1U_0402_16V7K
C446
0.1U_0402_16V7K
CLK_48M_CR_R
R970
33_0402_5%
CLK_48M_USB_R
R170
33_0402_5%
NB_OSC_14.318M_R
R379
158_0402_1%
R971
TIGRIS@
1
2
C447
0.1U_0402_16V7K
C448
0.1U_0402_16V7K
+3VS_CLK
1
C458
C459
C460
C461
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C449
0.1U_0402_16V7K
C450
0.1U_0402_16V7K
C451
1U_0402_6.3V4Z
CLK_48M_CR <28>
< To Card Reader >
CLK_48M_USB <21>
< To SB700 USB host >
0.1U_0402_16V4Z
NB_OSC_14.318M
R380 1
CLK_XTAL_OUT
CLK_XTAL_IN
2 90.9_0402_1%
33_0402_5%
SB_14.318M <20>
CLK_NBHT
CLK_NBHT <12>
< To RS780 Clock block >
CLK_NBHT#
1
14.31818MHZ_20P_6X1430004201
1
C465
CLK_NBHT# <12>
R174
+3VS_CLK
+3VS_CLK
C464
+3VS_CLK
Y2
2
C629
2
1
CLK_CPU_BCLK_R
2
8.2K_0402_5%
+3VS_CLK
1U_0402_6.3V4Z
R946
0_0402_5%
CLK_CPU_BCLK <7>
22P_0402_50V8J
22P_0402_50V8J
2
<12> < To RS780 Clock block >
73
GND
SMB_CK_CLK0
SMB_CK_DAT0
<9,10,21> SMB_CK_CLK0
<9,10,21> SMB_CK_DAT0
+3VS_CLK
CLK_SBLINK_BCLK#
CLK_SBLINK_BCLK
<12> CLK_SBLINK_BCLK#
<12> CLK_SBLINK_BCLK
SB LINK
+VDDCLK_IO
CLK_PCIE_MCARD2#
CLK_PCIE_MCARD2
<27> CLK_PCIE_MCARD2#
<27> CLK_PCIE_MCARD2
WLAN
SCL
SDA
VDD_DOT
SRC_7#/27M
SRC_7/27M_SS
VSS_DOT
SRC_5#
SRC_5
SRC_4#
SRC_4
VSS_SRC
VDD_SRC_IO
SRC_3#
SRC_3
SRC_2#
SRC_2
VDD_SRC
VDD_SRC_IO
VSS_SRC
SRC_1#
SRC_1
SRC_0#
SRC_0
CLKREQ_0#
ATIGCLK_2#
ATIGCLK_2
VSS_ATIG
VDD_ATIG_IO
VDD_ATIG
ATIGCLK_1#
ATIGCLK_1
ATIGCLK_0#
ATIGCLK_0
SB_SRC_1#
SB_SRC_1
VSS_SB_SRC
+3VS_CLK
+VDDCLK_IO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
+3VS_CLK
< To CPU >
R945
0_0402_5%
261_0402_1%
VSS_48
48MHz_0
48MHz_1
VDD_48
XTAL_OUT
XTAL_IN
VSS_REF
REF_0/SEL_HTT66
REF_1/SEL_SATA
REF_2/SEL_27
VDD_REF
VDD_HTT
HTT_0/66M_0
HTT_0#/66M_1
VSS_HTT
PD#
CPU_K8_0
CPU_K8_0#
U10
@
CLK_CPU_BCLK_R#
CLK_CPU_BCLK# <7>
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
SEL_SATA
27M_SEL
CLK_XTAL_OUT
CLK_XTAL_IN
R186
VDD_CPU
VDD_CPU_I/O
VSS_CPU
CLKREQ_1#
CLKREQ_2#
VDD_A
VSS_A
VSS_SATA
SRC_6/SATA
SRC_6#/SATA#
VDD_SATA
CLKREQ_3#
CLKREQ_4#
SB_SRC_SLOW#
SB_SRC_0
SB_SRC_0#
VDD_SB_SRC
VDD_SB_SRC_IO
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
+3VS_CLK
Reserve Clock Request

for NewCard
+3VS_CLK
+VDDCLK_IO
CLKREQ_NCARD#
CLKREQ_MCARD2#
CLKREQ_NCARD#
CLKREQ_MCARD2# <27>
+3VS_CLK
CLKREQ_MCARD2#
CLKREQ_LAN#
CLK_SBSRC_BCLK
CLK_SBSRC_BCLK#
CLK_SBSRC_BCLK <20>
CLK_SBSRC_BCLK# <20> SB
1
R324
1
R325
1
R390
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
SRC
+3VS_CLK
R372 1
2 10K_0402_5%
+3VS_CLK
+3VS_CLK
+VDDCLK_IO
3
SLG8SP626VTR_QFN72_10x10
R179
8.2K_0402_5%
@
OSC_14M_NB
RS780
R181
8.2K_0402_5%
NBGFX_CLK <12>
NBGFX_CLK# <12>
NB CLOCK INPUT TABLE
NB GFX
NB CLOCKS
RX780
RS780
R180
8.2K_0402_5%
+3VS_CLK
+VDDCLK_IO
+3VS_CLK
SEL_SATA
1.1V 158R/90.9R
HT_REFCLKP
27M_SEL
100M DIFF
100M DIFF
100M DIFF
100M DIFF
REFCLK_N
14M SE (1.8V)
NC
14M SE (1.1V)
vref
GFX_REFCLK
100M DIFF
100M DIFF(IN/OUT)*
GPP_REFCLK
100M DIFF
NC or 100M DIFF OUTPUT
GPPSB_REFCLK
100M DIFF
100M DIFF
HT_REFCLKN
REFCLK_P
1
CLKREQ_LAN#
CLK_PCIE_LAN
CLK_PCIE_LAN#
configure as SATA output
SEL_SATA
1 *
configure as normal SRC(SRC_6) output
0 *
* default
configure as 27M and 27M_SS output
27M_SEL
configure as SRC_7 output
0
* default
CLKREQ_LAN# <26>
CLK_PCIE_LAN <26>
CLK_PCIE_LAN# <26>
LAN
Use voltage divider resistor R379 & R380 to pull low

1
configure as single-ended 66MHz output
0*
configure as differential 100MHz output
* default
2009-02-12
2009-02-12
Deciphered Date
Title
Custom
A
Compal Secret Data
Issued Date
NB_OSC_14.318M
Date:
Clock Generator
Rev
1.0
LA-5831P
Sheet
E
16
of
44
+5VS
< CRT CONNECTOR >
+R_CRT_VCC
D36
+CRT_VCC
F2
2 1.1A_6V_MINISMDC110F-2
2
1
1
RB491D_SOT23-3
C475
0.1U_0402_16V4Z
D35
DAN217_SC59 @
D37
DAN217_SC59 @
D34
DAN217_SC59
JCRT
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
+3VS
RED_L
D_DDCDATA
GREEN_L
L47
<12> UMA_CRT_R
<12> UMA_CRT_G
<12> UMA_CRT_B
2 NBQ100505T-800Y_0402
RED_L
2 NBQ100505T-800Y_0402
GREEN_L
2 NBQ100505T-800Y_0402
BLUE_L
HSYNC
BLUE_L
L48
+CRT_VCC
VSYNC
L49
R217
150_0402_1%
C471
6P_0402_50V8D
C859
6P_0402_50V8D
C469
6P_0402_50V8D
C858
6P_0402_50V8D
C476
6P_0402_50V8D
C472
6P_0402_50V8D
220P_0402_50V7K
D_DDCCLK
G
G
16
17
ALLTO_C10532-11505-L_15P-T
R211
150_0402_1%
C706
R214
140_0402_1%
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
+CRT_VCC
2
2 0.1U_0402_16V4Z
R972
2 10K_0402_5%
<12,15> UMA_CRT_HSYNC
P
OE#
5
1
C473 1
D_HSYNC
L84 1
2 10_0402_5%
HSYNC
L83 1
2 10_0402_5%
VSYNC
U14
SN74AHCT1G125GW_SOT353-5
< SYNC SIGNAL >
+CRT_VCC
2 0.1U_0402_16V4Z
R973
2 10K_0402_5%
<12,15> UMA_CRT_VSYNC
P
OE#
5
1
C477 1
C474
10P_0402_50V8J @
2
Y
C470
10P_0402_50V8J
D_VSYNC
4
U13
+CRT_VCC
+3VS
+3VS
R238
4.7K_0402_5%
R100
6.8K_0402_5%
Q10B
3 2N7002DW-7-F_SOT363-6
4
1
<12> UMA_CRT_DATA
D_DDCDATA
C177
33P_0402_50V8K
R218
6.8K_0402_5%
R237
4.7K_0402_5%
< Display Data Channel >
+3VS
Q10A
6 2N7002DW-7-F_SOT363-6
1
1
<12> UMA_CRT_CLK
C181
33P_0402_50V8K
D_DDCCLK
1
C857
470P_0402_50V8J
1
@
C856
470P_0402_50V8J
RS780 DAC_SCL & SDA is 5V tolerance

FOR EMI
2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title

CRT Connector
Custom
A
Compal Secret Data
Date:
Rev
1.0
LA-5831P
Sheet
E
17
of
44
< Int. Camera, USB port 9 >
Int. Camera
< EMI require >
+5V_CAM
CAM@
0_0402_5%
1 R103
R1009
2
1
0_0603_5% @
+5VS
L60
2
<21>
<21>
USB20_N9
USB20_P9
USB20_N9_R
USB20_P9_R
0_0402_5%
2
2
0_0402_5%
@
@
R1004
1
1
R1005
USB20_N9_R_R
USB20_P9_R_R
reserve for test, close to JLVDS
1
2
3
4
5
GND1
GND2
CAM@
2
C888 @
1
2
0.1U_0402_16V4Z
JCAM
WCM-2012-900T_0805
0_0402_5%
W=20mils
R99
1
2
3
4
5
6
7
USB20_N9_R_R
USB20_P9_R_R
ACES_88266-05001
@
+5V_LVDS_CAM
LVDS & CAMERA
R146
10K_0402_5%
C265
0.1U_0402_16V4Z
C266
4.7U_0805_10V4Z
+LCD_VDD
+LCDVDD_R
ACES_88242-4001
+3VS
+LCD_INV
Rated Current MAX:3000mA

1
C268
68P_0402_50V8J
+3VS
L12 2
1
B+
FBMA-L11-201209-221LMA30T_0805
C269
0.1U_0402_25V4Z
+3VS
R142
R143
150_0603_5%
100K_0402_5%
2N7002DW-T/R7_SOT363-6
2 4.7K_0402_5%
UMA_LCD_DDC_CLK
2 4.7K_0402_5%
UMA_LCD_DDC_DAT
INVT_PWM
AO3413_SOT23
W=60mils
Inrush current = 0A
R668
2 0_0402_5%
5
2N7002DW-T/R7_SOT363-6
C708
1
2
C263
C264
Q1B
ENVDD
1
4.7U_0805_10V4Z
0.1U_0402_16V7K
<12> UMA_ENVDD
R144
100K_0402_5%
220P_0402_50V7K
BKOFF#
0.01U_0402_25V7K
R69
+LCD_VDD
C875
C707
1
2
220P_0402_50V7K
R68
Q2
2
1
47K_0402_5%
+3VS
0.1U_0402_16V7K
R140
C267
0.1U_0402_16V4Z
W=60mils
3
Q1A
For EMI
DAC_BRIG
C874
UMA_LCD_DDC_CLK <12>
UMA_LCD_DDC_DAT <12>
+LCD_VDD
1
BKOFF#
<32>
BKOFF#
2 L8
1
0_0805_5%
1
LCD/PANEL BD. Conn.
1.5A
DAC_BRIG <32>
INVT_PWM <32>
USB20_P9_R
USB20_N9_R
+5V_LVDS_CAM
UMA_LCD_TXCLK_ACLK+ <12>
UMA_LCD_TXCLK_ACLK- <12>
6 2
+5V_LVDS_CAM
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
<12> UMA_LCD_TXOUT0_A2+
<12> UMA_LCD_TXOUT0_A2-
W=20mils0.1U_0402_16V4Z
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GND
C882 CAM@
1
2
+5VS
JLVDS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
R1006
2
1
0_0603_5%
CAM@
C709
1
2
220P_0402_50V7K
Compal Secret Data
2009-02-12
Issued Date
Title

LCD CONN. / Camera
Custom
A
2009-02-12
Deciphered Date
Date:
Rev
1.0
LA-5831P
Sheet
E
18
of
44
+HDMI_5V_OUT_M
+HDMI_5V_OUT
HDMI@
1
<11>
<11>
<11>
<11>
<11>
<11>
HDMI_TXD0+
HDMI_TXD0HDMI_TXD1+
HDMI_TXD1HDMI_TXD2+
HDMI_TXD2-
<11> HDMI_CLK0+
<11> HDMI_CLK0-
HDMI@
HDMI@
HDMI@
HDMI@
HDMI@
HDMI@
C189
C188
C190
C184
C187
C191
HDMI@
HDMI@
C185 1
C186 1
1
1
1
1
1
1
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
HDMI_TX0+
HDMI_TX0HDMI_TX1+
HDMI_TX1HDMI_TX2+
HDMI_TX2-
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
HDMI_CLK+
HDMI_CLK-
2
2
2
2
2
2
D53
1 PMEG2010AEH_SOD123
+5VS
HDMI@ F3
1 1.1A_6V_MINISMDC110F-2
Vf=0.25V when If=55mA

2
C258
HDMI@
0.1U_0402_16V7K
< Place MOSFET close to HDMI connector >

< HDMI DDC channel to device >
+3VS
+3VS
+HDMI_5V_OUT
< HDMI Connector >
R616
0_0402_5%
HDMI_R_CK-
HDMI_R_D2+
2
1
<12> HDMICLK_UMA
HDMI_SCLK
@
HDMI_CLK-
3
S
HDMI_R_D1+
HDMI_R_D2-
HDMI_SDATA
HDMI@
Q140
BSH111_SOT23-3
1
< EMI solution >
HDMI@
R236
2.2K_0402_5%
HDMI_R_D0+
HDMI_R_D1-
HDMI@
R210
2.2K_0402_5%
HDMI@
Q139
BSH111_SOT23-3
1
<12> HDMIDAT_UMA
20
21
22
23
HDMI_R_CK+
HDMI_R_D0-
HDMI@
R209
4.7K_0402_5%
HDMI_R_CK-
HDMI@
R176
4.7K_0402_5%
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
HDMI_SDATA
HDMI_SCLK
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
JHDMI
HDMI_HPD
+HDMI_5V_OUT
TYCO_1939864-1_19P
R618
0_0402_5%
HDMI@
HDMI@
@
1
HDMI_R_CK-
HDMI_R_D0-
R307
2 715_0402_1%
2
715_0402_1%
R315
HDMI@
L86
2
+5VS
WCM-2012-900T_0805
@
HDMI_TX0+
R619
0_0402_5%
HDMI_R_D0+
R620
0_0402_5%
HDMI_R_D1-
@
HDMI_TX1-
L87
1
4
HDMI@
HDMI_R_D0-
HDMI_R_D0+
R304
2 715_0402_1%
HDMI@
3
HDMI_R_D1-
HDMI_R_D1+
R297
2 715_0402_1%
R621
0_0402_5%
HDMI_R_D1+
R623
0_0402_5%
HDMI_R_D2-
715_0402_1%
R173
HPD
+5VS
HDMI_R_D2+
R141
2 715_0402_1%
HDMI_R_D2-
2
HDMI@
R588
2.2K_0402_5%
HDMI@
+5VS
Q137B
3
HPD
<12,21>
715_0402_1%
R139
R977
100K_0402_5%
4
2N7002DW-7-F_SOT363-6
HDMI@
+3VS
Q137A
1
2N7002DW-7-F_SOT363-6
HDMI@
L88
C850
HDMI@
0.1U_0402_16V4Z
2
@
U39
HDMI@
HDMI@
R628
HDMI@
100K_0402_5%
HPD
HDMI@
4
2N7002DW-7-F_SOT363-6
HDMI@
715_0402_1%
R172
HDMI@
HDMI_TX2-
2
HDMI@
WCM-2012-900T_0805
HDMI_TX1+
C851
HDMI@
0.1U_0402_16V4Z
Q136B
3
HDMI_HPD
+HDMI_5V_OUT
+5VS
HDMI@
< Hot-plug detection & level shift >
Q136A
1
2N7002DW-7-F_SOT363-6
HDMI@
HDMI_TX0-
HDMI_R_CK+
< Termination resistor >

HDMI_R_CK+
R617
0_0402_5%
5
1
@
HDMI_CLK+
P
OE#
WCM-2012-900T_0805
HDMI@
L85
1
WCM-2012-900T_0805
@
HDMI_TX2+
R624
0_0402_5%
2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Custom
A
Compal Secret Data
HDMI_R_D2+
Date:
HDMI
Rev
1.0
LA-5831P
Sheet
E
19
of
44
+3VALW
C506
1 0.1U_0402_16V4Z
U16
NC7SZ08P5X_NL_SC70-5
R303
2 100_0402_5%
@ 1
C501
2 100P_0402_50V8J
PLT_RST#
PLT_RST# <12,15,26,27,31,32>
CLK_PCI_SIO2 @ 1
R369
2 100_0402_5%
@ 1
C503
2 100P_0402_50V8J
Y
3
NB_RST#_R
@ 1
CLK_PCI_EC
1 33_0402_5%
U15A
N2
< x4 PCIE A-link To NB >
< x4 PCIE A-link from NB >
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
C492
C493
C494
C495
C496
C497
C498
C499
R305
R306
+PCIE_VDDR
+1.2V_HT
1
1
1
1
1
1
1
1
L53 1
2
2
2
2
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
V23
V22
V24
V25
U25
U24
T23
T22
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
U22
U21
U19
V19
R20
R21
R18
R17
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
T25
T24
PCIE_CALRP
PCIE_CALRN
1 562_0402_1%
1 2.05K_0402_1%
2
2
2 BLM18PG121SN1D_0603
1
C504
2.2U_0603_6.3V4Z
SB700
A_RST#
SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C
Part 1 of 5
PCI CLKS
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
+SB_PCIEVDD P24
PCIE_PVDD
P25
PCIE_PVSS
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5/GPIO41
PCIRST#
PCI EXPRESS INTERFACE
R312 2
1
Close to SB
K23
K22
M24
M25
P17
M18
M23
M22
J19
J18
L20
L19
M19
M20
N22
P22
SB_14.318M
<16> SB_14.318M
L18
J21
C643
2 18P_0402_50V8J
Close to SB
GPP_CLK0P
GPP_CLK0N
GPP_CLK1P
GPP_CLK1N
GPP_CLK2P
GPP_CLK2N
GPP_CLK3P
GPP_CLK3N
25M_48M_66M_OSC
25M_X1
25M_X2
IN
NC
NC
SB_32KHI
A3
32.768KHZ_12.5P_1TJS125BJ4A421P
SB_32KHO
CPU_LDT_REQ#
H_PROCHOT#
H_PWRGD
LDT_STOP#
LDT_RST#
B3
F23
F24
F22
G25
G24
X1
X2
ALLOW_LDTSTP
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#
LPC
OUT
<7,12> CPU_LDT_REQ#
<7> H_PROCHOT#
<7,42> H_PWRGD
<7,12> LDT_STOP#
<7> LDT_RST#
H_PROCHOT#
SLT_GFX_CLKP
SLT_GFX_CLKN
U2
P7
V4
T1
V3
U1
V1
V2
T2
W1
T9
R6
R7
R5
U8
U5
Y7
W8
V9
Y8
AA8
Y4
Y3
Y2
AA2
AB4
AA1
AB3
AB2
AC1
AC2
AD1
W2
U7
AA7
Y1
AA6
W5
AA5
Y5
U6
W6
W4
V7
AC3
AD4
AB7
AE6
AB6
AD2
AE4
AD5
AC6
AE5
AD6
V5
INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36
AD3
AC4
AE2
AE3
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/GNT5#/GPIO68
BMREQ#/REQ5#/GPIO65
SERIRQ
RTCCLK
INTRUDER_ALERT#
VBAT
+SB_VBAT
+RTCVCC
R316
2 120_0402_5%
0.1U_0402_16V7K
W=20mils
R317
2 120_0402_5%
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PAD T18
PAD T26
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PAD T15
PAD T16
R308
G22 CLK_PCI_EC1
1
2
E22 CLK_PCI_SIOC R310
1
2
LPC_AD0
H24
LPC_AD0
LPC_AD1
H23
LPC_AD1
LPC_AD2
J25
LPC_AD2
LPC_AD3
J24
LPC_AD3
H25
LPC_FRAME#_SB PUMA@ 1
H22
AB8
R979 1
AD7
TIGRIS@
V15
SERIRQ
SERIRQ
C3
C2
B2
<24>
<24>
<24>
<24>
<24>
<24>
RTC_CLK
22_0402_5%
CLK_PCI_EC <24,32>
22_0402_5%
CLK_PCI_SIO2 <24,31>
<31,32>
<31,32>
<31,32>
<31,32>
D84
PUMA@
R978
2 CH751H-40PT_SOD323-2 2
1 300_0402_5%
EC & TPM &Debug
2 0_0402_5%
+3VS
LPC_FRAME# <31,32>
<31,32>
RTC_CLK <24>
STRAP PIN
+SB_VBAT
SB700R3@
4
218S7EALA11FG_BGA528_SB700
+RTCBATT
D10
R184
1 1K_0402_5%
<24>
<24>
<24>
<24>
C510
1U_0402_6.3V4Z
1
2
J1
JUMP_43X39
C297
0.1U_0402_16V7K
C509
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLK5
1
1
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLK5
N1
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
REQ3#/GPIO70
REQ4#/GPIO71
GNT0#
GNT1#
GNT2#
GNT3#/GPIO72
GNT4#/GPIO73
CLKRUN#
LOCK#
RTC
1 10K_0402_5%
CPU_HT_CLKP
CPU_HT_CLKN
CPU
R319 2
+3VS
C652
2 18P_0402_50V8J
NB_HT_CLKP
NB_HT_CLKN
RTC XTAL
4
R389
20M_0603_5%
J20
NB_DISP_CLKP
NB_DISP_CLKN
Y3
PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN
PCI INTERFACE
N25
N24
CLOCK GENERATOR
CLK_SBSRC_BCLK
CLK_SBSRC_BCLK#
<16> CLK_SBSRC_BCLK
<16> CLK_SBSRC_BCLK#
P4
P3
P1
P2
T4
T3
A
2009-02-12
Issued Date
Compal Secret Data
2009-02-12
Deciphered Date
Title
SB700 - PCIE / PCI / ACPI / LPC / RTC

+CHGRTC
Custom
Size
Date:
BAS40-04_SOT23-3
Document Number
Rev
1.0
LA-5831P
Sheet
E
20
of
44
+3VALW
R320
2.2K_0402_5%
SB_TEST2
R321
2.2K_0402_5%
SB_TEST1
Reserve for EMI request

U15D
R322
2.2K_0402_5%
E1
E2
H7
PM_SLP_S3#
F5
PM_SLP_S5#
G1
PBTN_OUT#
H2
SB_PWRGD
H1
SUS_STAT#
K3
SB_TEST2
H5
SB_TEST1
H4
SB_TEST0
H3
GATEA20
Y15
KB_RST#
W15
EC_SCI#
K4
EC_SMI#
K24
F1
J2
LAN_WAKE#
H6
F2
H_THERMTRIP# J6
NB_PWRGD
W14
SB_TEST0
R561
1K_0402_5%
LAN_WAKE#
R330
100K_0402_5%
EXP_CPPE#
<32>
<32>
<32>
<32,42>
<12,15>
PM_SLP_S3#
PM_SLP_S5#
PBTN_OUT#
SB_PWRGD
SUS_STAT#
Reserve pull-high for EXP_CPPE#

<32>
<32>
<32>
<32>
+3VS
1
1
R328
1.2K_0402_5%
SMB_CK_CLK0
R329
1.2K_0402_5%
SMB_CK_DAT0
GATEA20
KB_RST#
EC_SCI#
EC_SMI#
<26> LAN_WAKE#
<S0>
<7> H_THERMTRIP#
<12> NB_PWRGD
EC_RSMRST#
<32> EC_RSMRST#
D3
PCI_PME#/GEVENT4#
RI#/EXTEVNT0#
SLP_S2/GPM9#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
TEST2
TEST1
TEST0
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/EXTEVNT1#
S3_STATE/GEVENT5#
SYS_RESET#/GPM7#
WAKE#/GEVENT8#
BLINK/GPM6#
SMBALERT#/THRMTRIP#/GEVENT2#
NB_PWRGD
USBCLK/14M_25M_48M_OSC
USB_RCOMP
USB_FSD13P
USB_FSD13N
SMB_CK_CLK1
R332
2.2K_0402_5%
SMB_CK_DAT1
R327
100K_0402_5%
< S0~ S5 ASF only >
<29> SB_SPKR
<9,10,16> SMB_CK_CLK0
<9,10,16> SMB_CK_DAT0
<27> SMB_CK_CLK1
<27> SMB_CK_DAT1
EC_RSMRST#
@
1
+3VS
+3VS
HDMI@
R388
2 4.7K_0402_5%
AE18
AD18
AA19
W17
V17
W20
SB_SPKR
W21
SMB_CK_CLK0 AA18
SMB_CK_DAT0 W18
SMB_CK_CLK1
K1
SMB_CK_DAT1
K2
AA20
Y18
C1
Y19
G5
<12,19> HPD
R400
2 4.7K_0402_5%
R980
2 0_0402_5%
SATA_IS0#/GPIO10
CLK_REQ3#/SATA_IS1#/GPIO6
SMARTVOLT1/SATA_IS2#/GPIO4
CLK_REQ0#/SATA_IS3#/GPIO0
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39
CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
SPKR/GPIO2
SCL0/GPOC0#
SDA0/GPOC1#
SCL1/GPOC2#
SDA1/GPOC3#
DDC1_SCL/GPIO9
DDC1_SDA/GPIO8
LLB#/GPIO66
SMARTVOLT2/SHUTDOWN#/GPIO5
DDR3_RST#/GEVENT7#
USB 2.0
R331
2.2K_0402_5%
GPIO
SUS_STAT#
For BIOS utility support
<31> HDA_SYNC_MDC
<29> HDA_SYNC_CODEC
STRAP
<29> HDA_RST#_CODEC
<31> HDA_RST#_MDC
PIN<24> HDARST#
For EMI
Close to U15
R333
R334
R335
R336
1
2 33_0402_5%
1 MDC@ 2 33_0402_5%
1 MDC@ 2 33_0402_5%
1
2 33_0402_5%
HDA_BITCLK
HDA_SDOUT
HDA_SDIN0
HDA_SDIN1
R337
R338
1 MDC@ 2 33_0402_5%
1
2 33_0402_5%
HDA_SYNC
R339
R340
1
2 33_0402_5%
1 MDC@ 2 33_0402_5%
HDARST#
M1
M2
J7
J8
L8
M3
L6
M4
L5
AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO42
AZ_SDIN1/GPIO43
AZ_SDIN2/GPIO44
AZ_SDIN3/GPIO46
AZ_SYNC
AZ_RST#
AZ_DOCK_RST#/GPM8#
C619
100P_0402_50V8J
USB_HSD9P
USB_HSD9N
A11
B11
USB20_P9
USB20_N9
USB_HSD8P
USB_HSD8N
C10
D10
USB20_P8
USB20_N8
USB_HSD7P
USB_HSD7N
G11
H12
USB_HSD6P
USB_HSD6N
E12
E14
USB_HSD5P
USB_HSD5N
C12
D12
USB_HSD4P
USB_HSD4N
B12
A12
USB_HSD3P
USB_HSD3N
G12
G14
H19
H20
H21
F25
D22
E24
E25
D23
IMC_GPIO0
IMC_GPIO1
SPI_CS2#/IMC_GPIO2
IDE_RST#/F_RST#/IMC_GPO3
IMC_GPIO4
IMC_GPIO5
IMC_GPIO6
IMC_GPIO7
IMC_GPIO26
IMC_GPIO27
IMC_GPIO28
IMC_GPIO29
IMC_GPIO30
IMC_GPIO31
IMC_GPIO32
IMC_GPIO33
IMC_GPIO34
IMC_GPIO35
IMC_GPIO36
IMC_GPIO37
IMC_GPIO38
IMC_GPIO39
IMC_GPIO40
IMC_GPIO41
2 11.8K_0402_1%
E6
E7
E11
F11
IMC_GPIO18
IMC_GPIO19
IMC_GPIO20
IMC_GPIO21
IMC_GPIO22
IMC_GPIO23
IMC_GPIO24
IMC_GPIO25
INTEGRATED uC
USB_RCOMP
USB_HSD10P
USB_HSD10N
IMC_GPIO8
IMC_GPIO9
IMC_PWM0/IMC_GPIO10
SCL2/IMC_GPIO11
SDA2/IMC_GPIO12
SCL3_LV/IMC_GPIO13
SDA3_LV/IMC_GPIO14
IMC_PWM1/IMC_GPIO15
IMC_PWM2/IMC_GPO16
IMC_PWM3/IMC_GPO17
INTEGRATED uC
HDA_BITCLK_CODEC
HDA_BITCLK_MDC
HDA_SDOUT_MDC
HDA_SDOUT_CODEC
HDA_SDIN0
HDA_SDIN1
USB OC
<29>
<31>
<31>
<29>
<29>
<31>
USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GPM5#
USB_OC4#/IR_RX0/GPM4#
USB_OC3#/IR_RX1/GPM3#
USB_OC2#/GPM2#
USB_OC1#/GPM1#
USB_OC0#/GPM0#
HD AUDIO
<32> EC_LID_OUT#
<25,32> USB_OC#2
<25,32> USB_OC#0
G8
H11
J10
USB_HSD0P
USB_HSD0N
CLK_48M_USB <16>
R323
USB_HSD11P
USB_HSD11N
USB_HSD1P
USB_HSD1N
B9
B8
A8
A9
E5
F8
E4
C617
2 100P_0402_50V8J
CLK_48M_USB
F7
E8
USB_HSD2P
USB_HSD2N
HPD_R
EC_LID_OUT#
EXP_CPPE#
C8
USB_FSD12P
USB_FSD12N
RSMRST#
+3VALW
1
R311
2 100_0402_5%
Part 4 of 5
SB700
USB MISC
USB 1.1
ACPI / WAKE UP EVENTS
USB-9 Int Camera
USB20_P8 <27>
USB20_N8 <27>
USB-8 WLAN
USB20_P4
USB20_N4
H14
H15
USB20_P2
USB20_N2
A13
B13
USB20_P1
USB20_N1
B14
A14
USB20_P0
USB20_N0
A18
B18
F21
D21
F19
E20
E21
E19
D19
E18
USB20_P9 <18>
USB20_N9 <18>
GPIO16
GPIO17
USB20_P4 <28>
USB20_N4 <28>
USB-4 Card Reader (3 IN 1)
USB20_P2 <25>
USB20_N2 <25>
USB-2 Left USB
USB20_P1 <25>
USB20_N1 <25>
USB-1 Right side
USB20_P0 <25>
USB20_N0 <25>
USB-0 Right side
GPIO16 <24>
GPIO17 <24>
STRAP PIN
STRAP PIN
G20
G21
D25
D24
C25
C24
B25
C23
B24
B23
A23
C22
A22
B22
B21
A21
D20
C20
A20
B20
B19
A19
D18
C18
SB700R3@
2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Custom
A
Compal Secret Data
Date:
SB700 USB / AC97

Rev
1.0
LA-5831P
Sheet
E
21
of
44
U15B
SATA_RX0N
SATA_RX0P
SATA_STX_DRX_P1
SATA_STX_DRX_N1
AE10
AD10
SATA_TX1P
SATA_TX1N
SATA_RXN1_C
SATA_RXP1_C
AD11
AE11
SATA_RX1N
SATA_RX1P
ODD
<25> SATA_STX_DRX_P3
<25> SATA_STX_DRX_N3
<25> SATA_RXN3_C
<25> SATA_RXP3_C
+3VS
2
AD13
AE13
SATA_RXN3_C
SATA_RXP3_C
AB14
AC14
SATA_RX3N
SATA_RX3P
AE14
AD14
SATA_TX4P
SATA_TX4N
AD15
AE15
SATA_RX4N
SATA_RX4P
AB16
AC16
SATA_TX5P
SATA_TX5N
AE16
AD16
SATA_RX5N
SATA_RX5P
2
1
R343
2 10K_0402_5%
SATA_CAL V12
<33> SATA_LED#
+1.2V_HT
1
2
+3VS
L55
BLM18PG121SN1D_0603
2
Y12
SATA_X1
SATA_X2
AA12
SATA_X2
SATA_LED#
W11
SATA_ACT#/GPIO67
PLLVDD_SATA
W12
XTLVDD_SATA
C523
1 0.1U_0402_16V4Z
+XTLVDD_SATA
C524
1U_0402_6.3V4Z
SATA_CAL
SATA_X1
SATA_TX3P
SATA_TX3N
+PLLVDD_SATA AA11
C522
2.2U_0603_6.3V4Z
SATA_RX2N
SATA_RX2P
SATA_STX_DRX_P3
SATA_STX_DRX_N3
R342
1 1K_0402_1%
L54
BLM18PG121SN1D_0603 2
SATA_TX2P
SATA_TX2N
ATA 66/100/133
AE12
AD12
SPI ROM
AB12
AC12
IDE_IORDY
IDE_IRQ
IDE_A0
IDE_A1
IDE_A2
IDE_DACK#
IDE_DRQ
IDE_IOR#
IDE_IOW#
IDE_CS1#
IDE_CS3#
Part 2 of 5
HW MONITOR
<25> SATA_RXN1_C
<25> SATA_RXP1_C
AB10
AC10
SERIAL ATA
<25> SATA_STX_DRX_P1
<25> SATA_STX_DRX_N1
SATA_TX0P
SATA_TX0N
SATA PWR
HDD
SB700
AD9
AE9
C625
0.1U_0402_16V4Z
IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23
IDE_D9/GPIO24
IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30
G6
D2
D1
F4
F3
LAN_RST#/GPIO13
ROM_RST#/GPIO14
U15
J1
FANOUT0/GPIO3
FANOUT1/GPIO48
FANOUT2/GPIO49
M8
M5
M7
FANIN0/GPIO50
FANIN1/GPIO51
FANIN2/GPIO52
P5
P8
R8
TEMP_COMM
TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63
TEMPIN3/TALERT#/GPIO64
VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60
AVSS
SPK_SEL
EC_THERM#
A4
B4
C4
D4
D5
D6
A7
B7
ACIN_SB
F6
+SB_AVDD
1
C525
G7
SPK_SEL <29>
EC_THERM# <32>
L56
1
0.1U_0402_16V4Z
D41
1 CH751H-40PT_SOD323-2
ACIN
R562
2 150K_0402_5%
+3VALW
1 0_0603_5%
+3VALW
<32,33,35>
C526
2.2U_0603_6.3V4Z
SATA_X1
R341
25MHz_20pF_6X25000017
SATA_X2
10M_0402_5%
2
Y4
C517
10P_0402_50V8J 2
C6
B6
A6
A5
B5
C516
10P_0402_50V8J 2
SB700R3@
AD24
AD23
AE22
AC22
AD21
AE20
AB20
AD19
AE19
AC20
AD20
AE21
AB22
AD22
AE23
AC23
SPI_DI/GPIO12
SPI_DO/GPIO11
SPI_CLK/GPIO47
SPI_HOLD#/GPIO31
SPI_CS1#/GPIO32
AVDD
AA24
AA25
Y22
AB23
Y23
AB24
AD25
AC25
AC24
Y25
Y24
Compal Secret Data
2009-02-12
Issued Date
Title

SB700 SATA / IDE / SPI
Custom
A
2009-02-12
Deciphered Date
Date:
Rev
1.0
LA-5831P
Sheet
E
22
of
44
U15E
U15C
@ C528
22U_0805_6.3V6M
@ C531
@ C530
@ C533
@ C536
@ C535
1
1
1
1
1
2
2
2
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
@ C539
@ C541
@ C542
1
1
1
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
Y20
AA21
AA22
AE25
VDD33_18_1
VDD33_18_2
VDD33_18_3
VDD33_18_4
Part 3 of 5
CORE S0
SB700
L9
M9
T15
U9
U16
U17
V8
W7
Y6
AA4
AB5
AB21
PCI/GPIO I/O
+3VS
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
L15
M12
M14
N13
P12
P14
R11
R15
T16
+1.2V_HT_R
R593
0_0805_5%
SB700
+1.2V_HT
10U_0805_6.3V6M
C529
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
2
2
2
1
1
1
1
C532
C534
C538
C537
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
1
1
C527
C540
T10
U10
U11
U12
V11
V14
W9
Y9
Y11
Y14
Y17
AA9
AB9
AB11
AB13
AB15
AB17
AC8
AD8
AE8
L61
1 0_0805_5%
1
4.7U_0805_10V6K
C553
C555
C554
C558
2 @
2
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
1
1
1
C557 1
C560 1
P18
P19
P20
P21
R22
R24
R25
PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7
AA14
AB18
AA15
AA17
AC18
AD17
AE17
AVDD_SATA_1
AVDD_SATA_4
AVDD_SATA_2
AVDD_SATA_3
AVDD_SATA_5
AVDD_SATA_6
AVDD_SATA_7
L63
1 0_0805_5%
2
C566
C567 1
C568 1
C571 1
C572 1
1
22U_0805_6.3V6M
2 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z
SATA I/O
+1.2V_SATA
+1.2V_HT
+1.2V_HT
+1.2V_HT
POWER
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
L21
L22
L24
L25
+S5_3V
3.3V_S5 I/O
C552 2
CORE S5
CKVDD_1.2V_1
CKVDD_1.2V_2
CKVDD_1.2V_3
CKVDD_1.2V_4
CLKGEN I/O
+PCIE_VDDR
+1.2V_HT
A-LINK I/O
+3VS
IDE/FLSH I/O
No IDE device unmount CAP
S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6
S5_3.3V_7
2 @ C556
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
2
1
1
C559
C561
1U_0402_6.3V4Z
C562
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
1
1
1
C563
C564
C565
L64
0_0603_5%
1U_0402_6.3V4Z 2
1U_0402_6.3V4Z 2
S5_1.2V_1
S5_1.2V_2
+3VALW
22U_0805_6.3V6M
+S5_1.2V
USB_PHY_1.2V_1
USB_PHY_1.2V_2
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
A17
A24
B17
J4
J5
L1
L2
R564
0_0805_5%
A15
B15
C14
D8
D9
D11
D13
D14
D15
E15
F12
F14
G9
H9
H17
J9
J11
J12
J14
J15
K10
K12
K14
K15
+1.2VALW
C569
C570
1
1
G2
G4
L65
0_0603_5%
A10
B10
+1.2_USB
+1.2VALW
10U_0805_10V4Z 1
2 @ C573
1U_0402_6.3V4Z
C574
0.1U_0402_16V4Z
C575
AVSS_SATA_1
AVSS_SATA_2
AVSS_SATA_3
AVSS_SATA_4
AVSS_SATA_5
AVSS_SATA_6
AVSS_SATA_7
AVSS_SATA_8
AVSS_SATA_9
AVSS_SATA_10
AVSS_SATA_11
AVSS_SATA_12
AVSS_SATA_13
AVSS_SATA_14
AVSS_SATA_15
AVSS_SATA_16
AVSS_SATA_17
AVSS_SATA_18
AVSS_SATA_19
AVSS_SATA_20
AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9
AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24
+AVDD_USB
C576 1
C577 1
2 10U_0805_10V4Z
2 10U_0805_10V4Z
C580 1
C581 1
2 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z
C583 1
C582 1
C584 1
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
A16
B16
C16
D16
D17
E17
F15
F17
F18
G15
G17
G18
AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDTX_4
AVDDTX_5
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3
AVDDRX_4
AVDDRX_5
V5_VREF
AVDDCK_3.3V
PLL
L66
1 0_0805_5%
USB I/O
+3VALW
AVDDCK_1.2V
AVDDC
AE7
+V5_VREF
J16
+AVDDCK_3.3V
K17
+AVDDCK_1.2V
E9
+AVDDC
C578
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+AVDDCK_1.2V
+AVDDCK_3.3V
R346
1 1K_0402_5%
+5VS
D14
2 CH751H-40PT_SOD323-2
+3VS
1U_0603_10V4Z
L67
1 0_0603_5%
2.2U_0603_6.3V4Z
218S7EALA11FG_BGA528_SB700 SB700R3@
2
C579
H18
J17
J22
K25
M16
M17
M21
P16
F9
+3VALW
PCIE_CK_VSS_1
PCIE_CK_VSS_2
PCIE_CK_VSS_3
PCIE_CK_VSS_4
PCIE_CK_VSS_5
PCIE_CK_VSS_6
PCIE_CK_VSS_7
PCIE_CK_VSS_8
AVSSC
GROUND
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
PCIE_CK_VSS_9
PCIE_CK_VSS_10
PCIE_CK_VSS_11
PCIE_CK_VSS_12
PCIE_CK_VSS_13
PCIE_CK_VSS_14
PCIE_CK_VSS_15
PCIE_CK_VSS_16
PCIE_CK_VSS_17
PCIE_CK_VSS_18
PCIE_CK_VSS_19
PCIE_CK_VSS_20
PCIE_CK_VSS_21
Part 5 of 5
AVSSCK
C585
C586
SB700R3@
L68
1 0_0603_5%
2
2.2U_0603_6.3V4Z
C587
0.1U_0402_16V4Z
C588
L69
1 0_0603_5%
2
2.2U_0603_6.3V4Z
1 C589
0.1U_0402_16V4Z
1 C590
A2
A25
B1
D7
F20
G19
H8
K9
K11
K16
L4
L7
L10
L11
L12
L14
L16
M6
M10
M11
M13
M15
N4
N12
N14
P6
P9
P10
P11
P13
P15
R1
R2
R4
R9
R10
R12
R14
T11
T12
T14
U4
U14
V6
Y21
AB1
AB19
AB25
AE1
AE24
P23
R16
R19
T17
U18
U20
V18
V20
V21
W19
W22
W24
W25
L17
+1.2V_HT
+3VS
2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Custom
A
Compal Secret Data
Date:
SB700 Power / GND

Rev
1.0
LA-5831P
Sheet
E
23
of
44
REQUIRED STRAPS
NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLK5
LPC_CLK0
LPC_CLK1
RTC_CLK AZ_RST_CD#
BOOTFAIL
TIMER
ENABLED
USE
DEBUG
STRAPS
RESERVED
RESERVED
ENABLE PCI
MEM BOOT
CLKGEN
ENABLED
INTERNAL
RTC
EC
ENABLED
DEFAULT
DEFAULT
+3VALW
1
R352
R353
+3VALW
+3VALW
R355
R356
2.2K_0402_5%
2.2K_0402_5%
10K_0402_5%
2
10K_0402_5%
L,H = LPC ROM (Default)

L,L = FWH ROM
R354
10K_0402_5%
+3VALW
1
R351
@
10K_0402_5%
DEFAULT
10K_0402_5%
2
R350
@
10K_0402_5%
1
R349
@
10K_0402_5%
+3VALW
R348
@
10K_0402_5%
+3VALW
R347
@
+3VS
+3VS
DEFAULT
EC
DISABLED
DEFAULT
H,L = SPI ROM
EXT. RTC
(PD on X1,
apply
32KHz to
RTC_CLK)
CLKGEN
DISABLED
H,H = Reserved
DISABLE PCI
MEM BOOT
+3VS
+3VS
IGNORE
DEBUG
STRAPS
GP16
Internal pull up
DEFAULT
BOOTFAIL
TIMER
DISABLED
GP17
PULL
LOW
PULL
HIGH
SI2: mount 2.2K
R358
10K_0402_5%
10K_0402_5%
R359
R361
R362
10K_0402_5%
10K_0402_5%
10K_0402_5%
1
R360
R363
R364
R365
2.2K_0402_5%
10K_0402_5%
2.2K_0402_5%
2
@
2
@
10K_0402_5%
R366
2.2K_0402_5%
2
R357
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLK5
CLK_PCI_EC
CLK_PCI_SIO2
RTC_CLK
HDARST#
GPIO17
GPIO16
1
<20>
<20>
<20>
<20>
<20,32>
<20,31>
<20>
<21>
<21>
<21>
Need to confirm if SB SPI ROM will mount
DEBUG STRAPS
SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]
PCI_AD28
PULL
HIGH
3
PULL
LOW
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
USE PCI
PLL
USE ACPI
BCLK
USE IDE
PLL
USE DEFAULT
PCIE STRAPS
RESERVED
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
USE
SHORT
RESET
BYPASS
PCI PLL
BYPASS
ACPI
BCLK
BYPASS IDE
PLL
USE EEPROM
PCIE STRAPS
1
R376
R377
R378
2.2K_0402_5%
2
R375
@
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2
@
2.2K_0402_5%
2.2K_0402_5%
2
R374
R373
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
1
<20>
<20>
<20>
<20>
<20>
<20>
PCI_AD27
USE
LONG
RESET
Compal Secret Data
2009-02-12
Issued Date
Title
Custom
A
2009-02-12
Deciphered Date
Date:
SB700 STRAPS
Rev
1.0
LA-5831P
Sheet
E
24
of
44
SATA HDD Conn.

+5VS
SATA ODD Conn
Place closely JHDD0 SATA CONN.

1.2A
C387
C388
+5VS
C389
C390
1.1A
JHDD0
10U_0805_10V4Z
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
GND
A+
AGND
BB+
GND
24
23
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
GND
GND
1
2
3
4
5
6
7
SATA_TXP1
SATA_TXN1
SATA_IRX_DTX_N1
SATA_IRX_DTX_P1
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
C512 1
C513 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
C410 1
C412 1
SATA_STX_DRX_P1 <22>
SATA_STX_DRX_N1 <22>
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_RXN1_C <22>
SATA_RXP1_C <22>
1
C416
@
10U_0805_10V4Z 1U_0402_6.3V4Z
2
2
C414
10U_0805_10V4Z
C415
1
C417
0.1U_0402_16V4Z
C418
0.1U_0402_16V4Z
+3VS
JODD
+5VS
OCTEK_SAT-22SO1G_RV
15
14
GND
GND
GND
A+
AGND
BB+
GND
1
2
3
4
5
6
7
DP
+5V
+5V
MD
GND
GND
8
9
10
11
12
13
SATA_TXP3
SATA_TXN3
C518
C519
1
1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_IRX_DTX_N3 C424
SATA_IRX_DTX_P3 C425
1
1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_STX_DRX_P3 <22>
SATA_STX_DRX_N3 <22>
SATA_RXN3_C <22>
SATA_RXP3_C <22>
+5VS
SANTA_206401-1_RV
2
USB Right Board
USB Left Conn

W=60mils
2A
+5VALW
<32>
USB_EN#0
USB_EN#0
8
7
6
5
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
RT9715BGS_SO8
3
+USB_VCCB
U19
U25
1
2
3
4
W=60mils
2A
+5VALW
+USB_VCCA
1
2
0_0402_5%
1 R422
C438
@
4.7U_0805_10V4Z
2
1
2
3
4
USB_EN#2
<32> USB_EN#2
USB_OC#0 <21,32>
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
8
7
6
5
1 R584
2
0_0402_5%
RT9715BGS_SO8
USB_OC#2 <21,32>
C367
4.7U_0805_10V4Z
@
3
For ESD
+USB_VCCA
W=60mils
R1026
<21>
USB20_N0
<21>
USB20_P0
0_0402_5%
L50
2
3
WCM-2012-900T_0805
R1027
USB20_N0_R
USB20_P0_R
USB20_N1_R
USB20_P1_R
JUSBB
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
2
3
C352
C351
2
220U_6.3V_M 2
1000P_0402_50V7K
R95
GND
GND
2 0_0402_5%
13
14
<21>
USB20_N2
<21>
USB20_P2
L46
JUSB
2
1
2
3
4
USB20_N2_R
USB20_P2_R
WCM-2012-900T_0805
0_0402_5%
C350
PJDLC05_SOT23-3
ACES_85201-1205N
R1028
0.1U_0402_16V4Z
1
1
0_0402_5%
W=60mils
+USB_VCCB
D11
VCC
DD+
GND
@
GND
GND
GND
GND
5
6
7
8
P-TWO_CU304G-A0G1G-P
L51
R96
<21>
USB20_N1
<21>
USB20_P1
WCM-2012-900T_0805
R1029
2008/04/14
2009/04/14
Deciphered Date
Title
Custom
A
2 0_0402_5%
Compal Secret Data
Issued Date
0_0402_5%
Date:
SATA HDD/ODD
Rev
1.0
LA-5831P
Sheet
E
25
of
44
Place Close to Chip
CL2 1
2 0.1U_0402_16V7K PCIE_PTX_IRX_P3
20
HSOP
<11> PCIE_PTX_C_IRX_N3
CL1 1
2 0.1U_0402_16V7K PCIE_PTX_IRX_N3
21
HSON
<11> PCIE_ITX_C_PRX_P3
<16> CLK_PCIE_LAN
<16> CLK_PCIE_LAN#
<16> CLKREQ_LAN#
<12,15,20,27,31,32> PLT_RST#
1
PCIE_ITX_C_PRX_P3
15
HSIP
PCIE_ITX_C_PRX_N3
16
HSIN
CLK_PCIE_LAN
CLK_PCIE_LAN#
17
18
CLKREQ_LAN#
25
PLT_RST#
27
RL3
2 2.49K_0402_1%
<21> LAN_WAKE#
26
28
LAN_X1
LAN_X2
41
42
RTL8103EL-GR
REFCLK_P
REFCLK_M
CLKREQB
PERSTB
46
LAN_WAKE#
ISOLATEB
33
34
35
32
LAN_DO
LAN_DI
LAN_SK_LAN_LINK#
LAN_CS
LED0
38
LAN_ACTIVITY#
MDIP0
MDIN0
MDIP1
MDIN1
NC
NC
NC
NC
2
3
5
6
8
9
11
12
LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-
LED3/EEDO
LED2/EEDI/AUX
LED1/EESK
EECS
RSET
LANWAKEB
ISOLATEB
RL4
2 10K_0402_5%
LAN_WAKE#
NC
NC
7
14
31
47
GND
GND
GND
GND
22
GNDTX
2 3.6K_0402_5%
RL2
1 1K_0402_5%
+LAN_VDD12
+3V_LAN
Close to Pin10,13,30,36
2
CL3
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CL5
0.1U_0402_16V4Z
48
CL6
0.1U_0402_16V4Z
+LAN_VDD12
Close to Pin45
VCTRL12
VDDTX
DVDD12
DVDD12
DVDD12
DVDD12
19
30
36
13
10
NC
39
NC
VCTRL12D
44
45
VDD33
VDD33
29
37
1
1
R97
R98
AVDD33
NC
NC
1
40
43
R105 2 0_0402_5%
CL7
0.1U_0402_16V4Z
+EVDD12
+LAN_VDD12
+EVDD12
Close to Pin19
2
+LAN_VDD12
2 0_0402_5%
2 0_0402_5%
CL8
1U_0402_6.3V4Z
CL9
1U_0402_6.3V4Z
+3V_LAN
+3V_LAN
Close to Pin1,37,29
Reserve bead for EMI

2
RTL8103EL-GR_LQFP48_7X7
+3VS
CL4
VCTRL12A
CKXTAL1
CKXTAL2
23
24
T27 PAD
RL1
NC
+3V_LAN
1
UL1
<11> PCIE_PTX_C_IRX_P3
<11> PCIE_ITX_C_PRX_N3
CL10
0.1U_0402_16V4Z
CL11
0.1U_0402_16V4Z
CL12
0.1U_0402_16V4Z
1
2
RL5
1K_0402_1%
ISOLATEB
R70 @
2
Close to Pin48
VCTRL12
WOL_EN# <32,34>
YL1
0_0402_5%
RL6
15K_0402_5%
CL13
Reserve R70 for cost down
27P_0402_50V8J
LAN_X1
1
LAN_X2
25MHz_20pF_6X25000017
2
CL14
CL16
10U_0805_10V4Z
CL21
LAN_ACTIVITY#
RL9
1 150_0402_1%
RL10
1 150_0402_1%
2
2
+3V_LAN
< LAN Conn >

1
JLAN
12
11
2
2
CL17
0.01U_0402_25V7K
CL19
0.01U_0402_25V7K
Add CL18, CL20

for customer request
UL2
LAN_MDI1+
LAN_MDI1-
1
2
3
4
5
6
7
8
TD+
TDCT
NC
NC
CT
RD+
RD-
TX+
TXCT
NC
NC
CT
RX+
RX-
16
15
14
13
12
11
10
9
RJ45_MIDI0+
RJ45_MIDI01
CL18
2 1000P_0402_50V8-J
CL20
2 1000P_0402_50V8-J
7
RJ45_MIDI1-
RL7
2 75_0402_1%
RL8
2 75_0402_1%
6
5
4
RJ45_MIDI1+
RJ45_MIDI1-
0.1U_0402_16V4Z
LAN_MDI0+
LAN_MDI0-
27P_0402_50V8J
68P_0402_50V8J
Place these components

colsed to LAN chip
CL15
@
1
RJ45_GND
CL22
LF-H1201P-2
LAN_SK_LAN_LINK#2
+3V_LAN
68P_0402_50V8J
1
RL11
150_0402_1%
RL12
150_0402_1%
RJ45_MIDI1+
RJ45_MIDI0-
RJ45_MIDI0+
1
10
9
Yellow LEDYellow LED+
PR4PR4+
PR2PR3PR3+
PR2+
PR1SHLD2
PR1+
SHLD1
14
13
Green LEDGreen LED+

TYCO_2068888-1_12P-T
RJ45_GND
CL23
2 1000P_1808_3KV7K
LANGND
1
CL24
0.1U_0402_16V4Z
CL25
4.7U_0603_6.3V6K
Compal Secret Data
2009-02-12
Issued Date
Title

RTL8103EL 10 / 100 LAN
Custom
A
2009-02-12
Deciphered Date
Date:
Rev
1.0
LA-5831P
Sheet
E
26
of
44
< PCIe Mini Card for WLAN/ WiMAX >

+1.5VS
1
CM20
0.01U_0402_25V7K
+3VS
CM21
0.1U_0402_16V4Z
CM22
4.7U_0805_10V4Z
CM17
0.01U_0402_25V7K
+1.5VS
JWLAN
CLKREQ_MCARD2#
<16> CLKREQ_MCARD2#
CLK_PCIE_MCARD2#
CLK_PCIE_MCARD2
<16> CLK_PCIE_MCARD2#
<16> CLK_PCIE_MCARD2
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2
<11> PCIE_PTX_C_IRX_N2
<11> PCIE_PTX_C_IRX_P2
PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_P2
<11> PCIE_ITX_C_PRX_N2
<11> PCIE_ITX_C_PRX_P2
+3VS
E51_TXD
E51_RXD
RM6
RM7
2 0_0402_5%
2 0_0402_5%
1
1
E51_TXD_R
E51_RXD_R
0.1U_0402_16V4Z
53
RM8
100K_0402_5%
GND1
CM19
4.7U_0805_10V4Z
+3VS
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
WL_OFF#
PLT_RST#
WL_OFF# <32>
PLT_RST# <12,15,20,26,31,32>
SMB_CK_CLK1
SMB_CK_DAT1
USB20_N8
USB20_P8
SMB_CK_CLK1 <21>
SMB_CK_DAT1 <21>
USB20_N8 <21>
USB20_P8 <21>
2
1
RN3
<32> E51_TXD
<32> E51_RXD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
CM18
GND2
54
2 PLT_RST#
100K_0402_5%
ACES_88911-5204
<NB & SB >

< R1 for customer BOM STRUCTURE >
< R3 for mass production BOM STRUCTURE >
< PCB >
U3
RS780MN
U3
ZZZ
RS780MN
RS780MN R1
RS780MNR1@
PCB
RS780MN R3
RS780MNR3@
PCB 075 LA-5831P REV1 M/B
U3
RS780MC
RS780MC R1
RS780MCR1@
U15
SB700
SB700R1
SB700R1@
4
2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title

WLAN / CAMERA
Custom
A
Compal Secret Data
Date:
Rev
1.0
LA-5831P
Sheet
E
27
of
44
CC1
1 0.1U_0402_16V4Z
RC1
1 0_0402_5%
UC1
CC2
+3VS_CR
RC2
2 0_0603_5%
+3VS
+3VALW
1
3
7
9
11
33
1 0.1U_0402_16V4Z
+3VS_CR
1
+VCC_3IN1
RC3
2 0_0603_5%
CC3
0.1U_0402_16V4Z
VREG
MS_D4
NC
CC4
XTLI
8
44
45
47
48
USB20_N4
USB20_P4
CR_LED#
4
5
14
RST#_R
MODE SEL
1U_0402_6.3V4Z
<21>
<21>
confirm that whether can be removed
AV_PLL
NC
NC
CARD_3V3
D3V3
D3V3
USB20_N4
USB20_P4
3V3_IN
RST#
MODE_SEL
XTLO
XTLI
XD_CLE_SP19
XD_CE#_SP18
XD_ALE_SP17
SD_DAT2/XD_RE#_SP16
SD_DAT3/XD_WE#_SP15
XD_RDY_SP14
SD_DAT4/XD_WP#/MS_D7_SP13
SD_DAT5/XD_D0/MS_D6_SP12
SD_CLK/XD_D1/MS_CLK_SP11
MS_INS#_SP9
XD_D5_SP5
XD_D4/SD_DAT1_SP4
SD_CD#_SP3
SD_WP_SP2
XD_CD#_SP1
EEDI
DM
DP
GPIO0
2
RC8
100K_0402_5%
RST#
RC9
1 0_0402_5%
RST#_R
CC8
RREF
DGND
DGND
6
46
AGND
AGND
CC5
1U_0402_6.3V4Z
43
42
41
40
39
38
37
35
34
31
29
28
27
26
25
23
21
20
19
18
XTAL_CTR
MS_D5
13
24
EEDO
EECS
EESK
SD_CMD
15
16
17
36
For EMI
SD_DATA2
SD_DATA3
SD_MS_CLK
MS_DATA3_SD_DATA6
MSCD#
MS_DATA2_SD_DATA7
SD_MS_DATA0
MS_DATA1
MSBS
SD_DATA1
SDCD#
SDWP#
RC4
2 22_0402_5% SDCLK
RC6
2 22_0402_5% MSCLK
1
1
RC5
2 10_0402_5%
CC6
10P_0402_50V8J
RC7
2 10_0402_5%
CC7
10P_0402_50V8J
XTAL_CTR
SDCMD
RC10
0_0402_5%
RC11
RC12
RTS5159-VDD-GR
0_0402_5%
1
6.19K_0402_1%
1
CC9
0.1U_0402_16V4Z
@
2
MODE SEL
2
12
32
1U_0402_6.3V4Z
+3VS_CR
10
22
30
< Card Reader LED >

< 3 in 1 Card Reader >
JREAD
1
RC13
22
120_0402_5%
DC1
HT-110UYG-CT_YEL/GRN
Vf=1.9V(typ),2.4V(max)
B
CR_LED#
22
23
Cost-down option
XTLI
RC15
2 0_0402_5%
R925
33_0402_5%
@
XTAL_CTR
2
+3VS_CR
NC
YES
NC
47P
MSBS
SDCLK
MS_DATA1
SD_MS_DATA0
+VCC_3IN1
MS_DATA2_SD_DATA7
1
MSCD#
MS_DATA3_SD_DATA6
SDCMD
MSCLK
CC10
0.1U_0402_16V4Z
CC11
1U_0402_6.3V4Z
B
SD_DATA3
SD_DATA2
SDCD#
YES
NC
NC
NC
680P
@
C919
22P_0402_50V8J
Description
Recommended
YES
Compatible with RTS5158E
YES
LED ON
10K 180P
LED ON
A
10K 680P
YES
Compal Secret Data
2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title

RTS5159 Card Reader
Custom
5
SDWP#
SD_DATA1
SD_MS_DATA0
USB AUTO DE-LINK MS FORMATTER
For EMI
1
<16> CLK_48M_CR
RC14
2 0_0402_5%
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
TAITW_R009-125-LR_RV
CR_LED: Low when card reader is being accessed.
< 48MHz >
SD-WP
SD-DAT1
SD-DAT0
SD-GND
MS-GND
MS-BS
SD-CLK
MS-DAT1
MS-DAT0
SD-VCC
MS-DAT2
SD-GND
MS-INS
MS-DAT3
SD-CMD
MS-SCLK
MS-VCC
SD-DAT3
MS-GND
GND1 SD-DAT2
GND2
SD-CD
+3VS
Date:
Rev
1.0
LA-5831P
Sheet
1
28
of
44
+3VS_DVDD
30mil
+AVDD
1
10U_0805_10V4Z
CA4
10U_0805_10V4Z
CA5
0.1U_0402_16V4Z
0.1U_0402_16V4Z
15
Ext. Mic
CA14 1
MIC2_L
<30>
MIC2_R
<30> MIC1_C_L
<30> MIC1_C_R
2 100P_0402_50V8J
<21> HDA_BITCLK_CODEC
<21> HDA_SDOUT_CODEC
2
<21> HDA_SDIN0
<21> HDA_RST#_CODEC
<21> HDA_SYNC_CODEC
<22>
MUTE#
38
DVDD
LINE2-L
LOUT1_L
LINE2-R
LOUT1_R
35
AMP_SPK_L
36
AMP_SPK_R
AMP_SPK_L <30>
AMP_SPK_R <30>
MIC2_L
LOUT2_L
39
MIC2_R
LOUT2_R
41
23
LINE1_L
SPDIFO1
48
24
LINE1_R
SPDIFO2
45
MIC1_C_L
21
MIC1_L
HPOUT_L
33
HPL
RA5
2 63.4_0402_1%
HP_L
<30>
MIC1_C_R
22
MIC1_R
HPOUT_R
32
HPR RA6
2 63.4_0402_1%
HP_R
<30>
MONO_IN
12
MONO_OUT
37
HDA_BITCLK_CODEC
BITCLK
DMIC_CLK1/2
46
HDA_SDOUT_CODEC
SDATA_OUT
DMIC_CLK3/4
44
1 33_0402_5% HDA_SDIN0_R
SDATA_IN
LINE2_VREFO
20
HDA_RST#_CODEC
11
RESET#
LINE1_VREFO
18
HDA_SYNC_CODEC
10
SYNC
MIC1_VREFO
28
MIC2_VREFO
19
13
SENSE_B
<30>
10U_0805_10V4Z
17
SENSE_A
MUTE#
CA8
16
GPIO63-->SPK_SEL HIGH: HARMAN

LOW: NO-BRAND
0.1U_0402_16V4Z
MIC2_R
SPK_SEL
SPK_SEL
10U_0805_10V4Z
MIC2_L
RA7
2
CA7
DVDD_IO
14
AVDD2
AVDD1
UA2
25
<30>
CA6
Remove LDO
Int. Mic
0.1U_0402_16V4Z
+3VS
CA2
RA39 1
34
2 0_0402_5%
47
GPIO0/DMIC_DATA1/2
CPVREF
GPIO1/DMIC_DATA3/4
VREF
SENSE A
JDREF
SENSE B
CBN
EAPD
CBP
10mil
10mil
+MIC2_VREFO
CA16 1
31
27
+MIC1_VREFO
2 2.2U_0603_6.3V6K
AC_VREF
40
AC_JDREF
30
CA17 1
1
RA10
2.2U_0603_6.3V6K
29
CA18
CA19
2
10U_0805_10V4Z
0.1U_0402_16V4Z
20K_0402_1%
NC
2
43
BEEP_IN
40mil
RA3
1 0_0603_5%
1
CA3
+5VS
RA1
1 0_0603_5%
2
1
CA1
4
7
For EMI
@
HDA_BITCLK_CODEC
C618 1
2
100_0402_5%
@
1
R313
DGND
2 100P_0402_50V8J
DVSS
DVSS
AVSS1
AVSS2
26
42
ALC272-GR_LQFP48
AGND
1
RA12
1
RA13
1
RA14
1
RA15
1
RA19
< SENSE_A & SENSE_B, place close to chip >

1
<30>
NBA_PLUG
MIC@
1
Sense Pin
SENSE_A
RA16
2 5.1K_0402_1%
SENSE_B
Add RA19 for EMI
RA17
2 20K_0402_1%
Impedance
39.2K
< MONO_IN SOURCE >
Codec Signals
Function
PORT-A (PIN 39, 41)
20K
PORT-B (PIN 21, 22)
10K
PORT-C (PIN 23, 24)
5.1K
PORT-D (PIN 35, 36)
39.2K
PORT-E (PIN 14, 15)
20K
PORT-F (PIN 16, 17)
10K
PORT-H (PIN 37)
5.1K
PORT-I (PIN 32, 33)
EC Beep <32> EC_BEEP
RA8
2 47K_0402_5%
PCI Beep <21> SB_SPKR
RA9
2 47K_0402_5%
CA15
2 0.1U_0402_16V4Z MONO_IN
Ext. MIC
RA11
10K_0402_5%
SPK out
SENSE B
CA20
0.1U_0402_16V4Z
4
Int. MIC
/
Headphone out
Compal Secret Data
2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title

HD Audio ALC272 Codec
Custom
A
SENSE A
RA18
2 20K_0402_1%
<30> MIC_SENSE
2
0_0603_5%
2
0_0603_5%
2
0_0603_5%
2
0_0603_5%
2
0_0603_5%
Date:
Rev
1.0
LA-5831P
Sheet
E
29
of
44
< TPA6017 Medium Range Amplifier >

+5VS
< Ext. Mic >

1
CA23
10U_0805_10V4Z
CA24
0.1U_0402_16V4Z
CA25
10 dB
CA32
0.033U_0402_16V7K LINE_C_OUTL
<29> AMP_SPK_L
+MIC1_VREFO
MIC1_L
MIC1_R
1 1K_0402_5%
RA22
RA23
1 4.7K_0402_5%
16
15
6
DA2
2 CH751H-40PT_SOD323-2
+MIC1_VREFO
1
GAIN1
RINROUT+
18
SPKR+
ROUT-
14
SPKR-
SPKL+
SPKL-
LIN+
100K_0402_5%
GAIN0
LOUT+
5
1 4.7U_0805_10V4Z
< Int. Mic >
RA29
RA30
100K_0402_5%
100K_0402_5%
+MIC2_VREFO
close to JMIC
LINLOUT-
<29> MIC1_C_R
CA22 2
DA1
2 CH751H-40PT_SOD323-2
RA21
1 1K_0402_5%
CA31
0.033U_0402_16V7K
17
RIN+
<29> AMP_SPK_R
@
100K_0402_5%
CA30
0.033U_0402_16V7K LINE_C_OUTR
1 4.7U_0805_10V4Z
RA28
CA29
0.033U_0402_16V7K
<29> MIC1_C_L
CA21 2
+5VS
RA27
VDD
PVDD1
PVDD2
UA3
1
RA20
1 4.7K_0402_5%
0.1U_0402_16V4Z
DA3
RA24
4.7K_0402_5%
MIC@
MIC@
2
1
For EMI
NC
MUTE#
19
21
20
13
11
1
MIC@
CA26
1 1U_0402_6.3V4Z
AMP_BYPASS
10
BYPASS
SHUTDOWN
GND5
GND1
GND2
GND3
GND4
<29> MUTE#
PJDLC05_SOT23-3
Keep 10 mil width
12
<29>
MIC2_L
<29>
MIC2_R
MIC@
RA25
1 1K_0402_5%
MIC@
LA12
JMIC @
1
2INT_MIC_L 1 1 NC1 3
SBY100505T-121Y-N
2 2 NC2 4
MIC@
LA11
ACES_85204-0200N
1
2
SBY100505T-121Y-N
INT_MIC
CA33
0.47U_0603_10V7K
1 1U_0402_6.3V4Z
CA28
MIC@
TPA6017A2_TSSOP20
1 1K_0402_5%
RA26
MIC@
CA27
1
2
220P_0402_50V7K
MIC@
close to Codec
close to JMIC
GAIN0 GAIN1 Av(db) Rin(ohm)

2
90K
10
70K
0 15.6
45K
1 21.6
25K
DA9
Left Connector
< Speaker Connector >
2
1
3
LA3 FBMA-L11-160808-800LMT_0603
1
2
1
2
SPKL+
SPKL-
JSPKL
PJDLC05_SOT23-3
SPK_L1
SPK_L2
1
2
LA4 FBMA-L11-160808-800LMT_0603
DA10
1
3
LA5 FBMA-L11-160808-800LMT_0603
1
2
1
2
JSPKR
PJDLC05_SOT23-3
SPK_R1
SPK_R2
1
2
LA6 FBMA-L11-160808-800LMT_0603
< Volume Control >
3
4
Right Connector
SPKR+
SPKR-
1 NC1
2 NC2
ACES_85204-0200N
@
1 NC1
2 NC2
@
3
4
ACES_85204-0200N
< HeadPhone JACK >

+3VS
JLINE
5
1
NBA_PLUG
<29> NBA_PLUG
RA32
100K_0402_5%
<29>
HP_R
L35 1
<29>
HP_L
L36 1
2 KC FBM-L11-160808-121LMT 0603
HP_R_L
2 KC FBM-L11-160808-121LMT 0603
HP_L_L
+3VS
3
6
2
1
FOX_JA6333L-B3T0-7F
DA8
CA36
0.1U_0402_16V4Z
2
1
3
1
10K_0402_5%
+3VS
RA35
2 10K_0402_5%
0.01U_0402_25V7K
SW_XRE094_3P
< Ext.MIC/LINE IN JACK >
4
UA5
74LVC1G14GW_SOT353-5
1
2
3
4
5
6
7
RA36
2 10K_0402_5%
CA37
+3VS
UA4
NC
DIP
1
3
10K_0402_5%
COM
CA35
0.1U_0402_16V4Z
2
RA34
DIP
SW2
PJDLC05_SOT23-3
RA33
CA38
0.01U_0402_25V7K
CD1#
D1
CP1
SD1#
Q1
Q1#
GND
VCC
CD2#
D2
CP2
SD2#
Q2
Q2#
14
13
12
11
10
09
08
74LCX74MTC_TSSOP14
JEXMIC
<29> MIC_SENSE
MIC1_R LA9
4
3
6
2
1
2 KC FBM-L11-160808-121LMT 0603
MIC1_L_R
MIC1_L LA10 1
2 KC FBM-L11-160808-121LMT 0603
MIC1_L_L
CA39
0.1U_0402_16V4Z
2
FOX_JA6333L-B3T0-7F
DA7
2
4
3
PJDLC05_SOT23-3
CA40
100P_0402_50V8J
@
Compal Secret Data
2009-02-12
Issued Date
ENCODER_DIR <32>
ENCODER_PULSE <32>
2009-02-12
Deciphered Date
Title
CA41
100P_0402_50V8J
@
AMP / Audio Jack / HP / SPEAKER / VR
Custom
Date:
5
MIC_SENSE
Rev
1.0
LA-5831P
Sheet
E
30
of
44
< SPI Flash 8Mb*1 >
C786
0.1U_0402_16V4Z
C877
@
10P_0402_50V8J
U46
C878
@
10P_0402_50V8J
VCC
HOLD
SPI_CS# 1
<32> SPI_CS#
SPI_CLK 6
<32> SPI_CLK
+3VL
20mils
1
<32> EC_SO_SPI_SI
VSS
< MDC 1.5 Conn >
S
C
+3VALW
EC_SI_SPI_SO <32>
JMDC
MX25L8005M2C-15G
1
HDA_SDOUT_MDC 3
5
HDA_SYNC_MDC 7
HDA_SDIN1_MDC 9
HDA_RST#_MDC 11
<21> HDA_SDOUT_MDC
MDC@
R495 1
2 33_0402_5%
2
4
6
8
10
12
HDA_BITCLK_MDC
HDA_BITCLK_MDC <21>
<21> HDA_SYNC_MDC
<21> HDA_SDIN1
<21> HDA_RST#_MDC
GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK
GND
GND
GND
GND
GND
GND
R496
@
10_0402_5%
13
14
15
16
17
18
ACES_88018-124G
< LPC Debug Port >
Connector for MDC Rev1.5
Please place the PAD under DDR DIMM.

+3VS
SERIRQ
<20,32> SERIRQ
<20,32> LPC_AD3
<20,32> LPC_AD1
PLT_RST#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
10
R622
2 0_0402_5%
C777
@
10P_0402_50V8J
LPC_FRAME#
+3VALW
PLT_RST# <12,15,20,26,27,32>
LPC_AD2 <20,32>
LPC_AD0 <20,32>
MDC@
C778
1000P_0402_50V7K
MDC@
C779
0.1U_0402_16V4Z
MDC@
C780
4.7U_0805_10V4Z
CLK_PCI_SIO2 <20,24>
2
<20,32> LPC_FRAME#
H1
R634
@
22_0402_5%
1
DEBUG_PAD
C639
@
22P_0402_50V8J
For EMI
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1
R502
2
300_0402_5%
+3VS
1
R503
2
300_0402_5%
+3VS
KSO14
KSO6
KSO2
KSO1
KSO0
KSO4
KSO3
KSO5
KSO14
KSO6
KSO7
KSO13
KSO8
KSO9
KSO10
KSO11
KSO12
KSO15
KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1
2
1
CAPS_LED# R509 300_0402_5%
CURS_LED#
NUM_LED#
KSO7
KSO13
KSO8
KSO9
KSO10
KSO11
KSO12
KSO15
KSI7
KSI2
KSI3
KSI4
KSI0
+3VS
CAPS_LED# <32>
CURS_LED# <32>
NUM_LED# <32>
KSI5
KSI6
KSI1
ACES_88170-3400
CAPS_LED#
CURS_LED#
NUM_LED#
A
<33>
TP_SWL
TP_SWL
SW8
SMT1-05_4P
<33>
TP_SWR
TP_SWR
C889
180P_0402_50V8J
@ 2
C890
180P_0402_50V8J
@ 2
D86
PJDLC05_SOT23-3
@
For EMI
D85
PJDLC05_SOT23-3
@
For EMI
Compal Secret Data
2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title

SPI / LPC / MDC
Custom
Date:
6
5
KSO5
JKB @
Right Switch
SW7
SMT1-05_4P
KSO3
3
Left switch
KSO4
KSO0
<32>
KSO[0..15] <32>
6
5
KSI[0..7]
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
KSI[0..7]
KSO[0..15]
1
C725
1
C717
1
C721
1
C609
1
C724
1
C728
1
C730
1
C715
1
C732
1
C733
1
C740
1
C737
1
C729
1
C738
1
C718
1
C736
1
C716
1
C741
1
C726
1
C723
1
C731
1
C739
1
C735
1
C734
1
C722
1
C727
1
C714
KSO1
KEYBOARD CONN.
KSO2
Rev
1.0
LA-5831P
Sheet
E
31
of
44
+3VL
+3VL_EC
L25
1 0_0603_5%
+EC_AVCC
9
22
33
96
111
125
<21> GATEA20
<21> KB_RST#
<20,31> SERIRQ
<20,31> LPC_FRAME#
<20,31> LPC_AD3
<20,31> LPC_AD2
<20,31> LPC_AD1
<20,31> LPC_AD0
Reserve for EMI request

@
R530
2 33_0402_5%
<20,24> CLK_PCI_EC
R533 1
<12,15,20,26,27,31> PLT_RST#
2 47K_0402_5%
<21> EC_SCI#
<33> WL_LED#
C811
+3VS
2.2K_0402_5% 2
1 R986
EC_SMB_DA2
2.2K_0402_5% 2
1 R987
EC_SMB_CK2
2.2K_0402_5% 2
1 R988
EC_SMB_DA1
<31>
KSI[0..7]
<31>
KSO[0..15]
KSI[0..7]
KSO[0..15]
EC_SMB_CK1
4.7K_0402_5% 2
1 R991
TP_CLK
4.7K_0402_5% 2
1 R992
TP_DATA
+3VALW
100K_0402_5% 1
2 R995
LID_SW#
+3VL
100K_0402_5% 1
+5VS
1 R989
R996
<36>
<36>
<7>
<7>
<21>
<21>
<21>
<33>
ON/OFFBTN#
47K_0402_5% 1
R998
KSO1
47K_0402_5% 1
R999
KSO2
1
1 R993
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
LID_SW#
<33> ESB_CK
<33> ESB_DA
1 R994
SUSP#
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
LID_SW#
ESB_CK
ESB_DA
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
CRY1
122
123
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
PS2 Interface
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
68
70
71
72
DAC_BRIG
EN_DFAN1
IREF
CHGVADJ
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
83
84
85
86
87
88
USB_EN#2
USB_EN#0
ENCODER_DIR
ENCODER_PULSE
TP_CLK
TP_DATA
NC
OSC
NC
OSC
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
WOL_EN#
USB_OC#2
VGATE
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#
119
120
126
128
EC_SI_SPI_SO
EC_SO_SPI_SI
SPI_CLK_R
SPI_CS#
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
73
74
89
90
91
92
93
95
121
127
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
GPI
V18R
2 0_0603_5%
1
+EC_AVCC
OVP component
ADP_I
<37>
C896
2 0.22U_0603_16V4Z
Reserve pull high for cap. sensor

+3VL
USB_EN#2 <25>
USB_EN#0 <25>
ENCODER_DIR <30>
ENCODER_PULSE <30>
TP_CLK <33>
TP_DATA <33>
WOL_EN# <26,34>
USB_OC#2 <21,25>
VGATE <42>
100
101
102
103
104
105
106
107
108
EC_SI_SPI_SO <31>
EC_SO_SPI_SI <31>
@
CAP_INT#
R1025
2 4.7K_0402_5%
1
@
ESB_CK
R1033
ESB_DA
R1034
2 4.7K_0402_5%
For EMI
2
R74
1
SPI_CLK <31>
0_0402_5%
1
C607
10P_0402_50V8J
CAP_INT#
@
CAP_INT# <33>
2
FSTCHG
FSTCHG <37>
BATT_FULL_LED#
BATT_FULL_LED# <33>
CAPS_LED#
CAPS_LED# <31>
BATT_CHG_LOW_LED#
BATT_CHG_LOW_LED# <33>
PWR_ON_LED#
PWR_ON_LED# <33>
SYSON
SYSON
<34,40>
CPU_VCORE_ENABLE
CPU_VCORE_ENABLE <42>
ACIN_D
R541
2
1 10K_0402_5%
EC_RSMRST#
EC_RSMRST# <21>
EC_LID_OUT#
EC_LID_OUT# <21>
EC_ON
EC_ON <33>
SB_PWRGD
BKOFF#_R
WL_OFF#
CURS_LED#
SB_PWRGD <21,42>
WL_OFF# <27>
CURS_LED# <31>
R560
2 150K_0402_5%
1
110
112
114
115
116
117
118
2 4.7K_0402_5%
SPI_CS# <31>
UMA_ENBKL
EC_THERM#
SUSP#
PBTN_OUT#
USB_OC#0
124 C814 2
+3VL
UMA_ENBKL <12>
EC_THERM# <22>
SUSP# <34,39>
PBTN_OUT# <21>
USB_OC#0 <21,25>
ACIN_D
1 D33
CH751H-40PT_SOD323-2
1 4.7U_0805_10V4Z
ACIN
<22,33,35>
C326
1 100P_0402_50V8J
KB926QFD3_LQFP128_14X14
ECAGND
L80
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
XCLK1
XCLK0
CRY2
+3VL_EC
ADP_V <37>
DAC_BRIG <18>
EN_DFAN1 <5>
IREF
<37>
CHGVADJ <37>
97
98
99
109
SPI Flash ROM
GPIO
R545
20M_0402_5%
Power has removed

BATT_TEMPA <36>
R1024
BATT_OVP <37>
1
2 100K_0402_5%
1
SPI Device Interface
32.768KHZ 12.5PF Q13MC14610002

C815
1
2 15P_0402_50V8J
C812
2 100P_0402_50V8J ECAGND
SM Bus
77
78
79
80
C813
2 15P_0402_50V8J
SYSON
Y7
10K_0402_5% 2
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
CAP_RST#
FAN_SPEED1
VLDT_EN
E51_TXD
E51_RXD
ON/OFFBTN#
PWR_SUSP_LED#
NUM_LED#
<33> CAP_RST#
<5> FAN_SPEED1
<34> VLDT_EN
<27> E51_TXD
<27> E51_RXD
<33> ON/OFFBTN#
<33> PWR_SUSP_LED#
<31> NUM_LED#
Add for KB926D2 issue. Please refer to KB926D-AN1-100 for detail
10K_0402_5% 2
AD
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
EC_BEEP <29>
ACOFF <37>
BATT_TEMPA
BATT_OVP
ADP_I_R
ADP_V
2.2K_0402_5% 2
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
ACOFF
63
64
65
66
75
76
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
DA Output
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
INVT_PWM_R
EC_BEEP
21
23
26
27
PWM Output
MISC
0.1U_0402_16V4Z
+3VL
12
13
37
20
38
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
AGND
+3VL
CLK_PCI_EC
PLT_RST#
ECRST#
EC_SCI#
WL_LED#
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC &
69
C810
2 15P_0402_50V8J1
1
2
3
4
5
7
8
10
GND
GND
GND
GND
GND
GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
11
24
35
94
113
AVCC
VCC
VCC
VCC
VCC
VCC
VCC
U33
67
C816
0.1U_0402_16V4Z
Add R344 and R345 for EC pin damage issue

L81
1 0_0603_5%
R344
BKOFF#_R
2 33_0402_5%
BKOFF# <18>
R345
INVT_PWM_R
+3VL_EC
1
4
1
C805
0.1U_0402_16V4Z
1
C806
0.1U_0402_16V4Z
1
C807
1000P_0402_50V7K
2 33_0402_5%
C809
1000P_0402_50V7K
Compal Secret Data

2009-02-12
2009-02-12
Deciphered Date
Title
Custom
Date:
INVT_PWM <18>
1
C808
0.1U_0402_16V4Z
Issued Date
ENE KB926 D3
Rev
1.0
LA-5831P
Sheet
E
32
of
44
Power Button/ PWR/B
CS/B Connector
Touch Pad Connector
@
JPOWER
ON/OFFBTN#
1
3
R512
100K_0402_5%
51_ON#
ESB_DA_L
ESB_CK_L
R1015
100_0402_5%
1
DC-IN LED
+3VALW
U34
APX9132ATI-TRL_SOT23-3
<22,32,35>
D49
PWR_SUSP_LED# <32>
< Ultra Bright Yellow Green >
2
1
120_0402_5%
2
BATT_CHG_LOW_LED# <32>
H2
Vf=1.9V(typ),2.4V(max) for amber

Vf=2.0V(typ),2.4V(max) for green
If=30mA(max)
HT-210UD/UYG_AMB/GRN
H12
< Ultra Bright Amber >

Vf=1.9V(typ),2.4V(max) for amber
Vf=2.0V(typ),2.4V(max) for green
If=30mA(max)
H13
H_3P0
@
H16
H6
H_3P0
@
H14
H_3P0
@
H7
H_3P0
@
H15
H_3P0
@
H37
H_3P0N
@
H8
H_3P0
@
H9
H_3P0
@
H10
H_3P0
@
H_3P0
@
H11
H_3P0
@
H_5P0
@
H38
H_5P0X3P0N
@
H_11P0X4P0N
@
2 0.22U_0603_16V4Z
C200 1
2 0.22U_0603_16V4Z
C201 1
2 0.22U_0603_16V4Z
C202 1
2 0.22U_0603_16V4Z
C203 1
2 0.22U_0603_16V4Z
H32
MINI CARD-1
H34
H_3P8
@
H27
MDC
SATA_LED# <22>
CPU
H_3P8
@
INS87990490H22
H_3P7
@
H19
H_3P8
@
H21
H_4P8X3P8
@
C199 1
WL_LED# <32>
+5VALW
D50
2
2
1
120_0402_5%
HT-110UD_1204_AMBER
+3VS
1
C647
10P_0402_50V8J
WLAN LED
1
R550
For EMI
H4
H_3P0
@
H3
H_3P0
@
H_3P8X4P8
@
H33
H_1P2
@
1
R549
+3VALW
< Ultra Bright Amber >
BATT_FULL_LED# <32>
C645
0.1U_0402_16V4Z
Screw Hole
HT-210UD/UYG_AMB/GRN
LID_SW# <32>
BATT CHARGE/FULL LED
2
120_0402_5%
PWR_ON_LED# <32>
1
R521
+3VALW
< Ultra Bright Yellow Green >
POWER ON/SUSPEND LED
VOUT
VDD
2N7002_SOT23-3
D38
C895
100P_0402_25V8K
2
G
2
2
1
120_0402_5%
ACES_85201-06051
Q20
1
R515
C894
100P_0402_25V8K
@
2
ACIN
+3VALW
ESB_CK_L
ESB_DA_L
1
6
5
Lid SW
D54
1
2
3
4
5
6
GND
GND
@
2
R1016
100_0402_5%
For EMI
Q19
GND
D87
@
PJDLC05_SOT23-3
R514
10K_0402_5%
SMT1-05-A_4P
2N7002_SOT23-3
2
G
2 FBMA-11-100505-301T_0402
2 FBMA-11-100505-301T_0402
1
2
JCS
1
2
3
4
5
6
7
8
EC_ON
2
BTM side
6
5
<32>
+3VL_CS
1 0_0603_5%
2 0_0402_5%
2 0_0402_5%
D60
PJDLC05_SOT23-3
@
SW6
@
@
@
ACES_85201-06051
<35>
ON/OFFBTN# <32>
SMT1-05-A_4P
@
@
1
1
L93
L94
ESB_CK
ESB_DA
ON/OFFBTN#
<32>
<32>
CAP_INT#
CAP_RST#
SW5
1
TOP side
<32>
<32>
1
2
3
4
5
6
GND
GND
For Debug
TP_CLK
TP_DATA
TP_SWL
TP_SWR
R1030 2
R1031 1
R1032 1
+3VL
C899 10P_0402_50V8J
ACES_85201-04051
<32>
<32>
<31>
<31>
1
2
3
4
5
6
7
8
C898 10P_0402_50V8J
C713
1U_0402_6.3V4Z
+5VS_TOUCH
TP_CLK
TP_DATA
TP_SWL
TP_SWR
+5VS
2 R111
1
0_0603_5%
C897 10P_0402_50V8J
1
2
GND 3
GND 4
5
6
20 mil width
@
JTOUCH
1
2
3
4
+3VL
H_1P2
@
HDD LED
3
PCB Fedical Mark PAD

4
4
FD1
@
FD3
FD4
2008/04/14
Issued Date
Compal Secret Data
2009/04/14
Deciphered Date
Title

LED/LID/PB/FB/SCREW HOLE
Custom
A
FD2
Q18B 2N7002DW-T/R7_SOT363-6
1
D46
2
2
1
120_0402_5%
1
R548
1
Q18A
2N7002DW-T/R7_SOT363-6
+3VS
2 R546
1
10K_0402_5%
+3VS
Date:
Rev
1.0
LA-5831P
Sheet
E
33
of
44
< +5VALW TO +5VS >
+1.8V
+5VALW
Q35
Inrush current = 0A
1
2
3
4
S
S
S
G
C833
8
7
6
5
C835
RUNON
2
SI4800BDY_SO8
1U_0402_6.3V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
Inrush current = 0A
1
2
3
C842
C848
1U_0402_6.3V4Z
C841
10U_0805_10V4Z
4.7U_0805_10V4Z
1.8VS_ENABLE
1
R809
< +3VALW TO +3VS >
10M_0402_5%
0.01U_0402_25V7K
+3VS
Q14
8
7
6
5
C840
4.7U_0805_10V4Z
SUSP
Q143A
2N7002DW-T/R7_SOT363-6
D
D
D
D
Inrush current = 0A
1
2
3
4
S
S
S
G
SI4800BDY_SO8
C839
1U_0402_6.3V4Z
< +1.2VALW TO +1.2V_HT >
C838
+1.2VALW
4.7U_0805_10V4Z
2
RUNON
R152
1 750K_0402_1%
8
7
6
5
+VSB
C847
4.7U_0805_10V4Z
R808
10M_0402_5%
+3VALW
+3VALW
+ C879
@
330U_D2E_2.5VM
4.7U_0805_10V4Z
For +1.2VALW OVP issue

Just mount for TPS51117
< +3VALW TO +3V_LAN >
1U_0402_6.3V4Z
C862
R367
@
1K_0402_5%
2N7002_SOT23-3
C846
R233
330K_0402_5%
+VSB
SUSP
2
G
1
1
Q17
0.01U_0402_25V7K
Inrush current = 0A
1
2
3
R556
@
10M_0402_5%
C834
For power noise issue
+1.2V_HT
Q11
IRF8113PBF_SO8
+3V_LAN
+3VALW
+VSB
C849
< close to PQ20, must EMI confirm >
R138
750K_0402_1%
D
D
D
D
Q4
IRF8113PBF_SO8
C864
+1.8VS
+5VS
8
7
6
5
< close to PQ20, must EMI confirm > < +1.8V TO +1.8VS >
C837
0.01U_0402_25V7K
2
1
Vgs=-4.5V, Id=3A
VLDT_EN#
Q12A
2N7002DW-T/R7_SOT363-6
Rds<97m ohm
2
< Inversion of SYSON, SUSP#, VLDT_EN, EC_ON >

R17
R596
<41>
C680
SYSON#
SYSON#
1U_0402_6.3V4Z
Q142B
2N7002DW-7-F_SOT363-6
5
<32,40> SYSON
2
SUSP
SUSP
VLDT_EN#
<41>
Q142A
2N7002DW-7-F_SOT363-6
2
SUSP#
<32>
4.7U_0805_10V4Z
Inrush current = 0A
C679
1
@
R597
100K_0402_5%
100K_0402_5%
2
0.01U_0402_25V7K
+5VL
1
1
R595
+5VL
100K_0402_5%
C182
PJ29
JUMP_43X79
VLDT_EN 2
G
VLDT_EN
<32,39>
Q53
2N7002_SOT23-3
+5VL
2
2
Q38
AO3413_SOT23
C880
0.1U_0402_16V7K
<26,32> WOL_EN#
1
R19
2 47K_0402_5%
1
100K_0402_5%
WOL_EN#
+0.9V
+1.5VS
+1.1VS
+3VS
SUSP
2N7002_SOT23-3
2N7002DW-T/R7_SOT363-6
SYSON#
Q144B
2N7002DW-7-F_SOT363-6
D
Q49
2
G
S
SUSP
D
Q50
2
G
2N7002_SOT23-3
SUSP
2N7002_SOT23-3
Q143B
5
SYSON#
2N7002DW-T/R7_SOT363-6
Q52
2
G
2N7002_SOT23-3
VLDT_EN#
Q12B
Q48
2
G
SUSP
470_0805_5%
R294
470_0805_5%
R293
470_0805_5%
R292
470_0805_5%
3 1
R288
470_0805_5%
3 1
R284
470_0805_5%
R280
470_0805_5%
R279
470_0805_5%
2N7002DW-7-F_SOT363-6
+1.8V
R239
Q144A
SUSP
+1.2V_HT
2
+1.8VS
+5VS
< Discharge circuit >
Compal Secret Data
2009-02-12
Issued Date
Title
Custom
A
2009-02-12
Deciphered Date
Date:
DC / DC Circuits
Rev
1.0
LA-5831P
Sheet
E
34
of
44
VIN
PL1
SMB3025500YA_2P
1
2
PF1
DC_IN_S2
PR1
1M_0402_1%
1
2
VIN
VS
PJP1
PR3
84.5K_0402_1%
PU1A
3
+
-
LM358DT_SO8
VIN
PC6
0.1U_0603_25V7K
2
1
10K_0402_1%
PD2
GLZ4.3B_LL34-2
PR7
10K_0402_1%
2 1
PR2
PR5
2
0_0402_5%
<22,32,33> ACIN
@ SINGA_2DW -0005-B03
PR4
22K_0402_1%
1
2
PC4
100P_0402_50V8J
1
PC3
1000P_0402_50V7K
PC2
100P_0402_50V8J
PC1
1000P_0402_50V7K
10A_125V_451010MRL
DC_IN_S1
PR6
20K_0402_1%
DC301001M80
PC5
1000P_0402_50V7K
RTCVREF
PR8
10K_0402_1%
PD4
RLS4148_LL34-2
PR9
68_1206_5%
PQ1
TP0610K-T1-E3_SOT23-3
N1
Vin Detector
High 18.384 17.901 17.430

Low 17.728 17.257 16.976
VS
RTC Battery
2
<33>
2
PR13
22K_0402_1%
51_ON#
OUT
IN
N2
GND
SP093MX0000
PC10
PC9
10U_0805_10V4Z
@ MAXEL_ML1220T10
G920AT24U_SOT89-3
+RTCBATT
PU2
3.3V
1
+CHGRTC
+RTCBATT
1
PR14
200_0603_5%
PR16
560_0603_5%
1
2
PBJ1
RTCVREF
PR15
560_0603_5%
1
2
PC8
0.1U_0603_25V7K
PC7
0.22U_1206_25V7K
PR12
100K_0402_1%
PR10
68_1206_5%
PR11
200_0603_5%
CHGRTCP 1
2
BATT+
PD3
RLS4148_LL34-2
1U_0805_25V4Z
PJ1
+3VALW P
PJ2
+3VALW
+1.8VP
@ JUMP_43X118
+5VALW
@ JUMP_43X118
(5A,200mils ,Via NO.= 10)

OCP(min)=7.9A
+VSBP
+3VLP
+VSB
+5VL
(100mA,40mils ,Via NO.= 2)

PJ7
+1.2VALW P
+3VL
(5A,200mils ,Via NO.=10)

OCP(min)=7.78A
PJ9
PJ10
+NB_CORE
+VDDNBP
@ JUMP_43X39
+0.9VP
PJ13
+0.9V
+1.5VSP
+1.5VS
@ JUMP_43X79
@ JUMP_43X79
(2.0A,80mils ,Via NO.=4)

Compal Secret Data
Issued Date
2008/04/14
Deciphered Date
2009/04/14
A
+VDDNB
(3A,120mils ,Via NO.=6)
PJ12
(0.5A,20mils ,Via NO.=1)
@ JUMP_43X118
(7.0A,280mils ,Via NO.=14)

OCP(min)=9.32A
+2.5VS
+1.2VALW
@ JUMP_43X118
@ JUMP_43X118
PJ11

+NB_COREP
@ JUMP_43X39
@ JUMP_43X39

+2.5VSP
VL
PJ6
@ JUMP_43X39
+1.8V

OCP(min)=8.87A
PJ8
PJ3
@ JUMP_43X118
PJ5
+5VALW P
@ JUMP_43X118
PJ4
2 2
1 1

OCP(min)=7.7A
2
Title

DCIN/DECTOR
Size
Document Number
Rev
1.0
LA-5831P
Date:
W ednesday, August 12, 2009

D
Sheet
35
of
44
PH1 under CPU botten side :

CPU thermal protection at 92 degree C
Recovery at 56 degree C
VMB
PF2
15A_65V_451015MRL
1
2
PJP2
VL
VL
PL2
SMB3025500YA_2P
1
2
ENTRIP1
<38>
VL
PC13
0.1U_0603_25V7K
PR20
47K_0402_1%
1
2
PQ2
SSM3K7002FU_SC70-3
ENTRIP2
<7,38>
PD5
RLS4148_LL34-2
LM393DG_SO8
VL
PQ3
SSM3K7002FU_SC70-3
PR27
100K_0402_1%
1
1
2
PR29
100K_0402_1%
2
2
G
PR28
1K_0402_1%
PC15
1000P_0402_50V7K
1
2
PR25
13.7K_0402_1%
+3VLP
PC14
0.22U_0805_16V7K
PR26
6.49K_0402_1%
2
1
2
G
PU3A
TM_REF1
PR24
100_0402_1%
1
PR23
100_0402_1%
PR22
13.7K_0402_1%
1
2
PR21
1K_0402_1%
@ OCTEK_BTJ-09HA1G
PR19
47K_0402_1%
PH1
100K_0402_1%_NCP15WF104F03RC
PC12
0.01U_0402_25V7K
PC11
1000P_0402_50V7K
+3VLP
2
PR18
47K_0402_1%
2
PR17
1K_0402_1%
BATT+
1
EC_SMDA
EC_SMCA
GND
GND
GND
GND
BATT_S1
10
11
12
13
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
BATT_TEMPA <32>
EC_SMB_DA1 <32>
EC_SMB_CK1 <32>
PH2 near main Battery CONN :

BAT. thermal protection at 92 degree C
Recovery at 56 degree C
VL
VL
PQ4
TP0610K-T1-E3_SOT23-3
PR30
47K_0402_1%
O
-
4
PC18
0.22U_0805_16V7K
PU3B
LM393DG_SO8
PD6
RLS4148_LL34-2
PR34
16.9K_0402_1%
2
PR37
0_0402_5%
2
PQ5
SSM3K7002FU_SC70-3
2
G
PC19
@ .1U_0402_16V7K
1
POK
PR36
100K_0402_1%
<38,39>
5
TM_REF1
1
2
2
2
PR33
13.7K_0402_1%
1
2
PR35
22K_0402_1%
1
2
PC17
0.1U_0603_25V7K
VL
PR31
47K_0402_1%
1
2
100K_0402_1%_NCP15WF104F03RC
PC16
0.22U_1206_25V7K
2
1
PR32
100K_0402_1%
+VSBP
PH2
3
B+
Compal Secret Data
Issued Date
2008/04/14
Deciphered Date
2009/04/14
Title
Size
Date:

BATTERY CONN / OTP
Document Number
Rev
1.0
LA-5831P
D
Sheet
36
of
44
2
3
ACN
ACP
4
5
ACDRV
ACDET
HIDRV
26
PH
25
PR40
100K_0402_1%
2
1
2
1
PC24
4.7U_1206_25V6K
PC23
4.7U_1206_25V6K
2
1
5
6
7
8
D
D
D
D
8
7
6
5
FDS4435BZ_SO8
PQ9
1
2
3
4
/BATDRV
S
S
S
G
D
D
D
D
8
7
6
5
PQ10
AO4466_SO8
24
REGN
PC36
1U_0603_10V6K
PQ11
AO4466_SO8
PC34
.1U_0402_16V7K
1
2
1
BATT+
PR48
120K_0402_1%
PR45
0.02_1206_1%
4
PC31
RLS4148_LL34-2
0.1U_0603_25V7K
PC33
10U_1206_25V6M
ACSET
PL3
10UH_SIL1045RA-100PF_4.5A_30%
1
2
PD7
2
10U_1206_25V6M
PC32
S
S
S
G
@ FDS4435BZ_SO8
PR43
0_0603_5%
1
2
REGN
ACSET
1
2
27
BTST
PC22
4.7U_1206_25V6K
PC30
@0.1U_0603_25V7K
1
2
3
4
3
2
1
PC29
0.1U_0603_25V7K
PR47
100K_0402_1%
1
2
PC35
@ 0.01U_0402_25V7K
28
PVCC
VREF
CHGEN
PL16
HCB2012KF-121T50_0805
CHG_B+
1
2
PC27
0.22U_1206_25V7K
1
2
PU4
1
ACDET
PR46
54.9K_0402_1%
PR163
4.7_1206_5%
1
PC26
.1U_0402_16V7K
1
2
PC141
@0.1U_0402_25V6
2
1
PC20
0.01U_0402_25V7K
PQ6
5
6
7
8
2
1
2
2
PR44
340K_0402_1%
8
7
6
5
PR42
100K_0402_1%
1 1
2
PC28
2.2U_0805_25V6K
PR41
3.3_1210_5%
PR38
0.015_1206_1%
1
4
CHGEN#
PC25
0.01U_0603_50V7K
2 1
PR39
3.3_1210_5%
1
2
3
PR162
1K_0402_1%
8
7
6
5
B+
PQ8
AO4407A_SO8
PQ7
FDS4435BZ_SO8
D
S 1
D
S 2
D
S 3
D
G 4
PC148
PC21
1000P_0402_50V7K 0.022U_0402_25V7K
2
1
2
1
VIN
PGND
22
LEARN
21
PC38
0.1U_0603_25V7K
23
PC39
@0.1U_0603_25V7K
LODRV
2
7 ACOP
PC37
0.47U_0603_16V7K
3
2
1
1
PR49
340K_0402_1%
2
OVPSET
OVPSET
AGND
ACOFF
<32>
PR50
54.9K_0402_1%
VREF
CELLS
20
CELLS
VADJ
PC42
0.1U_0603_25V7K
VREF
29
TP
ACGOOD
13
PR55
2
1
49.9K_0402_1%
PQ14
SSM3K7002FU_SC70-3
3
15
IADAPT
PR56
100K_0402_1%
2
G
16
SRSET
BATDRV
14
IREF
PR63
100K_0402_1%
<32>
/BATDRV
BQ24751ARHDR_QFN28_5X5
PR58
340K_0402_1%
PR57
10_0603_5%
REGN
PC44
@0.01U_0402_25V7K
CHGEN#
PQ15
SSM3K7002FU_SC70-3
3
CHGVADJ
Pre Cell
PR61
499K_0402_1%
PU1B
5
1.5A
VIN
4V
PR159
309K_0402_1%
ADP_V
<32>
PR160
10K_0402_1%
1
2
2
2
PC147
.1U_0402_16V7K
4
@ PC47
0.01U_0402_25V7K
LM358DT_SO8
0
4
3A
1.484V
PR161
47K_0402_1%
A
0V
4.35V
Current
2.968V
CHGVADJEC DA pin
2
1
@ PR66
105K_0402_1%
@ PR65
10K_0402_1%
1
2
2
1
2
1
@ PR64
@ PR62
499K_0402_1% 340K_0402_1%
1
2
BATT_OVP
<32>
PC46
0.01U_0402_25V7K
VS
VMB
3.28V
<32>
VADJ
<32> CHGVADJ
PR60
210K_0402_1%
1
2
ADP_I
IREF
PR59
@ 0_0402_5%
75W,Iadapter=3.947A,PR38=0.015ohm,PR47=100K,PR48=120K,CP=3.63A
PC45
100P_0402_50V8J
2
G
<32> FSTCHG
1
PC43
.1U_0402_16V7K
2
1
ACOFF
3
PQ13
SSM3K7002FU_SC70-3
2
G
PR54
100K_0402_1%
12
PR52
100K_0402_1%
17
1
3
18
SRN
VDAC
BAT
VADJ
ACSET
ACGOOD#
D
11
PC41
0.1U_0603_25V7K
PR53
200K_0402_1%
19
SRP
RTCVREF
VREF
VREF
PC40
1U_0603_10V6K
VREF
PQ12
SI2301BDS-T1-E3_SOT23-3
PR51
100K_0402_1%
1
2
10
Compal Secret Data
2008/04/14
Issued Date
2009/04/14
Deciphered Date
Title
Size
Date:

CHARGER
Document Number
Rev
1.0
LA-5831P
Sheet
E
37
of
44
PC48
1U_0603_10V6K
2VREF_51125
B++
PR67
13K_0402_1%
1
2
PR68
30K_0402_1%
1
2
PR69
20K_0402_1%
1
2
PR70
19.6K_0402_1%
1
2
B++
LX_5V
19
LG_5V
5
6
7
8
B++
2VREF_51125
PC57
220U_6.3V_M
VL
+5VALWP
PC143
@ .1U_0402_16V7K
PR79
@ 0_0402_5%
3
2
1
1
2
1
2
4
TPS51125RGER_QFN24_4X4
PC59
PR76
680P_0603_50V7K 4.7_1206_5%
PL5
4.7U_LF919AS-4R7M-P3_5.2A_20%
1
2
PQ19
AO4712_SO8
VCLK
18
VIN
VREG5
17
13
PR77
499K_0402_1%
1
2
16
EN0
DRVL1
GND
DRVL2
PC52
10U_1206_25V6M
UG_5V
20
<7,36>
PQ21
SSM3K7002FU_SC70-3
2
G
VL
1
2
G
21
LL1
PQ20
SSM3K7002FU_SC70-3
DRVH1
LL2
<36,39>
PC60
4.7U_0805_10V6K
ENTRIP2
DRVH2
2
<36>
PC51
2200P_0402_50V7K
ENTRIP1
PR74
PC55
2.2_0603_1% .1U_0402_16V7K
BST_5V 1
2 1
2
2
1
PC61
0.1U_0603_25V7K
ENTRIP1
2
VFB1
VREF
4
TONSEL
22
15
8
7
6
5
B+
1
2
3
23
VBST1
PR78
100K_0402_1%
12
PGOOD
VBST2
SKIPSEL
1
2
3
1
LG_3V
11
VREG3
POK
3
2
1
9
10
24
PQ18
AO4712_SO8
PC58
680P_0603_50V7K
2
1
PC56
220U_6.3V_M
PC142
@ .1U_0402_16V7K
2
1
PR75
4.7_1206_5%
2
1
PL4
4.7U_LF919AS-4R7M-P3_5.2A_20%
1
2
VO1
PQ16
AO4466_SO8
5
6
7
8
PR72
150K_0402_1%
2
ENTRIP1
VO2
14
PR73
2 1
2 BST_3V
2.2_0603_1%
UG_3V
PC54
.1U_0402_16V7K
LX_3V
1
Ipeak = 5A
Imax = 3.5A
F = 305kHz
Total Capacitor = 220 uF
ESR = 15m Ohm
7
4
+3VALWP
P PAD
25
ENTRIP2
PU5
PC53
4.7U_0805_10V6K
8
7
6
5
1
2
PQ17
AO4466_SO8
PR71
150K_0402_1%
1
2
VFB2
+3VLP
1
PC50
10U_1206_25V6M
@ JUMP_43X118
PC49
2200P_0402_50V7K
B+
ENTRIP2
PJ15
Ipeak = 5A
Imax = 3.5A
F = 245kHz
ESR = 15m Ohm
PQ22
SSM3K7002FU_SC70-3
2
G
PR81
100K_0402_1%
@ PC62
0.01U_0402_16V7K
2
1
PR82
49.9K_0402_1%
VS
PR80
100K_0402_1%
Compal Secret Data
Issued Date
2008/04/14
Deciphered Date
2009/04/14
Title
Size
Date:

3VALW/5VALW
Document Number
Rev
1.0
LA-5831P
D
Sheet
38
of
44
51124_B+
+NB_COREP
BST_NB_COREP
DR VH2
DR VH1
21
UG_NB_COREP
LL1
20
LX_NB_COREP
19
LG_NB_COREP
LL2
DR VL2
DR VL1
PGND1
PQ26
AO4712_SO8
2
TPS51124RGER_QFN24_4x4
3
2
1
PR92
16.5K_0402_1%
2
PR94
0_0402_5%
2
1
+5VALW
SUSP# <32,34>
PC79
4.7U_0805_10V6K
PC80
.1U_0402_16V7K
+NB_COREP
1
+
2
1
2
Ipeak =7A
Imax = 4.9A
F = 240kHz
ESR = 7.5m Ohm
PC78
1U_0603_10V6K
PC77
@ .1U_0402_16V7K
PR96
22K_0402_5%
1
2
PR95
3.3_0402_5%
1
<36,38> POK
+1.1V
PL7
1.8UH_SIL104R-1R8PF_9.5A_30%
1
2
18
TRIP1
PR93
13.7K_0402_1%
1
2
PC67
4.7U_1206_25V6K
2
1
17
V5FILT
V5IN
16
15
TRIP2
PGND2
13
14
PQ25
AO4712_SO8
4
PC66
4.7U_1206_25V6K
2
1
5
6
7
8
1
VO1
VFB1
3
GND
22
PC74
12
VBST1
PC70
.1U_0402_16V7K
4.7U_0805_6.3V6K
1
2
LG_1.2V
VBST2
PR89
2.2_0603_1%
2
1
PR91
4.7_1206_5%
10
11
23
PC76
680P_0603_50V7K
UG_1.2V
LX_1.2V
24
EN1
TONSEL
BST_1.2V
PGOOD1
5
6
7
8
8
7
6
5
EN2
1
2
3
PR90
4.7_1206_5%
2
1
PGOOD2
Ipeak =5A
Imax = 3.5A
F = 300kHz
ESR = 15m Ohm
PC75
680P_0603_50V7K
2
1
PC72
4.7U_0805_6.3V6K
PC71
220U_6.3V_M
PC144
@ .1U_0402_16V7K
2
1
+1.2VALWP
PL6
1.8UH_SIL104R-1R8PF_9.5A_30%
1
2
PQ24
AO4466_SO8
B+
3
2
1
1
2
3
PC69
PR88
.1U_0402_16V7K 2.2_0603_1%
2
1 2
1
P PAD
1
4
VO2
25
VFB2
8
7
6
5
PU6
PQ23
AO4466_SO8
+1.2VALWP
PR87
0_0402_5%
2200P_0402_50V7K
PC65
2
1
PC64
4.7U_1206_25V6K
2
1
PC63
4.7U_1206_25V6K
2
1
51124_B+
PC137
0.1U_0402_25V6
2
1
PL14
HCB2012KF-121T50_0805
1
2
PC145
@ .1U_0402_16V7K
2
1
PC139
@0.1U_0402_25V6
2
1
PR86
33K_0402_1%
PC138
@0.1U_0402_25V6
2
1
PR85
75K_0402_1%
2200P_0402_50V7K
PC68
PR84
75K_0402_1%
PC73
220U_6.3V_M
PR83
44.2K_0402_1%
+1.2VALWP
Compal Secret Data
2008/04/14
Issued Date
Title
Size
5
2009/04/14
Deciphered Date
Date:

NB_COREP/1.2VALWP
Document Number
Rev
1.0
LA-5831P
Sheet
1
39
of
44
PQ27
AO4466_SO8
PR97
255K_0402_1%
1
2
TPS51117RGYR_QFN14_3.5x3.5
DL_1.8VP
PC146
@ .1U_0402_16V7K
PQ28
AO4712_SO8
2
+1.8VP
PC89
4.7U_0805_10V6K
DRVL
TP
PGND
GND
PGOOD
PC88
@ 47P_0402_50V8J
1
2
6
PC86
4.7U_0603_10V6K
+5VALW
PC85
220U_D2_4VM
2
PR102
15.4K_0402_1%
V5DRV
10
LX_1.8VP
1
PR100
4.7_1206_5%
14
12
11
VFB
LL
TRIP
V5FILT
0.1U_0603_25V7K
VOUT
DH_1.8VP
13
DRVH
PC87
680P_0603_50V7K
15
TON
5
6
7
8
PR101
100_0603_1%
1
2
PL8
1.8UH_SIL104R-1R8PF_9.5A_30%
1
2
PC84
BST_1.8VP
3
2
1
+5VALW
PU7
EN_PSV
PC83
@.1U_0402_16V7K
B+
3
2
1
PR99
2.2_0603_1%
1
2
VBST
SYSON
PL15
HCB2012KF-121T50_0805
1
2
PR98
0_0402_5%
1
2
1
<32,34>
5
6
7
8
PC81
4.7U_1206_25V6K
51117_B+
PC140
@0.1U_0402_25V6
2
1
PC82
4.7U_1206_25V6K
Ipeak = 8A
Imax = 5.6A
F = 312kHz
ESR = 15m Ohm
PR103
28.7K_0402_1%
1
2
PR104
20.5K_0402_1%
PU8
APL5508-25DC-TRL_SOT89-3
PJ18
1
@ JUMP_43X39
IN
OUT
1
2
PC90
1U_0603_10V6K
+2.5VSP
GND
1
+3VS
PC91
4.7U_0805_6.3V6K
Compal Secret Data
2008/04/14
Issued Date
Title
Size
5
2009/04/14
Deciphered Date
Date:

1.8VP/2.5VS
Document Number
Rev
1.0
LA-5831P
Sheet
1
40
of
44
+3VS
D
PJ19
@ JUMP_43X79
VIN
VCNTL
6
5
GND
NC
VREF
NC
VOUT
NC
TP
+5VALW
PU9
1
PC93
1U_0603_6.3V6M
PC92
4.7U_0805_6.3V6K
PR105
1.15K_0402_1%
APL5331KAC-TRL_SO8
+1.5VSP
PC94
PQ29
.1U_0402_16V7K
SSM3K7002FU_SC70-3
1
PC95
10U_0805_6.3V6M
PR107
0_0402_5%
PC96
@ .1U_0402_16V7K
PR106
D 1K_0402_1%
2
G
1
1
SUSP
SUSP
<34>
PJ20
@ JUMP_43X79
+1.8V
VIN
VCNTL
GND
NC
VREF
NC
VOUT
NC
6
5
+3VALW
7
2
PR108
1K_0402_1%
PC97
4.7U_0805_6.3V6K
PU10
1
TP
PC98
1U_0603_6.3V6M
8
9
+0.9VP
PC99
.1U_0402_16V7K
S PQ30
SSM3K7002FU_SC70-3
PC101
@ .1U_0402_16V7K
PR109
1K_0402_1%
PC100
10U_0805_6.3V6M
2
G
SYSON#
<34>
APL5331KAC-TRL_SO8
PR110
0_0402_5%
1
2
Compal Secret Data
2008/04/14
Issued Date
Title
Size
5
2009/04/14
Deciphered Date
Date:

0.9VP/1.5VSP
Document Number
Rev
1.0
LA-5831P
Sheet
1
41
of
44
PR112
2_0603_5%
1
2
<7>
1
2
PC132
0.1U_0402_25V6
2
1
PC114
10U_1206_25V6M
2
1
3
2
1
27
PHASE1
26
UGATE1
25
BOOT1
PC118
1U_0603_16V6K
+CPU_CORE_0
2
PR128
3.65K_0402_1%
PC117
2
1
PC116
680P_0603_50V7K
PQ35
@ TPCA8028-H_SOP-ADVANCE8-5
0.1U_0603_16V7K
2
LGATE0
PR136
47K_0402_1%
CPU_B+
49
PQ36
SI7686DP-T1-E3_SO8
UGATE1
PHASE1
PL12
0.36UH_PCMC104T-R36MN1R17_30A_20%
3
2
1
PR139
2.2_0603_1%
BOOT1 1
2 1
PQ37
TPCA8028-H_SOP-ADVANCE8-5
1 2
PR141
3.65K_0402_1%
PC122
680P_0603_50V7K
PQ38
@ TPCA8028-H_SOP-ADVANCE8-5
PC123
2
1
PR146 1
3
2
1
3
2
1
PR145
0_0402_5%
1 VSEN1
+CPU_CORE_1
1
5
PC121
0.22U_0603_10V7K
PR144
4.7_1206_5%
ISN0
LGATE1
28
1 2
3
2
1
PQ34
TPCA8028-H_SOP-ADVANCE8-5
29
+5VS
30
1RTN1
PR140
0_0402_5%
@ 10_0402_5%
1 PR143 2
LGATE0
31
2
PR142
@ 10_0402_5%
1
2
PR130
4.7_1206_5%
TP
ISN1
24
ISN1
ISP1
23
ISP1
VW1
COMP1
22
21
FB1
20
19
18
13
BOOT1
ISP0
ISN0
PR135
0_0402_5%
2
1 VSEN0
0_0402_5%
2 PR138 1 RTN0
+CPU_CORE_1
UGATE1
VDIFF1
PHASE1
COMP0
VSEN1
FB0
PGND1
PC115
0.22U_0603_10V7K
ISP0
LGATE1
VDIFF0
PL11
0.36UH_PCMC104T-R36MN1R17_30A_20%
PC119
10U_1206_25V6M
2
1
OCSET
32
PR127
2.2_0603_1%
BOOT0 1
2 1
3
2
1
PVCC
ISL6265HRTZ-T_QFN48_6X6
VW0
PC113
10U_1206_25V6M
2
1
PQ33
SI7686DP-T1-E3_SO8
UGATE0
RBIAS
PR137
2
1
@ 10_0402_5%
PJ23
LGATE0
ISP0
12
ENABLE
RTN1
11
+CPU_CORE_1
1 2
3
2
1
PGND0
<7>
SVC
37
UGATE_NB
39
PHASE0
10
38
UGATE0
33
PHASE_NB
PGND_NB
LGATE_NB
40
41
42
RTN_NB
OCSET_NB
44
43
VSEN_NB
34
PHASE0
+CPU_CORE_0
45
UGATE0
SVD
FSET_NB
PWROK
17
FB_NB
BOOT0
PR132
0_0402_5%
PR134
4.02K_0402_1%
2
1
35
RTN0
PR133
113K_0402_1%
2
1
36
BOOT0
VSEN0
<32> CPU_VCORE_ENABLE
BOOT_NB
PGOOD
16
1
PR131
0_0402_5%2
OFS/VFIXEN
2
3
COMP_NB
46
47
VCC
VIN
48
1
2
ISL6265_PWROK
CPU_SVD
CPU_SVC
15
<7>
<7>
2
PR129 100K_0402_5%
2
PR158 100K_0402_5%
PHASE0
BOOT_NB
ISN0
<21,32> SB_PWRGD
CPU_VDDNB_RUN_FB_L
PR125
@ 10_0402_5%
14
1
@
1
PJ22
2
+CPU_CORE_0
UGATE_NB
2
VGATE
@ JUMP_43X118
1
PR122
0_0402_5%
PU11
@ JUMP_43X118
CPU_B+
1
2
<32>
<7,20> H_PWRGD
LGATE_NB
PR121
@ 105K_0402_1%
PR126
@ 105K_0402_1%
PJ21
PC110
220U_D2_4VM
PHASE_NB
PR124
@ 10K_0402_1%
PC111
680P_0603_50V7K
@ JUMP_43X118
PR123
105K_0402_1%
AP1
+
PHASE_NB
PC112
0.1U_0603_25V7K
1
PR120
0_0402_5%
CPU_VDDNB_RUN_FB_H
PR119
11.3K_0402_1%
2
1
PQ32
AO4712_SO8
2
PR117
2_0603_5%
+3VS
+5VS
PR114
4.7_1206_5%
PC109
0.22U_0603_10V7K
4
LGATE_NB
+VDDNBP
PR113
2.2_0603_1%
BOOT_NB 1
2 1
PR118
0_0402_5%
2
1
PL10
4.7U_LF919AS-4R7M-P3_5.2A_20%
1
2
3
2
1
PHASE_NB
PR115
22K_0402_1%
2
1
PR116
@ 10_0402_5%
1
2 +VDDNBP
CPU_B+
B+
PC107
1000P_0402_50V7K
2
1
PC108
0.1U_0603_16V7K
PQ31
AO4466_SO8
+
2
PL9
HCB4532KF-800T90_1812
1
2
PC134
@0.1U_0402_25V6
2
1
UGATE_NB
+
2
PC136
0.1U_0402_25V6
2
1
PC105
1000P_0402_50V7K
5
6
7
8
+5VS
5
6
7
8
PC104
@ 220U_25V_M
PR111
44.2K_0402_1%
PL13
HCB2012KF-121T50_0805
1
2
PC103
220U_25V_M
PC106
10U_1206_25V6M
2
1
CPU_B+
PC102
33P_0402_50V8J
2
1
PC133
0.1U_0402_25V6
PC135
@0.1U_0402_25V6
2
1
PC120
10U_1206_25V6M
2
1
0.1U_0603_16V7K
@ 10_0402_5%
VW0
DIFF_1
VW1
COMP0
PC125
180P_0402_50V8J
PR149
1K_0402_5%
2
1
PR150
2
PC130
2
1
PC126
1000P_0402_50V7K
COMP1
PC128
180P_0402_50V8J
PR151
6.81K_0402_1%
2
1
PR152
1K_0402_5%
2
1
PR153
2
PC129
1000P_0402_50V7K
4
PR154
6.81K_0402_1%
2
1
PC131
2
1
1
PR155
@ 36.5K_0402_1%
PR156
@ 36.5K_0402_1%
Compal Secret Data
2008/04/14
2009/04/14
Deciphered Date
Title
Issued Date
Custom
A
PR157
47K_0402_1%
54.9K_0402_1% 1200P_0402_50V7K
54.9K_0402_1% 1200P_0402_50V7K
PR148
PC127
255_0402_1% 4700P_0402_25V7K
FB_1
2
1 2
1
ISP1
LGATE1
PR147
PC124
255_0402_1% 4700P_0402_25V7K
FB_0
2
1 2
1
ISN1
DIFF_0
Date:
+CPU_CORE
Rev
1.0
LA-5831P
Sheet
E
42
of
44
Version Change List ( P. I. R. List ) for Circuit

Item Page#
1
35-43
39-40
38
36
37
PVT
Pre-MP
Pre-MP
Pre-MP
Pre-MP
Title
Change
Change
Change
Change
PL6,PL7,PL8
PC56
PH1,PH2
PR38,PR45
Date
Request
Owner
2009/07/20
2009/07/30
2009/07/30
2009/08/4
2009/08/4
Release
POWER
POWER
POWER
POWER
Issue Description
Rev.
Solution Description
Change
change
change
change
PL6,PL7,PL8 footprint
to common circuit.
to common circuit.
to common circuit.
Compal Secret Data
2009-02-12
Issued Date
Title
Custom
A
2009-02-12
Deciphered Date
Date:
List History
Rev
1.0
LA-5831P
Sheet
E
43
of
44
HW4 Product Improvement Record (P.I.R.)

D
NBWAE LA-5831P SCHEMATIC CHANGE LIST

REVISION CHANGE: 0.1 TO 1.0
GERBER-OUT DATE: 2009/08/07
NO
DATE
PAGE
MODIFICATION LIST
PURPOSE
-------------------------------------------------------------------------------------------------------------1
7/21
25
Change JUSBB footprint back to E-T_6905-E12N-00R_12P
USB/B pin define reverse
2
7/27
25
Add D11
For ESD
3
7/27
9
Add C120~C123
For EMI
4
7/27
32
Add R344 and R345
For EC pin damage issue
5
7/30
26
Add R97, R98 and R105
Reserve bead for EMI
6
8/6
18
Add C707, C708 and C709
For EMI
7
8/6
30
Add LA11 and LA12
For EMI
8
8/6
32
Add R74 and C607
For EMI
9
8/6
31
Delete R518 and C606
For EMI
10
8/6
7
Add C124
For EMI
--------------------------------------------------------------------------------------------------------------
2009-02-12
Issued Date
2009-02-12
Deciphered Date
Title
Size
5
Compal Secret Data
Date:
PIR
Document Number
Rev
1.0
Sheet
1
44
of
44

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A

NBWAE LA-5831P Schematics Document

Compal Secret Data

Compal Electronics, Inc.

Wednesday, August 12, 2009

File Name : LA-5831P

AMD S1G2 CPU

Model Name : NBWAE

1.8V DDRII 667/800MHZ

Hyper Transport Link 2.6GHz

RTL8103E LAN 10/100M

PCIe Mini Card WLAN

USB port 0,1

3IN1 Card Reader

MDC 1.5 Conn

DC/DC Interface CKT.

Power Circuit DC/DC

Compal Secret Data

Compal Electronics, Inc.

Int. MIC Conn HP Conn

Wednesday, August 12, 2009

DESIGN CURRENT 100mA

DESIGN CURRENT 100mA

Ipeak=5A, Imax=3.5A, Iocp min=7.9

Ipeak=5A, Imax=3.5A, Iocp min=7.7

DESIGN CURRENT 1.0A

DESIGN CURRENT 330mA

DESIGN CURRENT 500mA

Ipeak=5A, Imax=3.5A, Iocp min=7.78

Ipeak=18A, Imax=12.6A, Iocp min=30

Ipeak=18A, Imax=12.6A, Iocp min=30

Ipeak=8A, Imax=5.6A, Iocp min=8.87

Compal Secret Data

Compal Electronics, Inc.

Wednesday, August 12, 2009

@ : just reserve , no build

S5 S4/ Battery only

S5 S4/AC & Battery

CAMERA & MIC

SMBUS Control Table

SB700 SM Bus0 Address

SB700 SM Bus1 Address

KB926 SM Bus2 Address

KB926 SM Bus1 Address

KB926 ESB Address

Compal Secret Data

Compal Electronics, Inc.

Wednesday, August 12, 2009

Near CPU Socket

< From NB >

< VLDT_A & VLDT_B : HyperTransport I/O ring power >

< FAN Control Circuit : Vout = 1.6 x Vset >

< From EC ><32> EN_DFAN1

Compal Electronics, Inc.

Compal Secret Data

Wednesday, August 12, 2009

< Processor DDR2 Memory Interface >

< DDR2 VREF is 0.5 ratio >

< PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH >

< From/To SO_DIMMB >

Place them close to CPU within 1"

< To SO_DIMMA > <10> DDR_A_ODT1

< To SO_DIMMA > <10> DDR_CS1_DIMMA#