0 0x00000000 sc=206

0 0x0000c000 477115ca8378909fc2ca2c9abf9e38550f524355 rc=6

I?
I7e
BORG sata0@0x0000c000 [_ftext=0x80140000 etext=0x80145524]
[_fdata=0x80145524 edata=0x80145b38] [_fbss=0x80145b38 end=0x80145d50] sp=0x8015
7cd8 gp=0x8014db30
pll1=0x01000033 premux=0x00000101 mux=0x17000000 [mips@349MHz]
!xxenv xload3 rc=6
#chpll 0x01000033/0x00000000 -> 0x01000026/0x00000201... ok
loaded key x.ddr.0.cfg0.RDATAENOFF=1
loaded key x.ddr.0.cfg0.SHUFFDISABLE=1
loaded key x.ddr.0.cfg0.CFG=0
loaded key x.ddr.0.cfg0.DD=0
loaded key x.ddr.0.cfg0.CL=0
loaded key x.ddr.0.cfg0.CL_up=1
loaded key x.ddr.0.cfg0.CCL=5
loaded key x.ddr.0.cfg0.AHRASSEL=1
loaded key x.ddr.0.cfg0.AL=2
loaded key x.ddr.0.cfg0.WMINUSONE=0
loaded key x.ddr.0.cfg0.ALreconf=5
loaded key x.ddr.0.cfg0.RCD=0
loaded key x.ddr.0.cfg0.REFSH=29
loaded key x.ddr.0.cfg1.WR=7
loaded key x.ddr.0.cfg1.RP=7
loaded key x.ddr.0.cfg1.RTP=1
loaded key x.ddr.0.cfg1.RRD=2
loaded key x.ddr.0.cfg1.RTW=1
loaded key x.ddr.0.cfg1.WTR=2
loaded key x.ddr.0.cfg1.RC=30
loaded key x.ddr.0.cfg1.RFC=76
loaded key x.ddr.0.cfg2.RS=1
loaded key x.ddr.0.cfg2.WOD=5
loaded key x.ddr.0.cfg2.ROD_OFF=2
loaded key x.ddr.0.cfg2.ROD_ON=2
loaded key x.ddr.0.cfg2.ROD_RV=2
loaded key x.ddr.0.cfg3.SREFTIM=0
loaded key x.ddr.0.cfg3.MD2RTTWR=1
loaded key x.ddr.0.cfg3.MD2SRT=0
loaded key x.ddr.0.cfg3.MD2CWL=4
loaded key x.ddr.0.cfg3.MD2PASR=0
loaded key x.ddr.0.cfg3.RST2CKE=25000
loaded key x.ddr.0.phy_cfg0.SL=7
loaded key x.ddr.0.phy_cfg0.DDR3SEL=1
loaded key x.ddr.0.phy_cfg0.CLKDISABLE=0
loaded key x.ddr.0.phy_cfg0.FENA_RCV=1
loaded key x.ddr.0.phy_cfg0.ODISCLK=0
loaded key x.ddr.0.phy_cfg0.PHYUPDACK=0
loaded key x.ddr.0.phy_cfg0.CTRLUPDREQ=0
loaded key x.ddr.0.phy_cfg0.RDLVLEDGE=1
loaded key x.ddr.0.phy_cfg0.WRLVLCKPOL=0
loaded key x.ddr.0.phy_cfg0.DDR3BY16=1
loaded key x.ddr.0.phy_cfg0.GTTIME=4096
loaded key x.ddr.0.phy_cfg1.RDLVLRENSEL=4
loaded key x.ddr.0.phy_cfg1.DQSKEWRD=0
loaded key x.ddr.0.phy_cfg1.DQSKEWWR=0
loaded key x.ddr.0.phy_cfg1.DMWRSEL1=0
loaded key x.ddr.0.phy_cfg1.DMWRSEL0=0
loaded key x.ddr.0.phy_cfg1.COMP=1
loaded key x.ddr.0.phy_cfg1.RENSEL=3

loaded key x.ddr.0.phy_cfg1.GTSEL1=1

loaded key x.ddr.0.phy_cfg1.GTNEG1=3
loaded key x.ddr.0.phy_cfg1.GTSEL0=1
loaded key x.ddr.0.phy_cfg1.GTNEG0=3
loaded key x.ddr.1.phy_cfg1.DQSKEWRD=0
loaded key x.ddr.1.phy_cfg1.DMWRSEL1=0
loaded key x.ddr.1.phy_cfg1.DMWRSEL0=0
loaded key x.ddr.1.phy_cfg1.GTSEL1=1
loaded key x.ddr.1.phy_cfg1.GTNEG1=3
loaded key x.ddr.1.phy_cfg1.GTSEL0=1
loaded key x.ddr.1.phy_cfg1.GTNEG0=3
********* Rudimentary ddr-3 test, bank#0: ORG = 0x8b6ea7f5
0x8000e000 <- 0x80006000
0x8001e000 <- 0x8000e000
0x8003e000 <- 0x8001e000
0x8007e000 <- 0x8003e000
0x800fe000 <- 0x8007e000
0x801fe000 <- 0x800fe000
0x803fe000 <- 0x801fe000
0x807fe000 <- 0x803fe000
0x80ffe000 <- 0x807fe000
0x81ffe000 <- 0x80ffe000
0x83ffe000 <- 0x81ffe000
0x87ffe000 <- 0x83ffe000
0x8fffe000 <- 0x87ffe000
0x8fffe000 <- 0x8fffe000
0xafffe000 <- 0x8fffe000
********* Rudimentary ddr-3 test: ~0 bit failures!
********* Rudimentary ddr-3 test, bank#1: ORG = 0x7a2b11c8
0xc000e000 <- 0xc0006000
0xc001e000 <- 0xc000e000
0xc003e000 <- 0xc001e000
0xc007e000 <- 0xc003e000
0xc00fe000 <- 0xc007e000
0xc01fe000 <- 0xc00fe000
0xc03fe000 <- 0xc01fe000
0xc07fe000 <- 0xc03fe000
0xc0ffe000 <- 0xc07fe000
0xc1ffe000 <- 0xc0ffe000
0xc3ffe000 <- 0xc1ffe000
0xc7ffe000 <- 0xc3ffe000
0xcfffe000 <- 0xc7ffe000
0xcfffe000 <- 0xcfffe000
0xefffe000 <- 0xcfffe000
********* Rudimentary ddr-3 test: ~0 bit failures!
Boot from SATA...
device read in virtual offset 0x000c0000 for ZXENV succeeded!
device read in physical offset of xos3 succeeded!
device read in virtual offset 0x00040000 for ezboot xload succeeded!
!Cezroot xload3mrc=o
r!
+++ armor 0xa executing at 0xbf100000, will relocate and jump at 0x82000000 +++
pll0=0x01000024, sysclk_mux=0x16000201, cpuclk_div_ctrl=0x00604b00
Pre-ramp: Current CPU freq=13381000 HZ, and SysClk @ 351000000 HZ
[0] ../include/memorymap_v7.h,193: polling lrro until locked appears!
X

#xos3D36 (111 config 0x87560300 / subid 0x00 / feat 0x00000003 / bdl 0x00140400)
[serial#b84e028151c00a170d9e747427c7f8a8]
[oemid#3b39cffb34b3d6cb81cb2395cad8e4a14bb64bc2381f2968353d590e0d774fd9]
#step22
ruamm0 [0x98000000,0xbf2f0000[ (~657391616 bytes)
ruamm1 [0xc0000000,0xffd60000[ (~1070989312 bytes)
[0xbf0c0000,xos_public_ga=0xbf0c0000[ and [0xbf0e0000,0xbf100000[ are lost for a
lignment)
channel_index_ga=0x#ei
xos3 xload3 rc=6
[0xbec00000,ios_ga=0xbec00000[ and [0xbf000000,0xbf0afcbc[ are lost for alignmen
t)
step33
f_pll0=0x3b8b87c0
current_pll0=0x01000024
cpuclk_div_inclk_freq=999000000 HZ
pll_sysclk(from pll1)=0x01000026
freq_to_mux=0x3ec38140
cpuclk_div_bypass_freq=526500000 HZ
Gonna ramp "down", div.value=0x0060010e
Wrote the cpuclk_div_ctrl register...
Ramped DOWN. cpuclk_div=0x0060010e
reaching for bypass freq: cpuclk_div=0x00800200
Setting pll0=0x01000024
Slow ramped to cpuclk_div=0x00600100
Post-ramp: Current CPU freq=999100000 HZ, and SysClk @ 351000000 HZ
thimble 0x14 @(cpu=@999MHz/dsp=351MHz/sys=351MHz)
on 8756 rev ES1 (subid 0x00)
L2 cache settings tag 0x00000110 data 0x00000120
xos version = 0x36
xos serial = b84e028151c00a170d9e747427c7f8a8
Using zxenv ga=0xffd5c000 (va=0xa005c000)
Chip identified as SMP8756A03 (00) rev 1 dev (oemid: sigma)
Board ID.: 1162-E1 eMMC
Setting up H/W from XENV block at 0xa005c000.
Setting <SYSCLK avclk_mux> to 0x17400000.
Setting <SYSCLK hostclk_mux> to 0x00000131.
Setting <IRQ rise edge trigger lo> to 0xff28ca06.
Setting <IRQ fall edge trigger lo> to 0x0000c000.
Setting <IRQ rise edge trigger hi> to 0x8c10001f.
Setting <IRQ fall edge trigger hi> to 0x00000000.
Setting <IRQ GPIO map> to 0x000a0800.
Setting <PB default timing> to 0x03080202.
Setting <PB timing0> to 0x03080202.
Setting <PB Use timing0> to 0x000003f3.
Setting <PB timing1> to 0x04040000.
Setting <PB Use timing1> to 0x000003f4.
Setting <PB CS Config> to 0x04370007.
Setting <PB CS Ctrl> to 0x00000022.
Enabled Devices: 0x002303f8
Ethernet IR FIP I2CM I2CS SDIO SDIO1 USB SATA SCARD
Smartcard pin assignments:
OFF pin = 0
5V pin = 2
CMD pin = 1
PLL#1 postdivider = 0x0000060f
cd#0 disabled
cd#1 disabled
cd#2 want 96000000Hz: setting of 0x0000000043800000-2^28

cd#2 cannot measure

cd#3 want 60000000Hz: setting of 0x000000006c000000-2^28
cd#3 cannot measure
cd#4 disabled
cd#5 disabled
cd#6 want 96000000Hz: setting of 0x0000000043800000-2^28
cd#6 measured to 0kHz
cd#7 disabled
cd#8 disabled
cd#9 disabled
cd#10 disabled
cd#11 disabled
GPIO dir/data = 0x00000800/0x00000800
UART1 GPIO mode/dir/data = 0x00/0x00/0x00
UART2 GPIO mode/dir/data = 0x00/0x00/0x00
MAC0: 00:16:e8:3d:09:62
Default boot index: 1
**********************************************
*** Press 'p' to boot to the shell prompt! ***
**********************************************
Boot Index overridden, selected by UART keypress: (0)
IPU Stage0 booted Stage1 from devtype: 4, chipsel: 0, phyblocknum: 2, zxenv bloc
k#: 6
Explicit boot order specified:
0x81 : devtype=8, CS=1
Original kernel command line: [console=ttyS0 mem=384M]
Full kernel command line: [console=ttyS0 mem=384M]
Checking for DRM keys partition... Trying devtype=8 chipsel=1
emmc_init(cs=1): baseclk_hz determined to be 48000000 HZ
year0 month10 sncb6468 fwrev13 hwrev2 name4d433034473b id014e4d [wh14]
csd_regs[0] = 0xe78a4000
csd_regs[1] = 0xffffffff
csd_regs[2] = 0x320f5913
csd_regs[3] = 0x00d04f01
Attempt to switch to 8 bit mode ...successful.
MBR sig check failed.
Failed to init!
Failed to find valid DRM keys ROMFS in any device / chip select!
Checking for DRM key ROMFS... at offset 0x00140000 in virtual zone, size of 1310
72 bytes
Trying devtype=8 chipsel=1
Brute-forcing the clock settings to use PLL1_1 -> CD6@104MHz / 2 -> SDIO source
clock
emmc_init(cs=1): baseclk_hz determined to be 52000000 HZ
year0 month10 sncb6468 fwrev13 hwrev2 name4d433034473b id014e4d [wh14]
csd_regs[0] = 0xe78a4000
csd_regs[1] = 0xffffffff
csd_regs[2] = 0x320f5913
csd_regs[3] = 0x00d04f01
Attempt to switch to 8 bit mode ...successful.
MBR sig check failed.
Failed to init!
Failed to find valid DRM keys ROMFS in any device / chip select!
DRM key loading process failed.
Trying devtype=8 chipsel=1
Brute-forcing the clock settings to use PLL1_1 -> CD6@104MHz / 2 -> SDIO source
clock
emmc_init(cs=1): baseclk_hz determined to be 52000000 HZ
year0 month10 sncb6468 fwrev13 hwrev2 name4d433034473b id014e4d [wh14]
csd_regs[0] = 0xe78a4000

csd_regs[1] = 0xffffffff
csd_regs[2] = 0x320f5913
csd_regs[3] = 0x00d04f01
Attempt to switch to 8 bit mode ...successful.
MBR sig check failed.
Failed to init!
Boot failed (no bootable image found) ..