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5 4 3 2 1 D D DR1(Roberts) Schematics Document uFCPGA Mobile Penryn Intel Cantiga-GM
5
4
3
2
1
D
D
DR1(Roberts) Schematics Document
uFCPGA Mobile Penryn
Intel Cantiga-GM + ICH9M
C
C
2009-08-03
REV : -3
B
B
DY : Nopop Component
A
A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Cover Page
Cover Page
Cover Page
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
-3
-3
-3
Roberts
Roberts
Roberts
Date:
Date:
Date:
Monday, August 03, 2009
Monday, August 03, 2009
Monday, August 03, 2009
Sheet
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C

5 4 3 2 1 D C B A Roberts Block Diagram Intel Mobile CPU Penryn

B

A

Roberts Block Diagram

Intel Mobile CPU Penryn

Socket P

5,6,7

CPU DC/DC

ISL6266A

28,29

INPUTS

OUTPUTS

+PWR_SRC

+VCC_CORE

SYSTEM DC/DC

 

TPS51117

30

INPUTS

OUTPUTS

+PWR_SRC

+1.05V_VCCP

SYSTEM DC/DC

 

MAX17020

27

INPUTS

OUTPUTS

 

+5V_ALW2

+3.3V_RTC_LDO

+PWR_SRC

+5V_ALW

+3.3V_ALW

D

Clock Generator SLG8SP513VTR 4
Clock Generator
SLG8SP513VTR
4

Project code : 91.4AQ01.001

PCB P/N

: 48.4AQ01.031

Revision

: 08212-3

FSB 800/1066MHz Intel Cantiga-GML AGTL+ CPU I/F DDR Memory I/F External Graphics DMIx4 Intel ICH9-M
FSB
800/1066MHz
Intel
Cantiga-GML
AGTL+ CPU I/F
DDR Memory I/F
External Graphics
DMIx4
Intel
ICH9-M
USB 2.0/1.1 ports (12)
PCI Express ports (6)
High Definition Audio
SATA ports (4)
LPC I/F
ACPI 1.1
PCI/PCI BRIDGE
Thermal & Fan
Flash ROM
Touch
Int.
HDD
ODD
2MB
PAD
KB
EMC2102
36
36
25
42
44
44
SATA
DDRII Slot 0 DDRII 667/800 Channel A 667/800 14 DDRII Slot 1 DDR II 667/800
DDRII
Slot 0
DDRII 667/800 Channel A
667/800
14
DDRII
Slot 1
DDR II 667/800 Channel B
667/800
15
SYSTEM DC/DC RGB CRT CRT (on I/O board) TPS51116 31 Power SW 41 INPUTS OUTPUTS
SYSTEM DC/DC
RGB CRT
CRT
(on I/O board)
TPS51116
31
Power SW
41 INPUTS
OUTPUTS
G577BR91U
LVDS(Dual Channel)
+1.8V_SUS
LCD
35
+PWR_SRC
+0.9V_DDR_VTT
C
+V_DDR_MCH_REF
8,9,10,11,12,13
SYSTEM DC/DC
PCIE x 1 & USB 2.0 x 1
New Card
41
APL5912
32
INPUTS
OUTPUTS
C-LINK
10/100 NIC
RJ45
PCIE x 1
Marvell 88E8040
20
CONN
+1.8V_SUS
+1.5V_RUN
SYSTEM DC/DC
Left Side:
LDO
USB 2.0 x 2
34
41 USB x 2
PCIE
INPUTS
OUTPUTS
+5V_ALW
+5V_RUN
Mini-Card
PCIE x 1
+3.3V_ALW
+3.3V_RUN
802.11a/b/g
37
MAXIM CHARGER
CAMERA
MAX8731A
USB 2.0 x 1
26
USB 2.0
B
41
(Option)
INPUTS
OUTPUTS
+DC_IN
+PWR_SRC
USB 2.0 x 1
+PBATT
Bluetooth
41
PCB LAYER
LPC Bus
16,17,18,19
Right Side:
USB 2.0 x 1
USB x 1
43
L1: Top
L2: VCC
KBC
L3: Signal
SPI
WINBOND
L4: Signal
24
WPCE773L
L5: GND
L6: Bottom
A
<Core Design>
<Core Design>
<Core Design>
SATA
I/O Board
Connector
<Core Design> SATA I/O Board Connector Wistron Corporation Wistron Corporation Wistron Corporation

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CardReader SD/MMC Realtek USB2.0 MS/MS Pro/xD 37 RTS5159 21
CardReader
SD/MMC
Realtek
USB2.0
MS/MS Pro/xD
37 RTS5159
21
CAMERA Module Digital Mic Array Azalia CODEC MIC IN IDT 92HD71B7 22 Internal Analog MIC
CAMERA Module
Digital Mic Array
Azalia
CODEC
MIC IN
IDT
92HD71B7
22
Internal Analog MIC
HP1
OP AMP
MAX9789A
23
40
AZALIA
AZALIA

2CH SPEAKER

Title

Title

Title

Block Diagram

Block Diagram

Block Diagram

Size

Size

Size

Custom

Custom

Custom

Document Number

Document Number

Document Number

Roberts

Roberts

Roberts

Rev

Rev

Rev

-3

-3

-3

5

4

3

2

1

Date:

Date:

Date:

Thursday, August 27, 2009

Thursday, August 27, 2009

Thursday, August 27, 2009

Sheet

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ICH9M Functional Strap Definitions

ICH9 EDS 642879 Rev.1.5

 

Signal

Usage/When Sampled

 

Comment

 

HDA_SDOUT

XOR Chain Entrance/

Allows entrance to XOR Chain testing when TP3

PCIE Port Config1 bit1, pulled low. When TP3 not pulled low at rising edge

Rising Edge of PWROK.

of PWROK, sets bit1 of RPC.PC (Cofig Registers:

4

offset 224h). This signal has weak internal pull-down.

HDA_SYNC

PCIE config1 bit0, Rising Edge of PWROK.

This signal has a weak internal pull-down. Sets bit0 of PRC.PC (Config Registers: Offset

224h).

 

GNT2#/

PCIE config2 bit2, Rising Edge of PWROK.

This signal has a weak internal pull-up. Sets bit2 of PRC.PC2 (Config Registers: Offset

GPIO53

 

224h).

 

GPIO20

Reserved.

This signal should not be pulled high.

 

GNT1#/

 

ESI Strap (Server Only) ESI compatible mode is for server platforms only.

GPIO51

Rising Edge of PWROK.

This signal should not be pulled low for desktop and mobile.

GNT3#/

Top-Block Swap override. Rising Edge of PWROK.

Sampled low: Top-Block Swap mode (inverts A16 for all cycles targeting FWH BIOS space). Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down.

GPIO55

GNT0#:

Boot BIOS Destination

Controllable via Boot BIOS Destination bit

3

SPI_CS1#/

Selection 0:1. Rising Edge of PWROK.

(Config Registers: Offset 3410h:bit 11:10). GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC

GPIO58

 

SPI_MOSI

Integrated TPM Enable,

Sample low: the Integrated TPM will be disable.

Rising Edge of CLPWROK. Sample high: the MCH TPM enable strap is sampled low and the TPM Disable bit is clear, the Integrated TPM will be enable.

GPIO49

DMI Termination Voltage. Rising Edge of CLPWROK.

The signal is required to be low for desktop applications and required to be high for mobile applications.

SATALED#

PCI Express Lane Reversal. Rising Edge of PWROK.

Signal has weak internal pull-up. Sets bit 27 of MPC.LR (Device 28: Function 0:Offset D8).

SPKR

No Reboot. Rising Edge of PWROK.

If sampled high, the system is strapped to the "No Reboot" mode (ICH9 will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit.

TP3

XOR Chain Entrance. Rising Edge of PWROK.

This signal should not be pull low unless using XOR Chain testing.

GPIO33/

Flash Descriptor

Sampled low: the Flash Descriptor Security will be

HDA_DOCK

Security Override Strap. Rising Edge of PWROK.

overridden. If high, the security measures will be in effect. This should only be enabled in manufacturing environments using an external pull-up resister.

2

_EN#

 

PCIE Routing

 

USB Table

 
     

USB

Pair

Device

   

LANE2

MiniCard WLAN

 

0 USB1

   

1 USB2

LANE3

LAN

2 USB3

LANE5

New Card

3 RESERVED

 

4 MINI CARD

5 RESERVED

1

6 BLUETOOTH

7 NEW CARD

8 RESERVED

9 RESERVED

10 Card Reader

11 CAMERA

C

ICH9 Integrated pull-up and pull-down Resistors

ICH9 EDS 642879 Rev.1.5

SIGNAL

Resistor Type/Value

CL_CLK[1:0]

PULL-UP 20K

CL_DATA[1:0]

PULL-UP 20K

CL_RST0#

PULL-UP 20K

DPRSLPVR/GPIO16

PULL-DOWN 20K

ENERGY_DETECT

PULL-UP 20K

HDA_BIT_CLK

PULL-DOWN 20K

HDA_DOCK_EN#/GPIO33

PULL-UP 20K

HDA_RST#

PULL-DOWN 20K

HDA_SDIN[3:0]

PULL-DOWN 20K

HDA_SDOUT

PULL-DOWN 20K

HDA_SYNC

PULL-DOWN 20K

GLAN_DOCK#

The pull-up or pull-down active when configured for native GLAN_DOCK# functionality and determined by LAN controller.

GNT[3:0]#/GPIO[55,53,51]

PULL-UP 20K

GPIO20

PULL-DOWN 20K

GPIO49

PULL-UP 20K

LDA[3:0]#/FHW[3:0]#

PULL-UP 20K

LAN_RXD[2:0]

PULL-UP 20K

LDRQ[0]

PULL-UP 20K

LDRQ[1]/GPIO23

PULL-UP 20K

PME#

PULL-UP 20K

PWRBTN#

PULL-UP 20K

SATALED#

PULL-UP 15K

SPI_CS1#/GPIO58/CLGPIO6

PULL-UP 20K

SPI_MOSI

PULL-DOWN 20K

SPI_MISO

PULL-UP 20K

SPKR

PULL-DOWN 20K

TACH_[3:0]

PULL-UP 20K

TP[3]

PULL-UP 20K

USB[11:0][P,N]

PULL-DOWN 15K

TP[3] PULL-UP 20K USB[11:0][P,N] PULL-DOWN 15K D E Cantiga chipset and ICH9M I/O controller Hub strapping

D

E

Cantiga chipset and ICH9M I/O controller Hub strapping configuration

Montevina Platform Design guide 22339 Rev.0.5

Pin Name

Strap Description

 

Configuration

CFG[2:0]

FSB Frequency Select 000 = FSB1067

011

= FSB667

010

= FSB800

others = Reserved

CFG[4:3]

Reserved

 

CFG8

CFG[15:14]

CFG[18:17]

CFG5

DMI x2 Select

0

= DMI x2

1

= DMI x4 (Default)

CFG6

iTPM Host Interface

0

= The iTPM Host Interface is enabled (Note 2)

1

= The iTPM Host Interface is disabled (default)

CFG7

Intel Management engine crypto strap

0

= Transport Layer Security (TLS) cipher suite with no confidentiality

1

= TLS cipher suite with confidentiality(Default)

CFG9

PCIE Graphics Lane

0

= Reserved Lanes, 15->0, 14->1 ect

1

= Normal operation (Default): Lane Numbered in Order

CFG10

 

PCIE Loopback enable 0 = Enable (Note 3)

1

= Disable (Default)

CFG[13:12]

XOR/ALL

00

= Reserve

10

= XOR mode Enabled

01

= ALLZ mode Enable (Note 3)

11 = Disabled (Default)

CFG16

FSB Dynamic ODT

0

= Dynamic ODT Disabled

1

= Dynamic ODT Enabled (Default)

CFG19

DMI Lane Reversal

0

= Normal operation (Default): Lane Numbered in Order

1

= Reverse Lanes

DMI x4 mode [MCH->ICH]: (3->0, 2->1, 1->2 and 0->3)

DMI x2 mode [MCH->ICH]: (3->0, 2->1)

CFG20

 

Digital Display Port 0 = Only Digital Display Port or PCIE is

(SDVO/DP/iHDMI) Concurrent with PCIe

1

operational (Default)

= Digital display Port and PCIe are operating simulataneously via the PEG port

SDVO

SDVO Present

0

= No SDVO Card Present (Default)

_CTRLDATA

1

= SDVO Card Present

 

L_DDC_DATA Local Flat Panel (LFP) Present

0

= LFP Disabled (Default)

1

= LFP Card Present; PCIE disabled

NOTE:

1.

All strap signals are sampled with respect to the leading edge of the (G)MCH Power OK (PWROK) signal.

2.

iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of the Firmware. This 'Soft-Strap' is activated only after enabling iTPM via CFG6. Only one of the CFG10/CFG12/CFG13 straps can be enabled at any time.

<Core Design>

<Core Design>

<Core Design>

4

Design> <Core Design> <Core Design> 4 3 2 1 Wistron Corporation Wistron Corporation Wistron

3

Design> <Core Design> <Core Design> 4 3 2 1 Wistron Corporation Wistron Corporation Wistron

2

<Core Design> <Core Design> 4 3 2 1 Wistron Corporation Wistron Corporation Wistron

1

Wistron Corporation Wistron Corporation Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, 21F,

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Table of Content

Table of Content

Table of Content

 

Size

Size

Size

Custom

Custom

Custom

Document Number Document Number Document Number Roberts Roberts Roberts

Document Number

Document Number

Document Number

Roberts

Roberts

Roberts

Rev

Rev

Rev

-3

-3

-3

Date:

Date:

Date:

Monday, May 18, 2009

Monday, May 18, 2009

Monday, May 18, 2009

Sheet

Sheet

Sheet

3

3

3

of

of

of

59

59

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1

SSID = CLOCK NEWCARD_CLKREQ# R193R193 1 2 10KR2J-3-GP10KR2J-3-GP +3.3V_RUN MINI1_CLKREQ# R195R195 1
SSID = CLOCK
NEWCARD_CLKREQ#
R193R193
1 2
10KR2J-3-GP10KR2J-3-GP
+3.3V_RUN
MINI1_CLKREQ#
R195R195
1 10KR2J-3-GP10KR2J-3-GP
2
NEWCARD_CLKREQ#
CLK_PCIE_NEW
3D3V_S0_CK505
3D3V_S0_CK505_IO
CLK_PCIE_NEW#
+3.3V_RUN
3D3V_S0_CK505_IO
CLK_XTAL_IN
X3
X3
R204
R204
CLK_XTAL_OUT
1
2
1
2
DY
DY
DY
DY
D
D
0R0603-PAD
0R0603-PAD
X-14D31818M-37GP
X-14D31818M-37GP
C462
C462
C461
C461
U54
U54
DY
DY
SC12P50V2JN-3GP
SC12P50V2JN-3GP
SC12P50V2JN-3GP
SC12P50V2JN-3GP
A00.08/0910
61
CLK_CPU_BCLK
CPUT0
60
CLK_CPU_BCLK#
CPUC0
3
58
CLK_MCH_BCLK
X1
CPUT1_F
2
57
CLK_MCH_BCLK#
X2
CPUC1_F
R217R217
22R2J-2-GP22R2J-2-GP
1
2
CLK_48M_CARD
54
CLK_CPU_ITP
CPUT2_ITP/SRCT8
R216
R216
53
CLK_CPU_ITP#
CPUC2_ITP/SRCC8
FSA
1
2
17
CLK_48M_ICH
USB_48MHZ/FSLA
+3.3V_RUN
3D3V_S0_CK505
22R2J-2-GP
22R2J-2-GP
1
DY
DY
2
51
CLK_PCIE_LAN
SRCT7/CR#_F
C245
C245
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
50
CLK_PCIE_LAN#
SRCC7/CR#_E
R200
R200
1
2
45
H_STP_PCI#
PCI_STOP#
0R0603-PAD
0R0603-PAD
44
48
H_STP_CPU#
CPU_STOP#
SRCT6
47
SRCC6
ICS9LPRS355BKLFT-GP-U
ICS9LPRS355BKLFT-GP-U
41
CLK_PCIE_NEW
SRCT10
7
42
CLK_PCIE_NEW#
ICH_SMBCLK
SCLK
SRCC10
6
ICH_SMBDATA
SDATA
40
SRCT11/CR#_H
NEWCARD_CLKREQ#
63
39
CK_PWRGD
CK_PWRGD/PD#
SRCC11/CR#_G
MINI1_CLKREQ#
37
C
CLK_PCIE_MINI1
SRCT9
C
38
CLK_PCIE_MINI1#
SRCC9
8
CLKSATAREQ#
PCI0/CR#_A
R178R178
1 475R2F-L1-GP475R2F-L1-GP
CLKREQ#_1
2
10
34
CLK_MCH_3GPLL
CLKREQ#_B
PCI1/CR#_B
SRCT4
R196
R196
33R2J-2-GP
33R2J-2-GP
PCI2_TME
PCLK_FWH
1 DY
DY
2
11
35
CLK_MCH_3GPLL#
PCI2/TME
SRCC4
A00.08/0922
12
PCI3
R207R207
33R2J-2-GP33R2J-2-GP
27_SEL
1 2
13
31
PCLK_KBC
CLK_PCIE_ICH
PCI4/27_SELECT
SRCT3/CR#_C
R212R212
33R2J-2-GP33R2J-2-GP
ITP_EN
1 2
14
32
CLK_PCI_ICH
CLK_PCIE_ICH#
PCI_F5/ITP_EN
SRCC3/CR#_D
28
CLK_PCIE_SATA
SRCT2/SATAT
29
CLK_PCIE_SATA#
SRCC2/SATAC
FSB
64
FSLB/TEST_MODE
R190R190
33R2J-2-GP33R2J-2-GP
FSC
1 2
5
CLK_14M_ICH
REF0/FSLC/TEST_SEL
24
MCH_SSCDREFCLK
27MHZ_NONSS/SRCT1/SE1
55
25
MCH_SSCDREFCLK#
NC#55
27MHZ_SS/SRCC1/SE2
20
CLK_MCH_DREFCLK
SRCT0/DOTT_96
21
CLK_MCH_DREFCLK#
SRCC0/DOTC_96
DY
DY
DY
DY
DY
DY
A00.08/0910
Main source: 71.08513.003 (SLG8SP513VTR)
2nd source: 71.00875.C03 (RTM875N-606-VD-GRT)
3rd source:
Co-layout Ref: 71.09355.B03 (ICS9LPRS355BKLFT)
B
B
3D3V_S0_CK505
3D3V_S0_CK505
27_SEL
CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#
R206
R206
EC140
EC140
EC139
EC139
DY
DY
DY
DY
R209
R209
ITP_EN
Output
R198
R198
10KR2J-3-GP
10KR2J-3-GP
SC47P50V2JN-3GP
SC47P50V2JN-3GP
SC47P50V2JN-3GP
SC47P50V2JN-3GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
PCI2_TME
Output
0
SRC8
ITP_EN
1
CPU_ITP
PCI2_TME
0 Overclocking of CPU and SRC allowed
R218
R218
R202
R202
27_SEL
PIN 20
PIN 21
DY
DY
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
1 Overclocking of CPU and SRC not allowed
DY
DY
0 DOT96T
DOT96C
GM45
1 SRCT0
SRCC0
PM45
SEL2 SEL1 SEL0
CPU
FSB
A
R186R186
1 10KR2J-3-GP10KR2J-3-GP
FSC
A
FSC
FSB
FSA
2
<Core Design>
<Core Design>
<Core Design>
CPU_BSEL2
SB
1 R412
R412
FSB
2
CPU_BSEL1
0R0402-PAD
0R0402-PAD
1
0
1
100M
X
Wistron Corporation
Wistron Corporation
Wistron Corporation
R214R214
1 2K2R2J-2-GP2K2R2J-2-GP
FSA
2
CPU_BSEL0
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
0
0
1
133M
533M
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
0
1
667M
R215R215
1 1KR2J-1-GP1KR2J-1-GP
1
166M
MCH_CLKSEL0
Title
Title
Title
0
200M
800M
R411R411
1 1KR2J-1-GP1KR2J-1-GP
1
0
MCH_CLKSEL1
Clock Generator SLG8SP513VTR
Clock Generator SLG8SP513VTR
Clock Generator SLG8SP513VTR
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
R181R181
00
266M
1067M
1 1KR2J-1-GP1KR2J-1-GP
0
2
MCH_CLKSEL2
Custom
Custom
Custom
Roberts
Roberts
Roberts
-3
-3
-3
Date:
Date:
Date:
Tuesday, August 11, 2009
Tuesday, August 11, 2009
Tuesday, August 11, 2009
Sheet
Sheet
Sheet
4
4
4
of
of
of
59
59
59
5
4
3
2
1
12
12
C233
C233
C229
C229
12
12
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
12
12
C211
C211
C226
C226
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
12
12
C218
C218
C210
C210
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
12
C238
C238
C239
C239
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
12
C207
C207
C209
C209
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
12
C225
C225
C215
C215
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
12
C234
C234
C237
C237
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
12
12
C236
C236
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
12
C243
C243
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
12
C224
C224
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
12
12
18
4
GND48
VDDREF
15
16
GNDPCI
VDD48
1
9
GNDREF
VDDPCI
46
VDDSRC
62
VDDCPU
22
23
GND
VDDPLL3
30
GNDSRC
36
GNDSRC
49
GNDSRC
59
19
GNDCPU
VDD96_IO
26
27
GND
VDDPLL3_IO
43
VDDSRC_IO
52
VDDSRC_IO
33
VDDSRC_IO
65
56
GND
VDDCPU_IO
12
12
12
12
C463
C463
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
12
C464
C464
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
12
EC57
EC57
SC22P50V2JN-4GP
SC22P50V2JN-4GP

D

C

B

A

5

SSID = CPU

4

3

2

H_A#[35 3]

U41A U41A 1 1 OF 4 OF 4 H_A#[35 3] H_A#3 J4 H1 H_ADS# A3#
U41A
U41A
1 1
OF 4
OF 4
H_A#[35 3]
H_A#3
J4
H1
H_ADS#
A3#
ADS#
H_A#4
L5
E2
H_BNR#
A4#
BNR#
H_A#5
L4
G5
H_BPRI#
A5#
BPRI#
H_A#6
K5
A6#
H_A#7
M3
H5
H_DEFER#
A7#
DEFER#
H_A#8
N2
F21
H_DRDY#
A8#
DRDY#
H_A#9
J1
E1
H_DBSY#
A9#
DBSY#
H_A#10
N3
A10#
H_A#11
P5
F1
H_BREQ#0
A11#
BR0#
H_A#12
P2
A12#
H_A#13
CPU_IERR#
R47R47
56R2J-4-GP56R2J-4-GP
L2
D20
1
2
+1.05V_VCCP
A13#
IERR#
H_A#14
P4
B3
H_INIT#
A14#
INIT#
H_A#15
P1
A15#
H_A#16
R1
H4
H_LOCK#
A16#
LOCK#
M1
H_ADSTB#0
H_CPURST#
ADSTB0#
H_CPURST#
C1
H_REQ#[4 0]
H_RS#[2 0]
RESET#
H_REQ#0
H_RS#0
K3
F3
REQ0#
RS0#
H_REQ#1
H_RS#1
H2
F4
REQ1#
RS1#
H_REQ#2
H_RS#2
K2
G3
REQ2#
RS2#
H_REQ#3
J3
G2
H_TRDY#
REQ3#
TRDY#
H_REQ#4
L1
REQ4#
G6
H_HIT#
HIT#
H_A#17
Y2
E4
H_HITM#
A17#
HITM#
H_A#18
U5
A18#
H_A#19
ITP_BPM#0
R3
AD4
ITP_BPM#0
A19#
BPM0#
H_A#20
ITP_BPM#1
W6
AD3
ITP_BPM#1
A20#
BPM1#
H_A#21
ITP_BPM#2
U4
AD1
ITP_BPM#2
A21#
BPM2#
H_A#22
ITP_BPM#3
Y5
AC4
ITP_BPM#3
A22#
BPM3#
H_A#23
ITP_BPM#4
U1
AC2
ITP_BPM#4
A23#
PRDY#
H_A#24
ITP_BPM#5
R4
AC1
ITP_BPM#5
A24#
PREQ#
H_A#25
ITP_TCK
T5
AC5
ITP_TCK
A25#
TCK
H_A#26
ITP_TDI
T3
AA6
ITP_TDI
A26#
TDI
H_A#27
ITP_TDO
W2
AB3
ITP_TDO
A27#
TDO
H_A#28
ITP_TMS
W5
AB5
ITP_TMS
A28#
TMS
H_A#29
ITP_TRST#
Y4
AB6
ITP_TRST#
A29#
TRST#
H_A#30
ITP_DBRESET#
U2
C20
ITP_DBRESET#
A30#
DBR#
H_A#31
V4
A31#
H_A#32
R50
R50
0R2J-2-GP
0R2J-2-GP
W3
1 DY
DY
2
CPU_PROCHOT#
A32#
H_A#33
AA4
THERMAL
THERMAL
A33#
H_A#34
R51R51
1 56R2J-4-GP56R2J-4-GP
H_THERMDA
AB2
2
+1.05V_VCCP
A34#
H_A#35
AA3
D21
A35#
PROCHOT#
V1
A24
H_ADSTB#1
H_THERMDA
ADSTB1#
THRMDA
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
DY C49
C49
B25
H_THERMDC
DY
THRMDC
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
A6
H_A20M#
A20M#
H_THERMDC
A5
C7
H_FERR#
H_THRMTRIP#
FERR#
THERMTRIP#
H_THRMTRIP# should connect to
C4
H_IGNNE#
IGNNE#
R76
R76
2
56R2J-4-GP
56R2J-4-GP
1 DY
DY
ICH9 and MCH without T-ing.
+1.05V_VCCP
D5
H_STPCLK#
A00.08/0903
STPCLK#
C6
HCLK
HCLK
A22
H_INTR
CLK_CPU_BCLK
LINT0
BCLK0
B4
A21
H_NMI
CLK_CPU_BCLK#
LINT1
BCLK1
A3
H_SMI#
SMI#
1 RSVD_CPU_1
M4
RSVD#M4
TP30TP30
1 RSVD_CPU_2
N5
RSVD#N5
TP31TP31
1 RSVD_CPU_3
T2
RSVD#T2
TP13TP13
1 RSVD_CPU_4
V3
RSVD#V3
TP23TP23
1 RSVD_CPU_5
B2
RSVD#B2
TP21TP21
1 RSVD_CPU_6
C3
RSVD#C3
TEST7
ADDR GROUP 0
ADDR GROUP 0
ADDR GROUP 1
ADDR GROUP 1
TP24TP24
1 RSVD_CPU_7
D2
ICH
ICH
RSVD#D2
TP19TP19
1 RSVD_CPU_8
D22
RSVD#D22
TP55TP55
1 RSVD_CPU_9
D3
RSVD#D3
TP25TP25
1 RSVD_CPU_10
F6
RSVD#F6
TP34TP34
1 RSVD_CPU_11
B1
KEY_NC
TP12TP12
BGA479-SKT6-GPU7
BGA479-SKT6-GPU7
RESERVED
RESERVED
XDP/ITP SIGNALS
XDP/ITP SIGNALS
CONTROL
CONTROL
12

62.10040.221

1

D

XDP/ITP SIGNALS CONTROL CONTROL 12 62.10040.221 1 D C B <Core Design> <Core Design> <Core

C

XDP/ITP SIGNALS CONTROL CONTROL 12 62.10040.221 1 D C B <Core Design> <Core Design> <Core

B

XDP/ITP SIGNALS CONTROL CONTROL 12 62.10040.221 1 D C B <Core Design> <Core Design> <Core

<Core Design>

<Core Design>

<Core Design>

A

Wistron Corporation Wistron Corporation Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, 21F,

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

CPU-FSB(1/3)

CPU-FSB(1/3)

CPU-FSB(1/3)

 

Size

Size

Size

Custom

Custom

Custom

Document Number Document Number Document Number Roberts Roberts Roberts

Document Number

Document Number

Document Number

Roberts

Roberts

Roberts

Rev

Rev

Rev

-3

-3

-3

Date:

Date:

Date:

Tuesday, August 11, 2009

Tuesday, August 11, 2009

Tuesday, August 11, 2009

Sheet

Sheet

Sheet

5

5

5

of

of

of

59

59

59

D

C

B

A

5

SSID = CPU

H_DINV#[3 0]

H_DSTBN#[3 0]

H_DSTBP#[3 0]

H_D#[63 0]

H_DINV#[3 0]

H_DSTBN#[3 0]

H_DSTBP#[3 0]

H_D#[63 0]

4

3

U41B U41B 2 2 OF 4 OF 4 H_D#0 H_D#32 E22 Y22 D0# D32# H_D#1
U41B
U41B
2 2
OF 4
OF 4
H_D#0
H_D#32
E22
Y22
D0#
D32#
H_D#1
H_D#33
F24
AB24
D1#
D33#
H_D#2
H_D#34
E26
V24
D2#
D34#
H_D#3
H_D#35
G22
V26
D3#
D35#
H_D#4
H_D#36
F23
V23
D4#
D36#
H_D#5
H_D#37
G25
T22
D5#
D37#
H_D#6
H_D#38
E25
U25
D6#
D38#
H_D#7
H_D#39
E23
U23
D7#
D39#
H_D#8
H_D#40
K24
Y25
D8#
D40#
H_D#9
H_D#41
G24
W22
D9#
D41#
H_D#10
H_D#42
J24
Y23
D10#
D42#
H_D#11
H_D#43
J23
W24
DATA GRP0
DATA GRP0
DATA GRP1
DATA GRP1
D11#
D43#
H_D#12
H_D#44
H22
W25
D12#
D44#
H_D#13
H_D#45
F26
AA23
D13#
D45#
H_D#14
H_D#46
K22
AA24
D14#
D46#
H_D#15
H_D#47
H23
AB25
D15#
D47#
J26
Y26
H_DSTBN#0
H_DSTBN#2
DSTBN0#
DSTBN2#
H26
AA26
H_DSTBP#0
H_DSTBP#2
DSTBP0#
DSTBP2#
H25
U22
H_DINV#0
H_DINV#2
DINV0#
DINV2#
H_D#16
H_D#48
N22
AE24
D16#
D48#
H_D#17
H_D#49
K25
AD24
D17#
D49#
H_D#18
H_D#50
P26
AA21
D18#
D50#
H_D#19
H_D#51
R23
AB22
D19#
D51#
H_D#20
H_D#52
L23
AB21
D20#
D52#
H_D#21
H_D#53
M24
AC26
D21#
D53#
H_D#22
H_D#54
L22
AD20
D22#
D54#
H_D#23
H_D#55
M23
AE22
D23#
D55#
Layout notes
Z= 55 Ohm 0.5" MAX for CPU_GTLREF0
H_D#24
H_D#56
P25
AF23
D24#
D56#
H_D#25
H_D#57
P23
AC25
D25#
D57#
H_D#26
H_D#58
P22
AE21
D26#
D58#
H_D#27
H_D#59
T24
AD21
D27#
D59#
+1.05V_VCCP
H_D#28
H_D#60
R24
AC22
D28#
D60#
H_D#29
H_D#61
L25
AD23
D29#
D61#
H_D#30
H_D#62
T25
AF22
D30#
D62#
H_D#31
H_D#63
N25
AC23
D31#
D63#
R357
R357
L26
AE25
H_DSTBN#1
H_DSTBN#3
DSTBN1#
DSTBN3#
1KR2F-3-GP
1KR2F-3-GP
M26
AF24
H_DSTBP#1
H_DSTBP#3
DSTBP1#
DSTBP3#
N24
AC20
H_DINV#1
H_DINV#3
DINV1#
DINV3#
CPU_GTLREF0
COMP0
AD26
R26
R350R350
1 2
27D4R2F-L1-GP27D4R2F-L1-GP
GTLREF
COMP0
R53
R53
1KR2J-1-GP
1KR2J-1-GP
TEST1
COMP1
R349R349
54D9R2F-L1-GP54D9R2F-L1-GP
1 1 DY
DY
2
C23
MISC
MISC
U26
1 2
TEST1
COMP1
R60
R60
1KR2J-1-GP
TEST2
2
1KR2J-1-GP
COMP2
D25
AA1
R14R14
1 DY
DY
1 2
27D4R2F-L1-GP27D4R2F-L1-GP
TEST2
COMP2
R354
R354
DY C376
C376
R58
R58
1KR2J-1-GP
1KR2J-1-GP
CPU_TEST3
COMP3
R13R13
54D9R2F-L1-GP54D9R2F-L1-GP
DY
DY
DY
2
C24
Y1
1 2
TEST3
COMP3
2KR2F-3-GP
2KR2F-3-GP
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
AF26
TEST4
R7
R7
1KR2J-1-GP
1KR2J-1-GP
CPU_TEST5
1 DY
DY
2
AF1
E5
H_DPRSTP#
TEST5
DPRSTP#
A26
B5
H_DPSLP#
TEST6
DPSLP#
D24
H_DPWR#
DPWR#
B22
D6
CPU_BSEL0
H_PWRGOOD
BSEL0
PWRGOOD
B23
D7
CPU_BSEL1
H_CPUSLP#
BSEL1
SLP#
C21
AE6
CPU_BSEL2
PSI#
BSEL2
PSI#
BGA479-SKT6-GPU7
BGA479-SKT6-GPU7
12
1
2
12
DATA GRP2DATA
DATA GRP2DATA
GRP3
GRP3

62.10040.221

Route the CPU_TEST3 and CPU_TEST5 signals through a ground referenced Zo = 55-ohm trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection.

via and is accessible through an oscilloscope connection. 2 1 Layout Note: Comp0, 2 connect with

2

1

Layout Note:

Comp0, 2 connect with Zo=27.4 ohm, make

trace length shorter than 0.5".

Comp1, 3 connect with Zo=55 ohm, make trace length shorter than 0.5".

<Core Design>

<Core Design>

<Core Design>

D

Design> <Core Design> <Core Design> D C B A Wistron Corporation Wistron Corporation Wistron

C

Design> <Core Design> <Core Design> D C B A Wistron Corporation Wistron Corporation Wistron

B

A

Wistron Corporation Wistron Corporation Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, 21F,

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

CPU-FSB(2/3)

CPU-FSB(2/3)

CPU-FSB(2/3)

 

Size

Size

Size

Custom

Custom

Custom

Document Number

Document Number

Document Number

Roberts

Roberts

Roberts

Rev

Rev

Rev

-3

-3

-3

Date:

Date:

Date:

Tuesday, August 11, 2009

Tuesday, August 11, 2009

Tuesday, August 11, 2009

Sheet

Sheet

Sheet

6

6

6

of

of

of

59

59

59

5

4

3

2

1

SSID = CPU

+VCC_CORE

U41D U41D 4 4 OF 4 OF 4 A4 P6 VSS VSS A8 P21 VSS
U41D
U41D
4
4
OF 4
OF 4
A4
P6
VSS
VSS
A8
P21
VSS
VSS
C10
C10
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
A11
P24
VSS
VSS
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
A14
R2
VSS
VSS
A16
R5
VSS
VSS
A19
R22
VSS
VSS
D
D
A23
R25
VSS
VSS
+VCC_CORE
+VCC_CORE
AF2
T1
VSS
VSS
B6
T4
VSS
VSS
B8
T23
VSS
VSS
U41C
U41C
3
3
OF 4
OF 4
B11
T26
VSS
VSS
+VCC_CORE
B13
U3
VSS
VSS
A7
AB20
B16
U6
VCC
VCC
VSS
VSS
A9
AB7
B19
U21
VCC
VCC
VSS
VSS
A10
AC7
B21
U24
VCC
VCC
VSS
VSS
A12
AC9
B24
V2
VCC
VCC
VSS
VSS
A13
AC12
C5
V5
VCC
VCC
VSS
VSS
A15
AC13
C24
C24
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
C8
V22
VCC
VCC
VSS
VSS
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
A17
AC15
C11
V25
VCC
VCC
VSS
VSS
A18
AC17
C14
W1
VCC
VCC
VSS
VSS
A20
AC18
C16
W4
VCC
VCC
VSS
VSS
B7
AD7
C19
W23
VCC
VCC
VSS
VSS
B9
AD9
C2
W26
VCC
VCC
VSS
VSS
B10
AD10
C22
Y3
VCC
VCC
VSS
VSS
B12
AD12
C25
Y6
VCC
VCC
VSS
VSS
+VCC_CORE
B14
AD14
D1
Y21
VCC
VCC
VSS
VSS
B15
AD15
D4
Y24
VCC
VCC
VSS
VSS
B17
AD17
D8
AA2
VCC
VCC
VSS
VSS
B18
AD18
D11
AA5
VCC
VCC
VSS
VSS
B20
AE9
D13
AA8
VCC
VCC
VSS
VSS
C9
AE10
D16
AA11
VCC
VCC
VSS
VSS
C336
C336
C10
AE12
DY
DY
D19
AA14
VCC
VCC
VSS
VSS
C12
AE13
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
D23
AA16
VCC
VCC
VSS
VSS
C13
AE15
D26
AA19
VCC
VCC
VSS
VSS
C15
AE17
E3
AA22
VCC
VCC
VSS
VSS
C17
AE18
E6
AA25
C
VCC
VCC
VSS
VSS
C
C18
AE20
E8
AB1
VCC
VCC
VSS
VSS
D9
AF9
E11
AB4
VCC
VCC
VSS
VSS
D10
AF10
E14
AB8
VCC
VCC
VSS
VSS
D12
AF12
E16
AB11
VCC
VCC
VSS
VSS
D14
AF14
E19
AB13
VCC
VCC
VSS
VSS
D15
AF15
E21
AB16
VCC
VCC
VSS
VSS
D17
AF17
E24
AB19
VCC
VCC
VSS
VSS
D18
AF18
F5
AB23
VCC
VCC
VSS
VSS
+1.05V_VCCP
E7
AF20
F8
AB26
VCC
VCC
VSS
VSS
E9
F11
AC3
VCC
VSS
VSS
E10
G21
F13
AC6
VCC
VCCP
VSS
VSS
E12
V6
F16
AC8
VCC
VCCP
VSS
VSS
E13
J6
F19
AC11
VCC
VCCP
VSS
VSS
E15
K6
C8
C8
DY
DY
F2
AC14
VCC
VCCP
VSS
VSS
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
E17
M6
F22
AC16
VCC
VCCP
VSS
VSS
E18
J21
F25
AC19
VCC
VCCP
VSS
VSS
E20
K21
G4
AC21
VCC
VCCP
VSS
VSS
F7
M21
G1
AC24
VCC
VCCP
VSS
VSS
F9
N21
G23
AD2
VCC
VCCP
VSS
VSS
F10
N6
G26
AD5
VCC
VCCP
VSS
VSS
F12
R21
H3
AD8
VCC
VCCP
VSS
VSS
F14
R6
H6
AD11
VCC
VCCP
VSS
VSS
F15
T21
H21
AD13
VCC
VCCP
VSS
VSS
F17
T6
layout note: "+1.5V_VCCA"
H24
AD16
VCC
VCCP
VSS
VSS
F18
V21
J2
AD19
NCTF
VCC
VCCP
as short as possible
VSS
VSS
+1.5V_VCCA
+1.5V_RUN
F20
W21
J5
AD22
VCC
VCCP
VSS
VSS
PIN
AA7
J22
AD25
VCC
VSS
VSS
R356
R356
CPU_GND1
AA9
B26
1
2
J25
AE1
1
VCC
VCCA
VSS
VSS
AA10
C26
0R0603-PAD
0R0603-PAD
K1
AE4
TP10TP10
VCC
VCCA
VSS
VSS
B
AA12
K4
AE8
B
CPU_VID[6 0]
VCC
VSS
VSS
CPU_VID0
AA13
AD6
K23
AE11
VCC
VID0
VSS
VSS
CPU_VID1
AA15
AF5
Layout Note:
K26
AE14
VCC
VID1
VSS
VSS
CPU_VID2
C374
C374
C377
C377
AA17
AE5
L3
AE16
VCC
VID2
CPU_VID3
AA18
AF4
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
VCC
VID3
CPU_VID4
Place as close as possible
to the CPU VCCA pin.
VSS
VSS
L6
AE19
VSS
VSS
AA20
AE3
L21
AE23
VCC
VID4
VSS
VSS
CPU_VID5
CPU_GND2
AB9
AF3
L24
AE26
1
VCC
VID5
VSS
VSS
CPU_VID6
CPU_GND3
AC10
AE2
M2
A2
1
TP224TP224
VCC
VID6
VSS
VSS
R311R311
100R2F-L1-GP-U100R2F-L1-GP-U
TP20TP20
AB10
2
M5
AF6
1 +VCC_CORE
VCC
VSS
VSS
AB12
M22
AF8
VCC
VSS
VSS
AB14
AF7
M25
AF11
VCC_SENSE
VCC
VCCSENSE
VSS
VSS
AB15
VCC_SENSE and VSS_SENSE lines
should be of equal length.
N1
AF13
VCC
VSS
VSS
AB17
N4
AF16
VCC
VSS
VSS
AB18
AE7
N23
AF19
VSS_SENSE
VCC
VSSSENSE
VSS
VSS
N26
AF21
VSS
VSS
R302R302
100R2F-L1-GP-U100R2F-L1-GP-U
CPU_GND4
1 2
P3
A25
1
VSS
VSS
BGA479-SKT6-GPU7
BGA479-SKT6-GPU7
TP56TP56
AF25
VSS
62.10040.221
BGA479-SKT6-GPU7
BGA479-SKT6-GPU7
62.10040.221
A
A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU-Power(3/3)
CPU-Power(3/3)
CPU-Power(3/3)
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
-3
-3
-3
Roberts
Roberts
Roberts
Date:
Date:
Date:
Tuesday, August 11, 2009
Tuesday, August 11, 2009
Tuesday, August 11, 2009
Sheet
Sheet
Sheet
7
7
7
of
of
of
59
59
59
5
4
3
2
1
12
12
12
12
TC17
TC17
C12
C12
C14
C14
C25
C25
ST220U2D5VBM-LGP
ST220U2D5VBM-LGP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
12
12
12
C44
C44
C17
C17
C15
C15
C36
C36
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
12
12
12
C43
C43
C32
C32
C352
C352
C31
C31
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
12
12
12
12
C45
C45
C30
C30
C26
C26
C11
C11
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
12
12
12
12
C9
C9
C29
C29
C35
C35
C370
C370
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
12
12
12
C7
C7
C340
C340
C338
C338
C5
C5
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
12
12
12
C344
C344
C367
C367
C6
C6
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
12
12
C347
C347
C13
C13
C3
C3
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
12
12
C368
C368
C357
C357
C365
C365
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
12
12
C363
C363
C366
C366
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
12

D

C

B

A

5

SSID = MCH

4

3

2

1

U52A U52A 1 1 OF 10 OF 10 H_A#[35 3] H_A#[35 3] H_D#[63 0] H_A#3
U52A
U52A
1
1
OF 10
OF 10
H_A#[35 3]
H_A#[35 3]
H_D#[63 0]
H_A#3
A14
H_D#[63 0]
H_A#_3
H_D#0
H_A#4
F2
C15
H_D#_0
H_A#_4
H_D#1
H_A#5
G8
F16
H_D#_1
H_A#_5
H_D#2
H_A#6
F8
H13
H_D#_2
H_A#_6
H_D#3
H_A#7
E6
C18
H_D#_3
H_A#_7
H_D#4
H_A#8
G2
M16
H_D#_4
H_A#_8
H_D#5
H_A#9
H6
J13
H_D#_5
H_A#_9
H_D#6
H_A#10
H2
P16
H_D#_6
H_A#_10
H_D#7
H_A#11
F6
R16
H_D#_7
H_A#_11
H_D#8
H_A#12
D4
N17
H_D#_8
H_A#_12
H_D#9
H_A#13
H3
M13
H_D#_9
H_A#_13
H_D#10
H_A#14
M9
E17
H_D#_10
H_A#_14
H_D#11
H_A#15
M11
P17
H_D#_11
H_A#_15
H_D#12
H_A#16
J1
F17
H_D#_12
H_A#_16
H_D#13
H_A#17
J2
G20
H_D#_13
H_A#_17
H_D#14
H_A#18
N12
B19
H_D#_14
H_A#_18
H_D#15
H_A#19
J6
J16
H_D#_15
H_A#_19
H_D#16
H_A#20
P2
E20
H_D#_16
H_A#_20
H_D#17
H_A#21
L2
H16
H_D#_17
H_A#_21
H_D#18
H_A#22
R2
J20
H_D#_18
H_A#_22
H_D#19
H_A#23
N9
L17
H_D#_19
H_A#_23
H_D#20
H_A#24
L6
A17
H_D#_20
H_A#_24
H_D#21
H_A#25
M5
B17
H_D#_21
H_A#_25
H_D#22
H_A#26
J3
L16
H_D#_22
H_A#_26
H_D#23
H_A#27
N2
C21
H_D#_23
H_A#_27
H_D#24
H_A#28
R1
J17
H_D#_24
H_A#_28
H_D#25
H_A#29
N5
H20
H_D#_25
H_A#_29
H_D#26
H_A#30
N6
B18
H_D#_26
H_A#_30
H_D#27
H_A#31
P13
K17
H_D#_27
H_A#_31
H_D#28
H_A#32
N8
B20
H_D#_28
H_A#_32
H_D#29
H_A#33
L7
F21
H_D#_29
H_A#_33
+1.05V_VCCP
H_D#30
H_A#34
N10
K21
H_D#_30
H_A#_34
H_SWING routing Trace width and
Spacing use 10 / 20 mil
H_D#31
H_A#35
M3
L20
H_D#_31
H_A#_35
H_D#32
Y3
H_D#_32
H_D#33
AD14
H12
H_ADS#
H_D#_33
H_ADS#
R368
R368
H_D#34
Y6
B16
H_ADSTB#0
H_D#_34
H_ADSTB#_0
221R2F-2-GP
221R2F-2-GP
H_D#35
Y10
G17
H_ADSTB#1
H_D#_35
H_ADSTB#_1
H_SWING Resistors and
Capacitors close MCH
500 mil ( MAX )
H_D#36
Y12
A9
H_BNR#
H_D#_36
H_BNR#
H_D#37
Y14
F11
H_BPRI#
H_D#_37
H_BPRI#
H_D#38
Y7
G12
H_BREQ#0
H_D#_38
H_BREQ#
H_SWING
H_D#39
W2
E9
H_DEFER#
H_D#_39
H_DEFER#
H_D#40
AA8
B10
H_DBSY#
H_D#_40
H_DBSY#
H_D#41
Y9
AH7
CLK_MCH_BCLK
H_D#_41
HPLL_CLK
C399
C399
R367
R367
H_D#42
AA13
AH6
CLK_MCH_BCLK#
H_D#_42
HPLL_CLK#
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
100R2F-L1-GP-U
100R2F-L1-GP-U
H_D#43
AA9
J11
H_DPWR#
H_D#_43
H_DPWR#
H_D#44
AA11
F9
H_DRDY#
H_D#_44
H_DRDY#
H_D#45
AD11
H9
H_HIT#
H_D#_45
H_HIT#
H_D#46
AD10
E12
H_HITM#
H_D#_46
H_HITM#
H_D#47
AD13
H11
H_LOCK#
H_D#_47
H_LOCK#
H_D#48
AE12
C9
H_TRDY#
H_D#_48
H_TRDY#
H_D#49
AE9
H_D#_49
H_D#50
AA2
H_D#_50
H_D#51
AD8
H_D#_51
H_D#52
H_DINV#[3 0]
AA3
H_DINV#[3 0]
H_D#_52
H_RCOMP routing Trace width and
Spacing use 10 / 20 mil
H_D#53
H_DINV#0
AD3
J8
H_D#_53
H_DINV#_0
H_D#54
H_DINV#1
AD7
L3
H_D#_54
H_DINV#_1
H_D#55
H_DINV#2
AE14
Y13
H_D#_55
H_DINV#_2
H_D#56
H_DINV#3
AF3
Y1
H_D#_56
H_DINV#_3
H_D#57
H_DSTBN#[3 0]
AC1
H_DSTBN#[3 0]
H_D#_57
H_RCOMP
H_D#58
H_DSTBN#0
1
2
AE3
L10
H_D#_58
H_DSTBN#_0
R361
R361
24D9R2F-L-GP
24D9R2F-L-GP
H_D#59
H_DSTBN#1
AC3
M7
H_D#_59
H_DSTBN#_1
H_D#60
H_DSTBN#2
AE11
AA5
H_D#_60
H_DSTBN#_2
H_D#61
H_DSTBN#3
AE8
AE6
H_D#_61
H_DSTBN#_3
Place R51 near to the chip ( < 0.5")
H_D#62
H_DSTBP#[3 0]
AG2
H_DSTBP#[3 0]
H_D#_62
H_D#63
H_DSTBP#0
AD6
L9
H_D#_63
H_DSTBP#_0
H_DSTBP#1
M8
H_DSTBP#_1
H_DSTBP#2
AA6
H_DSTBP#_2
H_DSTBP#3
AE5
H_DSTBP#_3
H_REQ#[4 0]
H_REQ#[4 0]
H_REQ#0
B15
H_REQ#_0
+1.05V_VCCP
H_SWING
H_REQ#1
C5
K13
H_SWING
H_REQ#_1
H_RCOMP
H_REQ#2
E3
F13
H_RCOMP
H_REQ#_2
H_REQ#3
B13
H_REQ#_3
H_REQ#4
C12
B14
H_CPURST#
H_CPURST#
H_REQ#_4
R369
R369
H_RS#[2 0]
E11
H_CPUSLP#
H_RS#[2 0]
H_CPUSLP#
1KR2F-3-GP
1KR2F-3-GP
H_RS#0
B6
H_RS#_0
H_RS#1
F12
H_RS#_1
H_RS#2
A11
C8
H_AVREF
H_RS#_2
H_AVREF
B11
H_DVREF
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
R372
R372
C403
C403
DY
DY
2KR2F-3-GP
2KR2F-3-GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
12
12
12
12
1
2
12
HOST
HOST

D

SCD1U16V2KX-3GP 12 12 12 12 1 2 12 HOST HOST D C B <Core Design> <Core

C

SCD1U16V2KX-3GP 12 12 12 12 1 2 12 HOST HOST D C B <Core Design> <Core

B

SCD1U16V2KX-3GP 12 12 12 12 1 2 12 HOST HOST D C B <Core Design> <Core

<Core Design>

<Core Design>

<Core Design>

A

Title

Title

Title

Design> <Core Design> A Title Title Title Size Size Size Wistron Corporation Wistron Corporation

Size

Size

Size

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Cantiga-HOST(1/6)

Cantiga-HOST(1/6)

Cantiga-HOST(1/6)

Custom

Custom

Custom

Document Number

Document Number

Document Number

Roberts

Roberts

Roberts

Rev

Rev

Rev

-3

-3

-3

Date:

Date:

Date:

Tuesday, August 11, 2009

Tuesday, August 11, 2009

Tuesday, August 11, 2009

Sheet

Sheet

Sheet

8

8

8

of

of

of

59

59

59

D

C

B

A

5

4

3

2

1

U52B U52B 2 2 OF 10 OF 10 SSID = MCH M36 RESERVED#M36 N36 AP24
U52B
U52B
2
2
OF 10
OF 10
SSID = MCH
M36
RESERVED#M36
N36
AP24
M_CLK_DDR0
RESERVED#N36
SA_CK_0
R33
AT21
M_CLK_DDR1
RESERVED#R33
SA_CK_1
T33
AV24
M_CLK_DDR2
RESERVED#T33
SB_CK_0
* is current setting
AH9
AU20
M_CLK_DDR3
RESERVED#AH9
SB_CK_1
AH10
RESERVED#AH10
CFG Strap
Low
High
AH12
AR24
M_CLK_DDR#0
RESERVED#AH12
SA_CK#_0
AH13
AR21
M_CLK_DDR#1
* RESERVED#AH13
SA_CK#_1
CFG 5
DMI X 2
DMI X 4
K12
AU24
M_CLK_DDR#2
RESERVED#K12
SB_CK#_0
AL34
AV20
M_CLK_DDR#3
RESERVED#AL34
SB_CK#_1
+1.8V_SUS
CFG 6
ITPM enable
ITPM disable
AK34
RESERVED#AK34
* AN35
BC28
M_CKE0
RESERVED#AN35
SA_CKE_0
D
TLS cipher suite with
no confidentiality
TLS cipher suite with
confidentiality
* AM35
AY28
M_CKE1
RESERVED#AM35
SA_CKE_1
CFG 7
T24
AY36
M_CKE2
RESERVED#T24
SB_CKE_0
BB36
R380
R380
M_CKE3
SB_CKE_1
PCIE GFX lane
numbered in oder
80D6R2F-L-GP
80D6R2F-L-GP
* B31
RESERVED#B31
+1.8V_SUS
CFG 9
PCIE GFX lane reversed
B2
BA17
M_CS0#
RESERVED#B2
SA_CS#_0
M1
AY16
M_CS1#
RESERVED#M1
SA_CS#_1
AV16
M_CS2#
SB_CS#_0
CFG 10
PCIE loopback enable
PCIE loopback disable
AR13
M_CS3#
SB_CS#_1
* AY21
* RESERVED#AY21
CFG 12
ALLZ mode enable
ALLZ mode disable
R122
R122
BD17
M_ODT0
SA_ODT_0
AY17
R377
R377
1KR2F-3-GP
1KR2F-3-GP
M_ODT1
SA_ODT_1
CFG 13
XOR mode enable
XOR mode disable
80D6R2F-L-GP
80D6R2F-L-GP
BF15
M_ODT2
SB_ODT_0
* BG23
AY13
M_ODT3
RESERVED#BG23
SB_ODT_1
CFG 16
FSB dynamic ODT disable
FSB Dynamic ODT enable
BF23
RESERVED#BF23
M_RCOMPP
SM_RCOMP_VOH
* BH18
BG22
RESERVED#BH18
SM_RCOMP
CFG 19
DMI Lane Reserved
M_RCOMPN
BF18
BH21
RESERVED#BF18
SM_RCOMP#
Normal operation
*
Reverse DMI lanes
C162
C162
SM_RCOMP_VOH
BF28
C159
C159
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
R116
R116
SM_RCOMP_VOH
+1.8V_SUS
CFG 20
PCIE and SDVO are
SM_RCOMP_VOL
+V_DDR_MCH_REF
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
3K01R2F-3-GP
3K01R2F-3-GP
BH28
SM_RCOMP_VOL
SDVO concurrent
Only PCIE or SDVO
is operational
*
AV42
1
DY
DY
2
SM_VREF
with PCIE
operatiing simultaneously
via the PEG port
AR36
SM_PWROK
SM_REXT
BF17
R374R374
1
2
499R2F-2-GP499R2F-2-GP
R142
R142
SM_RCOMP_VOL
SM_REXT
SDVO_CTRLDATA
SDVO interface disable
*
SDVO interface enable
10KR2J-3-GP
10KR2J-3-GP
BC36
SM_DRAMRST#
L_DDC_DATA
LFP disable
*
LFP card present
CLK_MCH_DREFCLK
B38
R145
R145
C151
C151
R119
R119
DY
DY
DPLL_REF_CLK
CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#
10KR2J-3-GP
10KR2J-3-GP
C145
C145
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
1KR2F-3-GP
1KR2F-3-GP
A38
DPLL_REF_CLK#
CLK_MCH_DREFCLK#
DDPC_CTRLDATA
SDVO/iHDMI/DP
*
SDVO/iHDMI/DP
MCH_SSCDREFCLK
E41
SC2D2U10V3KX-1GP
SC2D2U10V3KX-1GP
DPLL_REF_SSCLK
MCH_SSCDREFCLK
MCH_SSCDREFCLK#
F41
interface disabled
interface enabled
DPLL_REF_SSCLK#
MCH_SSCDREFCLK#
RSVD
RSVD
C
NC
NC
CLK_MCH_3GPLL
F43
CFG
CFG
PM
PM
PEG_CLK
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
E43
PEG_CLK#
CLK_MCH_3GPLL#
+3.3V_RUN
DMI_TXN0
AE41
DMI_RXN_0
DMI_TXN0
R104
R104
2K21R2F-GP
DMI_TXN1
1 DY
2K21R2F-GP
CFG11
DY
AE37
DMI_RXN_1
DMI_TXN1
DMI_TXN2
AE47
DMI_RXN_2
DMI_TXN2
R128
R128
2K21R2F-GP
2K21R2F-GP
CFG18
DMI_TXN3
1 DY
DY
AH39
DMI_RXN_3
DMI_TXN3
FSB setting
R117
R117
4K02R2F-GP
4K02R2F-GP
CFG19
DMI_TXP0
1 DY
DY
AE40
DMI_RXP_0
DMI_TXP0
DMI_TXP1
T25
AE38
MCH_CLKSEL0
CFG_0
DMI_RXP_1
DMI_TXP1
R121
R121
4K02R2F-GP
4K02R2F-GP
CFG20
DMI_TXP2
1 DY
DY
R25
AE48
MCH_CLKSEL1
CFG_1
DMI_RXP_2
DMI_TXP2
DMI_TXP3
P25
AH40
MCH_CLKSEL2
CFG_2
DMI_RXP_3
DMI_TXP3
RN20
RN20
CFG3
1 P20
CFG_3
+1.05V_VCCP
+3.3V_RUN
1 PM_EXTTS#0
CFG4
DMI_RXN0
4
TP86TP86
1 P24
AE35
CFG_4
DMI_TXN_0
DMI_RXN0
2 PM_EXTTS#1
TP88TP88
CFG5
DMI_RXN1
3
C25
AE43
CFG_5
DMI_TXN_1
DMI_RXN1
CFG6
DMI_RXN2
N24
AE46
CFG_6
DMI_TXN_2
DMI_RXN2
SRN10KJ-5-GP
SRN10KJ-5-GP
CFG7
DMI_RXN3
M24
AH42
CFG_7
DMI_TXN_3
DMI_RXN3
CFG8
E21
CFG_8
CFG9
DMI_RXP0
C23
AD35
R370
R370
R371
R371
DY
DY
CFG_9
DMI_TXP_0
DMI_RXP0
R383
R383
2K21R2F-GP
2K21R2F-GP
CFG5
CFG10
DMI_RXP1
56R2J-4-GP
56R2J-4-GP
10KR2J-3-GP
10KR2J-3-GP
1 DY
DY
2
C24
AE44
CFG_10
DMI_TXP_1
DMI_RXP1
CFG11
DMI_RXP2
N21
AF46
CFG_11
DMI_TXP_2
DMI_RXP2
R112
R112
2K21R2F-GP
2K21R2F-GP
CFG6
CFG12
DMI_RXP3
1 DY
DY
2
P21
AH43
CFG_12
DMI_TXP_3
DMI_RXP3
CFG13
T21
CFG_13
R111
R111
2K21R2F-GP
2K21R2F-GP
CFG7
CFG14
TSATN#_KBC
1 DY
DY
2
1 R20
TSATN#_KBC
CFG_14
TP84TP84
CFG15
1 M20
CFG_15
R102
R102
2K21R2F-GP
2K21R2F-GP
CFG8
TP85TP85
CFG16
1 DY
DY
2
L21
CFG_16
1 CFG17
TSATN#
DY Q19
Q19
H21
B
DY
CFG_17
R382
R382
4K02R2F-GP
4K02R2F-GP
CFG9
TP87TP87
CFG18
MMBT3904WT1G-GP
MMBT3904WT1G-GP
1 DY
DY
2
P29
CFG_18
CFG19
B
R28
CFG_19
R375
R375
2K21R2F-GP
2K21R2F-GP
CFG10
CFG20
1 DY
DY
2
T28
B33
CFG_20
GFX_VID_0
B32
GFX_VID_1
R101
R101
2K21R2F-GP
2K21R2F-GP
CFG12
1 DY
DY
2
G33
GFX_VID_2
F33
GFX_VID_3
R105
R105
2K21R2F-GP
CFG13
1 DY
DY
2
2K21R2F-GP
R29
E33
PM_SYNC#
PM_SYNC#
GFX_VID_4
B7
H_DPRSTP#
PM_DPRSTP#
R103
R103
2
2K21R2F-GP
2K21R2F-GP
CFG16
1 DY
DY
N33
PM_EXTTS#0
PM_EXT_TS#_0
P32
PM_EXTTS#1
PM_EXT_TS#_1
AT40
C34
PWROK
GFX_VR_EN
RSTIN#
AT11
+1.05V_VCCP
RSTIN#
T20
PM_PWROK
THERMTRIP#
R32
DPRSLPVR
2009/07/27
R126
R126
1KR2F-3-GP
1KR2F-3-GP
AH37
R94
R94
CL_CLK
CL_CLK0
AH36
CL_DATA
CL_DATA0
1
2
BG48
AN36
PLT_RST#
M_PWROK
NC#BG48
CL_PWROK
BF48
AJ35
CL_RST#0
NC#BF48
CL_RST#
100R2J-2-GP
100R2J-2-GP
MCH_CLVREF
BD48
AH34
-3
NC#BD48
CL_VREF
+3.3V_RUN
BC48
NC#BC48
C94
C94
DY
DY
BH47
MCH_CLVREF ~= 0.35V
NC#BH47
SC100P50V2JN-3GP
SC100P50V2JN-3GP
R130
R130
R131
R131
BG47
NC#BG47
499R2F-2-GP
499R2F-2-GP
CLKREQ#_B
BE47
N28
1
2
NC#BE47
DDPC_CTRLCLK
BH46
M28
NC#BH46
DDPC_CTRLDATA
10KR2J-3-GP
10KR2J-3-GP
BF46
G36
NC#BF46
SDVO_CTRLCLK
BG45
E36
1
TP271TP271
NC#BG45
SDVO_CTRLDATA
BH44
K36
H_THRMTRIP#
CLKREQ#_B
NC#BH44
CLKREQ#
BH43
H36
DPRSLPVR
MCH_ICH_SYNC#
NC#BH43
ICH_SYNC#
BH6
NC#BH6
BH5
BG4
NC#BH5
TSATN#
B12
<Core Design>
<Core Design>
<Core Design>
A
NC#BG4
TSATN#
BH3
NC#BH3
BF3
NC#BF3
BH2
Wistron Corporation
Wistron Corporation
Wistron Corporation
NC#BH2
BG2
B28
NC#BG2
HDA_BCLK
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
BE2
B30
NC#BE2
HDA_RST#
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
BG1
B29
NC#BG1
HDA_SDI
BF1
C29
NC#BF1
HDA_SDO
Title
Title
Title
BD1
A28
NC#BD1
HDA_SYNC
BC1
NC#BC1
Cantiga-DMI/CFG(2/6)
Cantiga-DMI/CFG(2/6)
Cantiga-DMI/CFG(2/6)
F1
NC#F1
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A47
NC#A47
Custom
Custom
Custom
Roberts
Roberts
Roberts
-3
-3
-3
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
Date:
Date:
Date:
Tuesday, August 11, 2009
Tuesday, August 11, 2009
Tuesday, August 11, 2009
Sheet
Sheet
Sheet
9
9
9
of
of
of
59
59
59
12
MISC
MISC
GRAPHICS VIDMEHDA
GRAPHICS VIDMEHDA
DDR CLK/ CONTROL/COMPENSATIONCLKDMI
DDR CLK/ CONTROL/COMPENSATIONCLKDMI
12
C175
C175
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
12
12
1
2
12
12
12
E
C
12
12
12
12
12
1
2
12
1
2

5

SSID = MCH

4

3

2

1

M_A_DQ[63 0]
D

C

B

M_A_DQ[63 0] U52D U52D 4 4 OF 10 OF 10 M_B_DQ[63 0] U52E U52E 5
M_A_DQ[63 0]
U52D
U52D
4
4
OF 10
OF 10
M_B_DQ[63 0]
U52E
U52E
5
5
OF 10
OF 10
M_B_DQ[63 0]
M_A_DQ0
M_B_DQ0
AJ38
BD21
AK47
BC16
M_A_BS#0
M_B_BS#0
SA_DQ_0
SA_BS_0
SB_DQ_0
SB_BS_0
D
M_A_DQ1
M_B_DQ1
AJ41
BG18
AH46
BB17
M_A_BS#1
M_B_BS#1
SA_DQ_1
SA_BS_1
SB_DQ_1
SB_BS_1
M_A_DQ2
M_B_DQ2
AN38
AT25
AP47
BB33
M_A_BS#2
M_B_BS#2
SA_DQ_2
SA_BS_2
SB_DQ_2
SB_BS_2
M_A_DQ3
M_B_DQ3
AM38
AP46
SA_DQ_3
SB_DQ_3
M_A_DQ4
M_B_DQ4
AJ36
BB20
AJ46
M_A_RAS#
SA_DQ_4
SA_RAS#
SB_DQ_4
M_A_DQ5
M_B_DQ5
AJ40
BD20
AJ48
AU17
M_A_CAS#
M_B_RAS#
SA_DQ_5
SA_CAS#
SB_DQ_5
SB_RAS#
M_A_DQ6
M_B_DQ6
AM44
AY20
AM48
BG16
M_A_WE#
M_B_CAS#
SA_DQ_6
SA_WE#
SB_DQ_6
SB_CAS#
M_A_DQ7
M_B_DQ7
AM42
AP48
BF14
M_B_WE#
SA_DQ_7
SB_DQ_7
SB_WE#
M_A_DQ8
M_B_DQ8
AN43
AU47
SA_DQ_8
SB_DQ_8
M_A_DQ9
M_B_DQ9
AN44
AU46
SA_DQ_9
SB_DQ_9
M_A_DQ10
M_A_DM[7 0]
M_B_DQ10
AU40
BA48
M_A_DM[7 0]
SA_DQ_10
SB_DQ_10
M_A_DQ11
M_A_DM0
M_B_DQ11
M_B_DM[7 0]
AT38
AM37
AY48
M_B_DM[7 0]
SA_DQ_11
SA_DM_0
SB_DQ_11
M_A_DQ12
M_A_DM1
M_B_DQ12
M_B_DM0
AN41
AT41
AT47
AM47
SA_DQ_12
SA_DM_1
SB_DQ_12
SB_DM_0
M_A_DQ13
M_A_DM2
M_B_DQ13
M_B_DM1
AN39
AY41
AR47
AY47
SA_DQ_13
SA_DM_2
SB_DQ_13
SB_DM_1
M_A_DQ14
M_A_DM3
M_B_DQ14
M_B_DM2
AU44
AU39
BA47
BD40
SA_DQ_14
SA_DM_3
SB_DQ_14
SB_DM_2
M_A_DQ15
M_A_DM4
M_B_DQ15
M_B_DM3
AU42
BB12
BC47
BF35
SA_DQ_15
SA_DM_4
SB_DQ_15
SB_DM_3
M_A_DQ16
M_A_DM5
M_B_DQ16
M_B_DM4
AV39
AY6
BC46
BG11
SA_DQ_16
SA_DM_5
SB_DQ_16
SB_DM_4
M_A_DQ17
M_A_DM6
M_B_DQ17
M_B_DM5
AY44
AT7
BC44
BA3
SA_DQ_17
SA_DM_6
SB_DQ_17
SB_DM_5
M_A_DQ18
M_A_DM7
M_B_DQ18
M_B_DM6
BA40
AJ5
BG43
AP1
SA_DQ_18
SA_DM_7
SB_DQ_18
SB_DM_6
M_A_DQ19
M_A_DQS[7 0]
M_B_DQ19
M_B_DM7
BD43
BF43
AK2
M_A_DQS[7 0]
SA_DQ_19
SB_DQ_19
SB_DM_7
M_A_DQ20
M_A_DQS0
M_B_DQ20
M_B_DQS[7 0]
AV41
AJ44
BE45
M_B_DQS[7 0]
SA_DQ_20
SA_DQS_0
SB_DQ_20
M_A_DQ21
M_A_DQS1
M_B_DQ21
M_B_DQS0
AY43
AT44
BC41
AL47
SA_DQ_21
SA_DQS_1
SB_DQ_21
SB_DQS_0
M_A_DQ22
M_A_DQS2
M_B_DQ22
M_B_DQS1
BB41
BA43
BF40
AV48
SA_DQ_22
SA_DQS_2
SB_DQ_22
SB_DQS_1
M_A_DQ23
M_A_DQS3
M_B_DQ23
M_B_DQS2
BC40
BC37
BF41
BG41
SA_DQ_23
SA_DQS_3
SB_DQ_23
SB_DQS_2
M_A_DQ24
M_A_DQS4
M_B_DQ24
M_B_DQS3
AY37
AW12
BG38
BG37
SA_DQ_24
SA_DQS_4
SB_DQ_24
SB_DQS_3
M_A_DQ25
M_A_DQS5
M_B_DQ25
M_B_DQS4
BD38
BC8
BF38
BH9
SA_DQ_25
SA_DQS_5
SB_DQ_25
SB_DQS_4
M_A_DQ26
M_A_DQS6
M_B_DQ26
M_B_DQS5
AV37
AU8
BH35
BB2
SA_DQ_26
SA_DQS_6
SB_DQ_26
SB_DQS_5
M_A_DQ27
M_A_DQS7
M_A_DQS#[7 0]
M_B_DQ27
M_B_DQS6
AT36
AM7
BG35
AU1
M_A_DQS#[7 0]
SA_DQ_27
SA_DQS_7
SB_DQ_27
SB_DQS_6
M_A_DQ28
M_A_DQS#0
M_B_DQ28
M_B_DQS7
M_B_DQS#[7 0]
AY38
AJ43
BH40
AN6
M_B_DQS#[7 0]
SA_DQ_28
SA_DQS#_0
SB_DQ_28
SB_DQS_7
M_A_DQ29
M_A_DQS#1
M_B_DQ29
M_B_DQS#0
BB38
AT43
BG39
AL46
SA_DQ_29
SA_DQS#_1
SB_DQ_29
SB_DQS#_0
M_A_DQ30
M_A_DQS#2
M_B_DQ30
M_B_DQS#1
AV36
BA44
BG34
AV47
SA_DQ_30
SA_DQS#_2
SB_DQ_30
SB_DQS#_1
C
M_A_DQ31
M_A_DQS#3
M_B_DQ31
M_B_DQS#2
AW36
BD37
BH34
BH41
SA_DQ_31
SA_DQS#_3
SB_DQ_31
SB_DQS#_2
M_A_DQ32
M_A_DQS#4
M_B_DQ32
M_B_DQS#3
BD13
AY12
BH14
BH37
SA_DQ_32
SA_DQS#_4
SB_DQ_32
SB_DQS#_3
M_A_DQ33
M_A_DQS#5
M_B_DQ33
M_B_DQS#4
AU11
BD8
BG12
BG9
SA_DQ_33
SA_DQS#_5
SB_DQ_33
SB_DQS#_4
M_A_DQ34
M_A_DQS#6
M_B_DQ34
M_B_DQS#5
BC11
AU9
BH11
BC2