Encoder Using Case statement

module encoder_using_case(
binary_out , // 4 bit binary Output
encoder_in , // 16-bit Input
enable // Enable or t!e encoder
"#
output $%&'( binary_out #
input enable #
input $1)&'( encoder_in #

reg $%&'( binary_out #

al*ays + (enable or encoder_in"
begin
binary_out , '#
i (enable" begin
case (encoder_in"
16-!'''. & binary_out , 1#
16-!'''4 & binary_out , .#
16-!'''/ & binary_out , %#
16-!''1' & binary_out , 4#
16-!''.' & binary_out , )#
16-!''4' & binary_out , 6#
16-!''/' & binary_out , 0#
16-!'1'' & binary_out , /#
16-!'.'' & binary_out , 1#
16-!'4'' & binary_out , 1'#
16-!'/'' & binary_out , 11#
16-!1''' & binary_out , 1.#
16-!.''' & binary_out , 1%#
16-!4''' & binary_out , 14#
16-!/''' & binary_out , 1)#
endcase
end
end
endmodule
2ecoder Using Case statement
module decoder_using_case (
binary_in , // 4 bit binary input
decoder_out , // 16-bit out
enable // Enable for the decoder
);
input !"#$ binary_in ;
input enable ;
output 1%"#$ decoder_out ;
reg 1%"#$ decoder_out ;
al&ays ' (enable or binary_in)
begin
decoder_out ( #;
if (enable) begin
case (binary_in)
4)h# " decoder_out ( 16)h###1;
4)h1 " decoder_out ( 16)h###*;
4)h* " decoder_out ( 16)h###4;
4)h! " decoder_out ( 16)h###+;
4)h4 " decoder_out ( 16)h##1#;
4)h% " decoder_out ( 16)h##*#;
4)h6 " decoder_out ( 16)h##4#;
4)h, " decoder_out ( 16)h##+#;
4)h+ " decoder_out ( 16)h#1##;
4)h- " decoder_out ( 16)h#*##;
4)h. " decoder_out ( 16)h#4##;
4)h/ " decoder_out ( 16)h#+##;
4)h0 " decoder_out ( 16)h1###;
4)h1 " decoder_out ( 16)h*###;
4)hE " decoder_out ( 16)h4###;
4)h2 " decoder_out ( 16)h+###;
endcase
end
end
endmodule
Multiplexer Using Assign
module mu3_using_assign(
din_# , // 4u3 first input
din_1 , // 4u3 5econd input
sel , // 5elect input
mu3_out // 4u3 output
);
//-----------6nput 7orts---------------
input din_#, din_1, sel ;
//-----------8utput 7orts---------------
output mu3_out;
//------------6nternal 9ariables--------
&ire mu3_out;
//-------------0ode 5tart-----------------
assign mu3_out ( (sel) : din_1 " din_#;
endmodule
Multiplexer Using If
module mu3_using_if(
din_# , // 4u3 first input
din_1 , // 4u3 5econd input
sel , // 5elect input
mu3_out // 4u3 output
);
//-----------6nput 7orts---------------
input din_#, din_1, sel ;
//-----------8utput 7orts---------------
output mu3_out;
//------------6nternal 9ariables--------
reg mu3_out;
//-------------0ode 5tarts ;ere---------
al&ays ' (sel or din_# or din_1)
begin
if (sel (( 1)b#)
mu3_out ( din_#;
else
mu3_out ( din_1 ;
end
endmodule
Multiplexer Using Case
module mu3_using_case(
din_# , // 4u3 first input
din_1 , // 4u3 5econd input
sel , // 5elect input
mu3_out // 4u3 output
);
//-----------6nput 7orts---------------
input din_#, din_1, sel ;
//-----------8utput 7orts---------------
output mu3_out;
//------------6nternal 9ariables--------
reg mu3_out;
//-------------0ode 5tarts ;ere---------
al&ays ' (sel or din_# or din_1)
begin
case(sel )
1)b# " mu3_out ( din_#;
1)b1 " mu3_out ( din_1;
endcase
end
endmodule
D Flip Flop
module dff_async_reset (
data , // 1ata 6nput
cl< , // 0loc< 6nput
reset , // =eset input
> // ? output
);
//-----------6nput 7orts---------------
input data, cl<, reset ;
//-----------8utput 7orts---------------
output >;
//------------6nternal 9ariables--------
reg >;
//-------------0ode 5tarts ;ere---------
al&ays ' ( posedge cl< or negedge reset)
if (@reset)
> A( 1)b#;
else
> A( data;
endmodule
8-bit UP counter
module up_counter (
out , // 8utput of the counter
enable , // enable for counter
cl< , // cloc< 6nput
reset // reset 6nput
);
//----------8utput 7orts--------------
output ,"#$ out;
//------------6nput 7orts--------------
input enable, cl<, reset;
//------------6nternal 9ariables--------
reg ,"#$ out;
//-------------0ode 5tarts ;ere-------
al&ays '(posedge cl<)
begin
if (reset)
out A( +)b# ;
else if (enable)
out A( out B 1;
end
endmodule
8-bit UP-DOWN counter
module up_do&n_counter (
out , // 8utput of the counter
up_do&n , // up_do&n control for counter
cl< , // cloc< input
reset // reset input
);
//----------8utput 7orts--------------
output ,"#$ out;
//------------6nput 7orts--------------
input ,"#$ data;
input up_do&n, cl<, reset;
//------------6nternal 9ariables--------
reg ,"#$ out;
//-------------0ode 5tarts ;ere-------
al&ays '(posedge cl<)
begin
if (reset)
out A( +)b# ;
else if (up_do&n)
out A( out B 1;
else
out A( out - 1;
end
endmodule
2ecade Counter
module decade(>,cl<,reset);
output !"#$>; //4 bit Cector output//
input cl<,reset;
reg !"#$>;
al&ays '(posedge cl<)
begin
if ((reset((1Db1) EE (>A4)b1##1) ) //condition for ma3mimum count E reset//
>(>B1;
else
>(4)b####;
end
endmodule
34U
module alu_8mod(out,a,b,s);
input [8:0]a,b;
input [3:0]s;
output [8:0]out;
reg [8:0]out;
//,flag;
always(s)
begin
!ase(s)
"#b0000: out$a%b; //8&bit addition
"#b000': out$a&b; //8&bit subtra!tion
"#b00'0: out$a(b; //8&bit multipli!ation
"#b00'': out$a/b; //8&bit di)ision
"#b0'00: out$in'*in+; //8&bit modulo di)ision
"#b0'0': out$in',,in+; //8&bit logi!al and
"#b0''0: out$a--b; //8&bit logi!al or
"#b0''': out$.a; //8&bit logi!al negation
"#b'000: out$/a; //8&bit bitwise negation
"#b'00': out$a,b; //8&bit bitwise and
"#b'0'0: out$a-b; //8&bit bitwise or
"#b'0'': out$a0b; //8&bit bitwise 1or
"#b''00: out$a22'; //left s3ift
"#b''0': out$a44'; //rig3t s3ift
"#b'''0: out$a%'; //in!rement
"#b'''': out$a&'; //de!rement
end!ase
end
endmodule
Cloc5 6enerator Using 3l*ays
Cloc5 6enerator Using 7ore8er()'9 2uty Cycle"
module foreCer_e3ample ();
reg cl<;
initial
begin
cl< ( #;
foreCer
F% cl< ( @cl<;
initial
F1## Gfinish;
endmodule
Cloc5 6enerator Using 7ore8er(.)9 2uty Cycle"
module foreCer_e3ample ();
reg cl<;
initial
begin
cl< ( #;
foreCer
begin
F1% cl< ( @cl<;
F% cl<(@cl<;
end
end
initial
F1## Gfinish;
endmodule
4 Bit Ripple Carry Adder in Verilog
Structural Model : 4 Bit Ripple Carry Adder
module ripple_adder_4bit(
output !"#$ 5um,
output 0out,
input !"#$ .,/,
input 0in
);
&ire c1,c*,c!;
full_adder 2.1(5um#$,c1,.#$,/#$,0in),
2.*(5um1$,c*,.1$,/1$,c1),
2.!(5um*$,c!,.*$,/*$,c*),
2.4(5um!$,0out,.!$,/!$,c!);
endmodule
Structural Model : Full Adder
module full_adder(
output 5,0out,
input .,/,0in
);
&ire s1,c1,c*;
half_adder ;.1(s1,c1,.,/);
half_adder ;.*(5,c*,s1,0in);
or 8H1(0out,c1,c*);
endmodule
Structural Model : Half Adder
module half_adder(
output 5,0,
input .,/
);
3or(5,.,/);
and(0,.,/);
endmodule