Cortex-M4

Dariusz Chaberski
STM32 Cortex-M4 implementation
2
Processor core registers
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APSR, IPSR, EPSR and PSR bit assignments
ICI - Interruptible-continuable instructions (LDM, STM, PUSH, POP, VLDM, VSTM, VPUSH, VPOP)
IT - If-Then block
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Load and Store Multiple instructions
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Condition Flags - Example
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Memory map
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Bit-band mapping
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Exception model
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Vector table
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Cortex-M4 stack frame layout
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Condition code suxes
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Condition code suxes - continued
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Instruction width selection
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Basic structure of a ve-volt tolerant I/O port bit
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Port bit conguration table
GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF =
alternate function
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Port bit conguration table
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DMA block diagram
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Channel selection
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EXTI block diagram
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Single ADC block diagram
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Single ADC block diagram
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Timing diagram
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Data alignment of 12-bit data
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Left alignment of 6-bit data
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Multi ADC block diagram
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Multi ADC block diagram
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DAC channel block diagram
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Noise generation
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DAC conversion (SW trigger enabled) with triangle wave
generation
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Digital camera interface
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DCMI signal waveforms
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Advanced-control timers (TIM1&TIM8)
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Addressing Mode 1 - Data-processing operands
l <opcode>{<cond>}{S} <Rd>, <Rn>, <shifter_operand>
#<immediate>
immed_8 == 0x3F, rotate_imm == 0xE
immed_8 == 0xFC, rotate_imm == 0xF
<Rm>
<Rm>, LSL #<shift_imm>
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Addressing Mode 1 - Data-processing operands
l <opcode>{<cond>}{S} <Rd>, <Rn>, <shifter_operand>
<Rm>, LSL <Rs>
<Rm>, LSR #<shift_imm>
<Rm>, LSR <Rs>
<Rm>, ASR #<shift_imm>
<Rm>, ASR <Rs>
<Rm>, ROR #<shift_imm>
<Rm>, ROR <Rs>
<Rm>, RRX
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Addressing Mode 2 - Load and Store Word or Unsigned Byte
l LDR|STR{<cond>}{B}{T} <Rd>, <addressing_mode>
[<Rn>, #+/-<oset_12>]
[<Rn>, +/-<Rm>]
[<Rn>, +/-<Rm>, <shift> #<shift_imm>]
[<Rn>, +/-<Rm>, LSL #<shift_imm>]
[<Rn>, +/-<Rm>, LSR #<shift_imm>]
[<Rn>, +/-<Rm>, ASR #<shift_imm>]
[<Rn>, +/-<Rm>, ROR #<shift_imm>]
[<Rn>, +/-<Rm>, RRX]
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Addressing Mode 2 - Load and Store Word or Unsigned Byte
l LDR|STR{<cond>}{B}{T} <Rd>, <addressing_mode>
[<Rn>, #+/-<oset_12>]!
[<Rn>, +/-<Rm>]!
[<Rn>, +/-<Rm>, <shift> #<shift_imm>]!
[<Rn>], #+/-<oset_12>
[<Rn>], +/-<Rm>
[<Rn>], +/-<Rm>, <shift> #<shift_imm>
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Addressing Mode 3 - Miscellaneous Loads and Stores
l LDR|STR{<cond>}H|SH|SB|D <Rd>, <addressing_mode>
[<Rn>, #+/-<oset_8>]
[<Rn>, +/-<Rm>]
[<Rn>, #+/-<oset_8>]!
[<Rn>, +/-<Rm>]!
[<Rn>], #+/-<oset_8>
[<Rn>], +/-<Rm>
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Addressing Mode 4 - Load and Store Multiple
l LDM|STM{<cond>}<addressing_mode> <Rn>{!}, <registers>{^}
IA (Increment After)
IB (Increment Before)
DA (Decrement After)
DB (Decrement Before)
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Addressing Mode 5 - Load and Store Coprocessor
l <opcode>{<cond>}{L} <coproc>,<CRd>,<addressing_mode>
[<Rn>,#+/-<oset_8>*4]
[<Rn>,#+/-<oset_8>*4]!
[<Rn>],#+/-<oset_8>*4
[<Rn>],<option>
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ARM Instructions
ADC{<cond>}{S} <Rd>, <Rn>, <shifter_operand>
ADDS R4,R0,R2
ADCS R5,R1,R3
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ARM Instructions
AND{<cond>}{S} <Rd>, <Rn>, <shifter_operand>
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ARM Instructions
B{L}{<cond>} <target_address>
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ARM Instructions
BIC{<cond>}{S} <Rd>, <Rn>, <shifter_operand>
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ARM Instructions
BLX <target_addr>
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ARM Instructions
BLX{<cond>} <Rm>
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ARM Instructions
CDP{<cond>} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>, <opcode_2>
CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>, <opcode_2>
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ARM Instructions
CLZ{<cond>} <Rd>, <Rm>
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ARM Instructions
LDC{<cond>}{L} <coproc>, <CRd>, <addressing_mode>
LDC2{L} <coproc>, <CRd>, <addressing_mode>
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ARM Instructions
MLA{<cond>}{S} <Rd>, <Rm>, <Rs>, <Rn>
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ARM Instructions
QADD{<cond>} <Rd>, <Rm>, <Rn>
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Thumb Instructions
ADC <Rd>, <Rm>
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Thumb Instructions
Rd = Rn + immed_3
Rd = Rd + immed_8
Rd = Rn + Rm
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Thumb Instructions
Rd = Rd + Rm
Rd = (PC AND 0xFFFFFFFC) + (immed_8 * 4)
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Thumb Instructions
Rd = SP + (immed_8 < < 2)
SP = SP + (immed_7 < < 2)
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Thumb Instructions
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