HINDUSTHAN INSTITUTE OF TECHNOLOGY, COIMBATORE 32

DEPARTMENT OF ECE
Internal Assessent I ! FEB 2"#$
%I SEMESTER &B'E ECE(
EC23)$!%LSI DESIGN
DATE* TIME* #'3" HOURS MA+'MAR,S* )"
PART A #" - 2 . 2"
ANS/ER ALL 0UESTIONS

1. What is the objective of layout design rule? Mention its types.
2. What are the different regions that can be defined in nMOS
depending upon the voltages applied?
3. What is meant by channel length modulation and rite don the
e!uation hich describes the channel length modulation.
". #efine $hreshold voltage in %MOS?
&. #ra the circuit and layout diagram for nMOS inverter.
'. #efine noise margin.
(. What is meant by body effect?
). Mention the advantage and disadvantage of SO*..
+. Give some of the important CAD tools.
1,. #ra the symbol of nMOS and pMOS.
PART! B 2- #). 3"
11. a- i- #ra and e.plain the #% and transfer characteristics of a
%MOS inverter ith necessary conditions for the different
regions of operation. /(-
ii- 0.plain layout design rule. /)-
&OR(
b- 0.plain different steps involved in n1ell %MOS fabrication
process ith neat diagram. /1&-
12. a- i- #rive the e!uation for drain to source current for different
region. /(-
ii- With necessary e!uation e.plain %2 characteristics. /)-
&OR(
b- With neat s3etch e.plain the or3ing principle of nMOS transistor.
/1&-