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Date:24-10-2009

Veda IIT VLSI Physical /Logical Design Exam Pattern:

Exam contains 4 sections .

Digital Design— 30 Marks

Microprocessor - 10 Marks

Programming - 30 Marks

Aptitude --- 30 Marks

Digital Design:

Most of the questions came from flip flops.

I remember some questions.

1.To design 16:1 MUX, howmany 2:1 multiplexers are required.

2. Write the output function for the following diagram y=__


C

~c
Y=?

~c

A0 A1

3.Which type of MOD counter we can use for generate 2 high pulse and one
low pulse

4.

1. Develop JK flipflop using D-flip flop.


2. Draw the circuit of Y=(A xor B) OR C, using 2:1 MUX
Some questions asked out flow of according to circuit and clock.

Microprocessor:

1.Using 8086 processor how much address space you can access ,how many bytes
of input and output space you can address.

2.In 8086 micro processor for DMA access signals is used ______ and __________

3.How can you interface 2 MB RAM to 8086 processor? Write your approach?

4.What is cache memory?what is technology used in making Cache memory?

5.virtual memory

6.In VGA,you are having two 16 bit addressable spaces.how can you access those
two spaces?

Questions came from 8086 Micro Processor, In this they ask what is cache memory?
And its functionality and what is inside cache ram means development
technology .and also asked virtual memory.They asked memory addressing type
questions .

Programming:

In this Section all questions are from C language. They ask answers and
explanations also.

1. Without using semicolon Print the following message “ HI welcome to veda iit