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• 4 Accumulator
Register(s)
Accumulates bits swapped
in and out of the ALU.
• 5 Shifter
Stores, carries and rotates
results
CPU Architecture
• 6 Program Counter
Register
Contains the address of the next
instruction to be fetched and executed.
The program counter is then
incremented and the next processing
cycle begins.
• 7 Stack Pointer
Register
Keeps track of the STACK.
• Control Path
• responsible for instruction fetch and
execution sequencing
• responsible for operand fetch
• responsible for saving results
CPU Architecture
• 8 STACK • The Processing Cycle
Register(s) (simplified)
• The Stack is not part of the CPU it
is part of memory. • Fetch the next instruction
• The pull operation results in a
transfer of the word at the top of • Decode instruction
the stack into the accumulator.
• The push operation puts a word on
• Execute instruction
the stack. The final accumulator
contents are deposited on top of the
• Increment counter
stack.
• The Stack Pointer keeps track of
what’s next on the stack. First word
at the bottom.
Instruction Cycle
Fetching
Execution
CPU
Fetch Cycle
Address Line
Data Line
PC
PC++ Memory
IR MBR
Address Line
Data Line
IR Memory
A MBR
Basic Instruction Cycle (contd.)
Begin
Begin
Fetch Cycle
Fetch
FetchNext
Next
Instruction
Instruction
Execute
Execute
Instruction
Instruction
Execute Cycle
Layout of bits in an instruction
Includes opcode
Operand
◦ Shorter instructions
◦ Faster instruction fetch
Instruction Register
Register Data
Direct Addressing
Address field contains address of operand(Data)
In this addressing data required for instruction
Instruction Memory
Address Data
Register Indirect Addressing
In this addressing data required for instruction is in
memory location whose EA is in register pair which is
specified in the instruction.
i.e. Register pair indirectly points to the data in the
memory.
Large address space (2n)
One fewer memory access than indirect addressing
+ Data
Base Address
Implicit Addressing
Accumulator
Data