Uniwill M31ei1 - 37GM31000-B0

5
M31EI1
D
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
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37
COVER PAGE
SYSTEM BLOCK DIAGRAM
POWER DIADRAM & SEQUENCE
GPIO & POWER CONSU
ICS 9LPR310-CLK GEN.
YONAH_CPU 1 of 2
YONAH_CPU 2 of 2
Calistoga 1/6 HOST BUS
Calistoga 2/6 DDR,VGA,PCI-E
Calistoga 3/6 DDR_System&Terminator
Calistoga 4/6 Power pin
Calistoga 6/6 Gnd & Power TP
DDR2 SODIMM
Internal/Extenal VGA Switch
ICH7M 1/4 RTC,SATA,IDE,CPU
ICH7M 2/4 PCI-E,PCI,USB
ICH7M 3/4 GPIO,MGT
ICH7M 4/4 Power pin
LCD/INVERTOR
GIGA-LAN
IEEE-1394,Mini_card,SATA,HOL
CD-ROM/PCMCIA/IO/LAN/USB
Smart_power
CRT / AUDIO CONN
IT8510E &K/B&BIOS & TP & FAN
DC IN/BATT IN/Charger
+V3.3V +V5V +V12A
1.5V/1.05V/1.8V/0.9V/2.5VS
CPU CORE
Voltage SW
ADD&CHANGE NOTICE
M31EI1
VER: B
P/N:37GM31000-B0
MADE IN TAIWAN
UNIWILL COMPUTER CORP.

Title
COVER PAGE
Size
Document Number
Date:
SCHEMATIC1
Tuesday, January 17, 2006
Rev
B
M31EI1
Sheet
1
of
32
JM20330
BLOCK DIAGRAM
CPU
THERMAL
ADM1032
Yonah
Socket 478
EC
HOST BUS
Daughter BD1
400/533/667MHz
DDR2 RAM BUS
CRT
North Bridge
LCD
Calistoga
SODIMM1
SODIMM0
+1.8V_DDR
+0.9V_DDR terminal
+1.8V_DDR
+0.9V_DDR terminal
S-Video TV
945GM
Daughter BD6
PCI-E 16X
1466FCBGA
External VGA
Card
DMI
Daughter BD2
AZALIA
PCI BUS
CRYSTAL
24.576MHz
South Bridge
PCI-E
AUDIO CODEC
MDC
ICH7-M
ALC880
AMPLIFIER
TPA6011A4
SATA
HDD
2.5"
RJ11
INTERNAL MIC
+5V
Daughter BD5
SATA1
SATA0
MASTER
INTERNAL
SPK
LINE IN *1
MIC IN *1
SPDIF OUT *1
CONN
TSB43AB22A
Daughter BD6
JM20330
PCIEx1
LAN
BCM5787
USB*1
PATA
RJ45
B
PATA
CRYSTAL
NEW
CARD
USB*1
USB*1
USB*1
Daughter BD5
Daughter BD6
USB*1
CRT Docking
Daughter BD4
B
DVD
ROM
2.5"
PCIEx1
+5V
LPC BUS
+5V
MASTER
MINI
CARD
USB*1
CARD
Reader
GL817E-07
25M HZ
PHDD
PCIEx1
14.318MHz
IEEE1394
PCMCIA
OZ601T
USB*8
Daughter BD3
Daughter BD4
CRYSTAL
RTC
652BGA
PRIMARY
MASTER
( Wireless )
ICS
Clock Gen
CRYSTAL
9LPR310
K/B CONTROLLER
ITE 8510
32.768K Hz
LOW POWER
X-BUS
FLASH ROM
INT K/B
T/P
FAN
BATTERY
CHARGER

Title
SYSTEM BLOCK DIAGRAM

Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
of
32
POWER BLOCK DIAGRAM

D
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VIN
ISL 6261
POWER ON SEQUENCE
RSS090N03
RQA200N03
+VCC_CORE/30A
+V5
+V3.3
PM_PWRBTN#
VIN
+V5A/5A
100ms
2.1us
123ms
3.8ms
+5VS/5A
+V12S
2.5us
+V1.8_DDR
2.5ms
+1.5V
RSS090N03
18ms
RSS090N03
PM_RSMRST#
98ms
PM_SLP_S4#
+5V
AOS3414L
30.5us
PM_SLP_S3#
+5V_ON
33.3ms
+V12S
4ms
+12VA/100mA
ISL6232
+V5S
4.8ms
+V2.5S
C
0.06ms
+V0.9
+12VS
AOS3414L
0.51ms
21.4ms
VTTPWRGD#
+5V_ON
+V3.3S
4.3ms
VIN
+V1.5S
+V3.3A/5A
+V3.3S/3A
+V12S
3.8ms
+V2.5S/0.6A
+V1.05S
13ms
Vcore_ON
RSS090N03
RSS090N03
RT9173B
0.55ms
+VCC_Core
7.6ms
+V3.3 0.9A
VR_PWRGD
211ms
H_PWRGD
AOS3413L
1.05ms
PLT_RST#
6.4us
+3.3V_ON
PCI_RST#
1ms
H_CPURST#
B
VIN
+V1.5S/6A
RSS090N03
ISL6227
+1.5VS/4A
RSS090N03
+1.5VS_ON
+1.5V_ON
VIN +V1.8_DDR/7A
A
ISL6227
RSS090N03
+0.9VS/1A
RT9173B
+1.8VS/3A
RSS090N03
Title
POWER DIAGRAM & SEQUENCE
+1.8VS_ON
5
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
of
32
ICH7-M
GPIO0
GPIO6
GPIO7
GPIO9
GPIO10
GPIO11
GPIO12
GPIO16
GPIO18
GPIO19
GPIO20
GPIO21
GPIO26
GPIO27
GPIO28
GPIO32
GPIO36
GPIO37
GPIO49
GPIO
PM_BMBUSY#
EC_EXTSMI#
EC_SCI#
LCDSEL0
LCDSEL1
SMB_ALERT#
LCDSEL2
PM_DPRSLPVR
PM_STPPCI#
SATA0_R1
PM_STPCPU#
SATA0_R0
LED_R
LED_G
LED_B
PM_CLKRUN#
SATA0_R2
SATA0_R3
H_PWRGD
ITE8510E
GPCF0
GPCF1
GPCF2
GPCF3
GPCF4
GPCF5
GPCF6
GPCF7
GPI0
GPI1
GPI2
GPI3
GPI4
GPI5
GPI6
GPH0
GPH1
GPH2
GPH3
GPH4
GPH5
GPH6
GPH7
GPG4
GPG5
GPG6
GPG7
GPB0
GPB1
GPB2
GPB3
GPB4
GPB5
GPB6
GPB7
GPE0
GPE1
GPE2
GPE3
GPE4
GPE5
GPE6
GPE7
GPD0
GPD1
GPD2
GPD3
GPD4
GPD5
GPD6
GPD7
GPA0
GPA1
GPA2
GPA3
GPA4
GPA5
GPA6
GPA7
YONAH CPU
ITE8510E
GPIO
GPC0
GPC1
GPC2
GPC3
GPC4
GPC5
GPC6
GPC7
ADC8
ADC9
ADC0
ADC1
ADC2
ADC3
AC_BATT
PM_SYSRST#
CHG_G#
TP_BT
TP_CLK
TP_DATA
NC
INSTANT_EC
SCROLED#
CAPLED#
NUMLED#
CHG_R#
+5V_ON
SILENT_LED#
PWR_LED#
+1.8V_DDR_ON
RF_LED_ON#
MXM VO-DET
+3.3V_ON
NC
+1.05VS_ON
+1.5V_ON
VCORE_ON
DK_MXM_THERM#
LCDSW
AMP_MUTE#
+1.8VS_ON
CELERON_VO_DET
USB_P0_ON#
+3.3VS_ON
SMBCLK0
SMBDAT0
EC_HA20GATE
EC_HRCIN#
+5VS_ON
VR_THERM#
CPU_BSEL0_EC
GND
MXM_PCIE_DET#
PWRSW_EC
LID#
RF_OFF#
PM_SLP_S3#
ADAP_IN
SILNET_EC
PLT_RST#
EC_EXTSMI#_A
PM_SLP_S4#
LED_R
LED_G
LED_B
BTL_BEEP
EC_VID1
EC_VID2
EC_VID3
EC_VID4
SMP1_EN#
SMP2_EN#
PM_PWRBTN#
GPIO
600MHZ
VCC_MCH_VRPWRGD
SMBCLK1
SMBDAT1
PWR_keep
MINI_RFON
PM_RSMRST#
CHG_ON
USB5VA_ON
NC
NC
BATT_TEMP
ADAP_I
GND
GND
CPU CORE(V)ICC(A)
27
27
27
27
27
27
27
27
W
24.7
TEMP()
69
70
70
71
72
72
72
74
ITE8510E
ICC(mA)
300mA
VCC
+3.3V
W
0.99
TEMP()
70
CLOCK GENERATOR
VCC
+3.3V
ICC(mA)
400mA
W
1.32
TEMP()
115
ALC880
VCC
ICC(mA) W
TEMP()
125
+3.3V(DVDD)
35mA 0.116
+5VS(AVDD)
65mA 0.325
Calistoga
ICC(mA)
VCC
+3.3VS
160mA
+2.5VS
<200mA
+1.5VS
3.6A
+1.05VS
4.6A
+1.8V_DDR 3.1A
W
528mW
0.5W
5.4W
4.83W
5.58W
TEMP()
TPA6011A4
VCC
+5V_AMP
ICC(mA)
50mA
VCC
+3.3V
TEMP()
W
30mW
50mW
172mW
70
1.089W
ICC
170uA
ICC(mA)
1.5A
3A
500mA
500mA
4A
W
4.95W
5.4W
2.5W
1.25W
ICC(mA)
300mA
1A
500mA
W
0.99
3.3W
0.75W
OZ601T
ICC(mA)
1.5A
1A
<100mA
VCC
+3.3VS
+5VS
+12VS
VCC
+3.3V
+2.5V
+1.2V
ICC(mA)
4mA
218mA
426mA
VCC
+3.3VS
ICC(mA)
1.5A
TEMP()
150
W
4.95W
5W
1.2W
TEMP()
150
C
TEMP()
W
13.2mW
150
545mW
511mW
LCD Panel
TEMP()
150
W
10W
SATA/ODD
Mini Card
VCC
+3.3VA
+3.3V
+1.5V
W
TEMP()
150
0.56mW
Giga LAN(Marvell)
2.67W
0.93W
MXM NVIDIA
VCC
+3.3VS
+1.8VS
+5VS
+2.5VS
VIN
TEMP()
150
ADM1032
70
ICH7-M
VCC
ICC(mA)
+5V
6mA
+5VS
10mA
+3.3V
52mA
+3.3VS
330mA
+3.3VA_RTC
N/A
+1.5VS
1.78A
+1.05VS
860mA
W
0.25
VCC
+5VS
ICC(mA)
1A/1.5A
VCC
+5VS
ICC(mA)
2A
VCC
+3.3VS
ICC(mA)
100mA
TEMP()
150
W
TEMP()
150
5/7.5W
USB x3
W
TEMP()
150
IEEE1394
W
330mW
TEMP()
150
PCI Interrupt
request
ID_SEL
PCMCIA
PCI_AD20
INT_PIRQA#
1394
PCI_AD26
INT_PIRQC#
PCI_REQ#1 / PCI_GNT#1
PCI_REQ#0 / PCI_GNT#0
LCD Panel ID select
PNLSW0
ICH-7M
GPIO9
PNLSW1
ICH-7M
GPIO10

Title
PNLSW2
5
ICH-7M
GPIO & Power Consumption
GPIO12
3
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
of
32
+V3.3S
C633
0.1u/10V
X7R
2*CL - ( Cs + Ci )
CL =
Crystal Load Cap = 20P
Ci =
IC internal Cap = 5P
Cs =
2P
Ce =
Crystal external Cap = 33P
C630
C620
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
QT1608RL060HC_3A_0603
23 PCI_CLK_PCMCIA
26 PCI_CLK_LPC
18 CLK_REF_ICH7
26 SMBDAT_GEN
26 SMBCLK_GEN
R152
R154
PCICLK3
PCI2
PCICLK2_2X
22
PCI1
PCICLK1_2X
R129
22
PCI0
64
PCICLK0_2X
R136
22
R572
R574
22
22
PCIF1
PCIF0
22
22
CLK_MCH_QE#
CPPE2#
22 MINICARD_REQ#
MINICARDpin7
9
8
FLSC
FLSB
FLSA
61
60
12
FLSC/REF1
FLSB/REF0
FLSA/USB_48M_2X
55
54
SDATA
SCLK
17
18
LCD_SSCGT/PCIEXOT
LCD_SSCGC/PCIEXOC
SATACLK
SATACLK#
26
27
SATACLKT
SATACLKC
*0
R181
R578
0
*0
33
32
34
16
45
46
PCI/PCIEX_STOP#
CPU_STOP#
63
62
R575
R576
0
0
CPUCLKT1
CPUCLKC1
49
48
CPU1
CPU#1
R155
R159
22
22
CPUCLKT0
CPUCLKC0
52
51
CPU0
CPU#0
R151
R153
22
22
PCIEXT1
PCIEXC1
19
20
PCIEXT1
PCIEXC1#
R157
R161
22
22
PCIEXT2
PCIEXC2
22
23
PCIEXT2
PCIEXC2#
R163
R165
22
22
PCIEXT3
PCIEXC3
24
25
PCIEXT3
PCIEXC3#
R169
R175
22
22
PCIEXT4
PCIEXC4
30
31
PCIEXT5
PCIEXC5
36
35
PCIEXT5
PCIEXC5#
R170
R176
22
22
PCIEXT6
PCIEXC6
39
38
PCIEXT6
PCIEXC6#
R164
R168
*22
*22
PCIEXT7
PCIEXC7
41
40
modify 10/06
Y3
X2_OUT
X1_IN
47
VREF
14.318MHz_SMD
R162 9LPR310-CLK
modify 10/17
modify 10/17
C147
C149
27p/50V
NPO
27p/50V
NPO
C599
0.1u/10V
X7R
PM_STPPCI# 18
PM_STPCPU# 18
CLK_MCH_BCLK 8
CLK_MCH_BCLK# 8
CLK_CPU_BCLK 6
CLK_CPU_BCLK# 6
PCIE_CLK_MINI_CARD 22
PCIE_CLK_MINI_CARD# 22
GCLK
GCLK#
9
9
PCIE_CLK_ICH 17
PCIE_CLK_ICH# 17
C
PCIE_CLK_LAN 21
PCIE_CLK_LAN# 21
TP143
TP144
+V3.3S
PCIEXT8
PCIEXC8
44
43
DOTT_96M
DOTC_96M
14
15
DOT96
DOT96#
VTT_PWRGD#/PD
10
VTT_PWRGD#
DEL R184
CLK_MCH_QE#
R617
11
56
VDDA
GNDA
PEREQ4#
PEREQ3#
PEREQ2#
PEREQ1#
57
58
L14
4.7u/10V_0805
Y5V
PCIEXT0
PCIEXC0#
R582
VDD48
VDDREF
SELDOT/ PCICLK_F1
PCICLK_F0
22
22
22
22
R178
R183
16 CLK_PCIE_SATA
16 CLK_PCIE_SATA#
PCI3
22
0
0
DREFSSCLK
DREFSSCLK#
VDDPCI1
22
R128
Descret VGA,SMBUS
9
9
VDDCPU
R133
R140
R142
18 USB_CLK_48M
26 LPC_CLK_48M
R141
R144
50
0.1u/10V
X7R
C138
R143
R150
22
22
R577
10K
Descret VGA,SMBUS
DREFCLK 9
DREFCLK# 9
VTT_PWRGD# 30
GND
GND
GND
GND
GND
GND
GND
GND
modify 09/15
C
TP569
10K
0.1u/10V
X7R
4.7u/10V_0805
Y5V
2
6
13
21
29
37
53
59
R139
VDDPCIEX
VDDPCIEX
R134
10K
17 PCI_CLK_ICH7
28
42
C615
C132
0.1u/10V
X7R
22 PCICLK_1394
R138
C613
26 CLK_PCI_LPC
+V3.3S
4.7u/10V_0805
Y5V
C618
U8
BIOS need modified

driven from 2X-->1X
C134
VDDPCI0
Ce =
C626
*4.3K_1%
*10K
modify 09/23
PCI-Express
Mini Card
PCIF1
0
PEREQ1#
PEREQ2#
FSLC FSLB FSLA

BSEL2 BSEL1 BSEL0
CPU
MHZ
PCI
MHZ
PCI
MHZ
Spread %
133
33.33
100.0
0.5% Down
166
33.33
100.0
0.5% Down
100
33.33
100.0
0.5% Down
PEREQ3#
R137
PEREQ4#
*10K
+V3.3S
00=PSB400(BSEL1=0)
01=PSB533(BSEL0=1)
+V3.3S
00=PSB400(BSEL1=0)
01=PSB533(BSEL0=1)
R132
+V3.3S
*10K
R131
+V3.3S
FLSB
R333
*10K
D
*4.7K
C
*1K
01=PSB400(BSEL0=1)
Q71
*2N7002
*4.7K
G
00=PSB533(BSEL1=0)
Q74
*2N3904
R332
CLK_BSEL1
R330
00=PSB533(BSEL1=0)
6
FLSC
Q73
*2N7002
01=PSB400(BSEL0=1)
CLK_BSEL2
R331
*1K
Q72
*2N3904
B
E
R135
2.2K
Title
R130
2.2K
ICS 9LPR310-CLK GEN.
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
of
32
+V1.05S
H_A#[31:3]
H_ADSTB#1
H_A20M#
H_FERR#
H_IGNNE#
A6
A5
C4
A20M#
FERR#
IGNNE#
16
16
16
16
H_STPCLK#
H_INTR
H_NMI
H_SMI#
D5
C6
B4
A3
STPCLK#
LINT0
LINT1
SMI#
AA1
AA4
AB2
AA3
M4
N5
T2
V3
B2
C3
RSVD{01}
RSVD{02}
RSVD{03}
RSVD{04}
RSVD{05}
RSVD{06}
RSVD{07}
RSVD{08}
RSVD{09}
RSVD{10}
TP_A32#
TP_A33#
TP_A34#
TP_A35#
TP_A36#
TP_A37#
TP_A38#
TP_A39#
TP_APM0#
TP_APM1#
TP117
TP116
TP122
TP118
TP106
TP108
TP114
TP115
TP65
TP79
TP_HFPLL
TP64
B25
ADDR GROUP 1
8
16
16
16
Layout note: on
stubon
H_STPCLKTP
CONTROL
H5
F21
E1
H_DEFER# 8
H_DRDY# 8
H_DBSY# 8
F1
H_BREQ#0 8
IERR#
INIT#
D20
B3
LOCK#
H4
RESET#
RS{0}#
RS{1}#
RS{2}#
TRDY#
B1
F3
F4
G3
G2
HIT#
HITM#
G6
E4
+V1.05S
H_D#[63:0] 8
R47
54.9_1%
H_INIT#
H_D#[63:0]
U504-2
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
56
E22
F24
E26
H22
F23
G25
E25
E23
K24
G24
J24
J23
H26
F26
K22
H25
H23
G22
J26
D{0}#
D{1}#
D{2}#
D{3}#
D{4}#
D{5}#
D{6}#
D{7}#
D{8}#
D{9}#
D{10}#
D{11}#
D{12}#
D{13}#
D{14}#
D{15}#
DSTBN{0}#
DSTBP{0}#
DINV{0}#
H_DSTBN#1
H_DSTBP#1
H_DINV#1
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
M24
N25
M26
D{16}#
D{17}#
D{18}#
D{19}#
D{20}#
D{21}#
D{22}#
D{23}#
D{24}#
D{25}#
D{26}#
D{27}#
D{28}#
D{29}#
D{30}#
D{31}#
DSTBN{1}#
DSTBP{1}#
DINV{1}#
GTLREF
AD26
Place testpoint on
H_IERR# with a GND
0.1"away
IERR#
16
H_LOCK# 8
H_RS#[2:0]
H_CPURST# 8 H_RS#0
H_RS#1
H_RS#2
H_TRDY# 8
H_HIT#
H_HITM#
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
BPM#5
TCK
TDI
TDO
TMS
TRST#
DBRESET#
PROCHOT#
THERMDA
THERMDC
D21
A24
A25
PROCHOT#
H_THERMDA
H_THERMDC
BCLK{0}
BCLK{1}
R61
BPM{0}#
BPM{1}#
BPM{2}#
BPM{3}#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
THERMTRIP#
8
8
8
8
8
TP127
TP128
TP126
TP125
TP124
TP542
TP541
TP119
TP123
TP120
TP121
TP78
A22
A21
8
8
8
8
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#[63:0]
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
R46
75
+V1.05S
PM_THRMTRIP# Should
PM_THRMTRIP# 9,16
connect to ICH7 and GMCH
without T-ing (no stub)
PM_THRMTRIP#
C7
+V1.05S
R85
1K_1%
8
8
8
CLK_CPU_BCLK 5
CLK_CPU_BCLK# 5
DATA GRP 2
A{17}#
A{18}#
A{19}#
A{20}#
A{21}#
A{22}#
A{23}#
A{24}#
A{25}#
A{26}#
A{27}#
A{28}#
A{29}#
A{30}#
A{31}#
ADSTB{1}#
Y2
U5
R3
W6
U4
Y5
U2
R4
T5
T3
W3
W5
Y4
W2
Y1
V4
H_ADS#
H_BNR#
H_BPRI#
DATA GRP 1
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
REQ{0}#
REQ{1}#
REQ{2}#
REQ{3}#
REQ{4}#
BR0#
H1
E2
G5
DATA GRP 3
H_A#[31:3]
K3
H2
K2
J3
L5
XDP/ITP SIGNALS
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
THERM
H_REQ#[4:0]
DEFER#
DRDY#
DBSY#
H CLK
H_ADSTB#0
ADS#
BNR#
BPRI#
A{3}#
A{4}#
A{5}#
A{6}#
A{7}#
A{8}#
A{9}#
A{10}#
A{11}#
A{12}#
A{13}#
A{14}#
A{15}#
A{16}#
ADSTB{0}#
DATA GRP 0
J4
L4
M3
K5
M1
N2
J1
N3
P5
P2
L1
P4
P1
R1
L2
ADDR GROUP 0
U504-1
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
GTLREF
R86
RSVD{12}
RESERVED
RSVD{11}
RSVD{13}
RSVD{14}
RSVD{15}
RSVD{16}
RSVD{17}
RSVD{18}
RSVD{19}
RSVD{20}
T22 TP_EXTBREF
D2
F6
D3
C1
AF1
D22
C23
C24
TP113
TP_SPARE0
TP_SPARE1
TP_SPARE2
TP_SPARE3
TP_SPARE4
TP_SPARE5
TP_SPARE6
TP_SPARE7
TP88
TP95
TP89
TP80
TP129
TP90
TP86
TP72
Layout note:
Zo=55ohm,
0.5"max for
GTLREF
2K_1%
R328
*IK
C26
TEST1
R329
51
D25
TEST2
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
B22
B23
C21
MISC
BSEL{0}
BSEL{1}
BSEL{2}
D{32}#
D{33}#
D{34}#
D{35}#
D{36}#
D{37}#
D{38}#
D{39}#
D{40}#
D{41}#
D{42}#
D{43}#
D{44}#
D{45}#
D{46}#
D{47}#
DSTBN{2}#
DSTBP{2}#
DINV{2}#
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
W24
Y25
V23
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
D{48}#
D{49}#
D{50}#
D{51}#
D{52}#
D{53}#
D{54}#
D{55}#
D{56}#
D{57}#
D{58}#
D{59}#
D{60}#
D{61}#
D{62}#
D{63}#
DSTBN{3}#
DSTBP{3}#
DINV{3}#
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
AD23
AE24
AC20
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP{0}
COMP{1}
COMP{2}
COMP{3}
R26
U26
U1
V1
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PS1#
E5
B5
D24
D6
D7
AE6
H_DSTBN#2 8
H_DSTBP#2 8
H_DINV#2 8
H_D#[63:0]
COMP(3:0) Traces should be at least

25mils away from any other toggling
single.
COMP(0,2) trace used of 18-mil wide
dog bones
Layout note :
Comp0,2 connect with
trace length shorter
Comp1,3 connect with
trace length shorter
Zo=27.4ohm make
than 0.5"
Zo=55ohm make
than 0.5"
H_DSTBN#3 8
H_DSTBP#3 8
H_DINV#3 8
COMP0
COMP1
COMP2
COMP3
R537
R538
R78
R79
27.4_1%
54.9_1%
27.4_1%
54.9_1%
+V1.05S
R56
H_DPRSTP# 16,30
H_DPSLP# 16
*1k
H_DPWR# 8
H_PWRGD 16
H_CPUSLP# 8,16
Layout:connect test point

with no stub
Place series resistor on
H_PWRGD_XDP without stub
I17665457
PSI#
TP565
I17665937
A#[32-39],AMP#[0-1] Leave
escape rputing on for
future functionality
+V1.05S
+VCC_CORE
54.9_1%
TDI
R539
54.9_1%
BPM#5
R547
54.9_1%
R45
9,16 PM_THRMTRIP#
AUX_OFF# 28,31
R55
R549
54.9_1%
TRST#
R81
54.9_1%
100K
Q10
B
1k
TCK
R548
2N3904
Q8
C23
TMS
B
C37
E
2N3904
1u/10V_0603
Y5V
0.1u/10V
X7R
+V3.3S R517
200
+V1.05S
C511
CPU
Thermal
+V1.05S
2200p/50V
X7R
H_THERMDC
R43
R41
+V3.3S
470
D+
THERM#
D-
GND
C514
R42
VDD
U502
H_THERMDA
+V1.05S
Sensor
0.1u/10V
X7R
ADATA
CPU_THER_SMBDAT0 26
SCLK
CPU_THER_SMBCLK0 26
ALERT
R513
26
10K
CPU_BSEL2
CPU_BSEL2 R50
R40
ADM1032
470
*0
CLK_BSEL2 5
R37
26
CPU_BSEL1
CPU_BSEL1 R48
R38
CLK_BSEL1 5
*0
470
CPU_BSEL0
R49
R39
*0
R35
1K_1%
R36
1K_1%
1K_1%
MCH_BSEL2 9
MCH_BSEL1 9
MCH_BSEL0 9

Title
YONAH_CPU 1 of 2
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
of
32
+VCC_CORE
+VCC_CORE
U504-4
A4
A8
A11
A14
A16
A19
A23
A26
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
U504-3
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
VCC001
VCC002
VCC003
VCC004
VCC005
VCC006
VCC007
VCC008
VCC009
VCC010
VCC011
VCC012
VCC013
VCC014
VCC015
VCC016
VCC017
VCC018
VCC019
VCC020
VCC021
VCC022
VCC023
VCC024
VCC025
VCC026
VCC027
VCC028
VCC029
VCC030
VCC031
VCC032
VCC033
VCC034
VCC035
VCC036
VCC037
VCC038
VCC039
VCC040
VCC041
VCC042
VCC043
VCC044
VCC045
VCC046
VCC047
VCC048
VCC049
VCC050
VCC051
VCC052
VCC053
VCC054
VCC055
VCC056
VCC057
VCC058
VCC059
VCC060
VCC061
VCC062
VCC063
VCC064
VCC065
VCC066
VCC067
VCC068
VCC069
VCC070
VCC071
VCC072
VCC073
VCC074
VCC075
VCC076
VCC077
VCC078
VCC079
VCC080
VCC081
VCC082
VCC083
VCC084
VCC085
VCC086
VCC087
VCC088
VCC089
VCC090
VCC091
VCC092
VCC093
VCC094
VCC095
VCC096
VCC097
VCC098
VCC099
VCC100
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
VCCP01
VCCP02
VCCP03
VCCP04
VCCP05
VCCP06
VCCP07
VCCP08
VCCP09
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
V6
G21
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
VCCA
B26
VID0
VID1
VID2
VID3
VID4
VID5
VID6
AD6
AF5
AE5
AF4
AE3
AF2
AE2
VCCSENSE
AF7
VCC_SENSE 30
VSSSENSE
AE7
VSS_SENSE 30
+V1.05S
C541
4.7u/10V_0805
Y5V
+V1.5S
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
C54
24
24
24
24
24
24
24
0.01u/16V
X7R
C52
modify 10/13
4.7u/10V_0805
Y5V
del R88,R89
PLACE NEAR
PIN B26
ROUTE VCCSENSE AND VSSSENSE

TRACES AT 27.4 OHMS AND 50 mil
spacing, place pu and pd
within 1 inch of cpu
I17668219
VSS001
VSS002
VSS003
VSS004
VSS005
VSS006
VSS007
VSS008
VSS009
VSS010
VSS011
VSS012
VSS013
VSS014
VSS015
VSS016
VSS017
VSS018
VSS019
VSS020
VSS021
VSS022
VSS023
VSS024
VSS025
VSS026
VSS027
VSS028
VSS029
VSS030
VSS031
VSS032
VSS033
VSS034
VSS035
VSS036
VSS037
VSS038
VSS039
VSS040
VSS041
VSS042
VSS043
VSS044
VSS045
VSS046
VSS047
VSS048
VSS049
VSS050
VSS051
VSS052
VSS053
VSS054
VSS055
VSS056
VSS057
VSS058
VSS059
VSS060
VSS061
VSS062
VSS063
VSS064
VSS065
VSS066
VSS067
VSS068
VSS069
VSS070
VSS071
VSS072
VSS073
VSS074
VSS075
VSS076
VSS077
VSS078
VSS079
VSS080
VSS081
VSS082
VSS083
VSS084
VSS085
VSS086
VSS087
VSS088
VSS089
VSS090
VSS091
VSS092
VSS093
VSS094
VSS095
VSS096
VSS097
VSS098
VSS099
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
AF3
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF24
I17668007
B
+VCC_CORE
+ C533
+ C85
4.7u/10V_0805
Y5V
+ C542
+ C84
4.7u/10V_0805
Y5V
+ C69
4.7u/10V_0805
Y5V
+ C77
4.7u/10V_0805
Y5V
+ C540
4.7u/10V_0805
Y5V
+ C86
4.7u/10V_0805
Y5V
+ C75
4.7u/10V_0805
Y5V
+ C87
4.7u/10V_0805
Y5V
+ C68
4.7u/10V_0805
Y5V
4.7u/10V_0805
Y5V
+ C76
4.7u/10V_0805
Y5V
4.7u/10V_0805
Y5V
C539
C534
C38
C47
C74
C45
C40
1u/10V_0603
Y5V
1u/10V_0603
Y5V
1u/10V_0603
Y5V
1u/10V_0603
Y5V
1u/10V_0603
Y5V
1u/10V_0603
Y5V
1u/10V_0603
Y5V
C42
C46
C48
C49
C41
C39
C99
1u/10V_0603
Y5V
1u/10V_0603
Y5V
1u/10V_0603
Y5V
1u/10V_0603
Y5V
1u/10V_0603
Y5V
1u/10V_0603
Y5V
1u/10V_0603
Y5V
+VCCP
+V1.05S
C83
C88
C80
C73
C67
C89
C82
C78
C70
C66
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
+ C526
4.7u/10V_0805
Y5V
+ C527
4.7u/10V_0805
Y5V
+ C532
+ C535
4.7u/10V_0805
Y5V
4.7u/10V_0805
Y5V
C90
C91
C105
C92
C100
C59
C56
C60
C63
C55
1000p/50V 1000p/50V 1000p/50V 1000p/50V 1000p/50V 1000p/50V 1000p/50V 1000p/50V 1000p/50V 1000p/50V
X7R
X7R
X7R
X7R
X7R
X7R
X7R
X7R
X7R
X7R

Title
YONAH_CPU 2 of 2
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
of
32
H_XRCOMP
H_D#[63:0]
+V1.05S
R519
54.9_1%
H_XSCOMP
+V1.05S
R33
221_1%
H_XSWING
C15
0.1u/10V
X7R
R32
C
100_1%
+V1.05S
R523
54.9_1%
H_YSCOMP
+V1.05S
U503A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
F1
J1
H1
J6
H3
K2
G1
G2
K9
K1
K7
J8
H4
J3
K11
G4
T10
W11
T3
U7
U9
U11
T11
W9
T1
T8
T4
W7
U5
T9
W6
T5
AB7
AA9
W4
W3
Y3
Y7
W5
Y10
AB8
W2
AA4
AA7
AA2
AA6
AA10
Y8
AA1
AB4
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5
AD10
AD4
AC8
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
R524
221_1%
H_XRCOMP
H_XSCOMP
H_XSWING
E1
E2
E4
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
Y1
U1
W1
H_YRCOMP
H_YSCOMP
H_YSWING
H_YSWING
B
C520
R525
100_1%
0.1u/10V
X7R
AG2
AG1
5 CLK_MCH_BCLK
5 CLK_MCH_BCLK#
H_CLKIN
H_CLKIN#
HOST
R516
24.9_1%
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_VREF
H_BNR#
H_BPRI#
H_BREQ#0
H_CPURST#
H_DBSY#
H_DEFER#
H_DPWR#
H_DRDY#
H_VREF
E8
B9
C13
J13
C6
F6
C7
B7
A7
C3
J9
H8
K13
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#[31:3] 6
+V1.05S
R26
H_ADS# 6
H_ADSTB#0 6
H_ADSTB#1 6
100_1%
H_VREF
H_BNR# 6
H_BPRI# 6
H_BREQ#0 6
H_CPURST# 6
H_DBSY# 6
H_DEFER# 6
H_DPWR# 6
H_DRDY# 6
C29
J7
W8
U3
AB10
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DINV#[3:0]
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
K4
T7
Y5
AC4
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBN#[3:0] 6
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
K3
T6
AA5
AC5
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_DSTBP#[3:0] 6
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_HIT#
H_HITM#
H_LOCK#
D3
D4
B3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
D8
G8
B8
F8
A8
H_RS#_0
H_RS#_1
H_RS#_2
B4
E6
D6
H_SLPCPU#
H_TRDY#
E3
E7
R30
0.1u/10V
X7R
200_1%
C
H_HIT#
6
H_HITM# 6
H_LOCK# 6
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_REQ#[4:0] 6
H_RS#0
H_RS#1
H_RS#2
H_RS#[2:0] 6
H_CPUSLP# 6,16
H_TRDY# 6
H_YRCOMP
CALISTOGA
R526
24.9_1%

Title
Calistoga 1/6 HOST BUS
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
of
32
+V1.5S_PCIE
U503C
TP42
modify 10/06
18 PM_BMBUSY#
0 PM_EXTTS#0
0 PM_EXTTS#1
R320
R10
R65
17,18,21,22,26 PLT_RST#
100
TP568
H28
H27
K28
H32
del CLK_MCH_QE# net

modify 10/06
D1
C41
C1
BA41
BA40
BA39
BA3
BA2
BA1
B41
B2
AY41
AY1
AW41
AW1
A40
A4
A39
A3
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
MUXING
AW35
AT1
AY7
AY40
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
SM_CKE_0
SM_CKE_1
SM_CKE_2
SM_CKE_3
AU20
AT20
BA29
AY29
M_CKE0
M_CKE1
M_CKE2
M_CKE3
10,14
10,14
10,14
10,14
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
AW13
AW12
AY21
AW21
M_CS#0
M_CS#1
M_CS#2
M_CS#3
10,14
10,14
10,14
10,14
SM_OCDCOMP_0
SM_OCDCOMP_1
AL20
AF10
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
BA13
BA12
AY20
AU21
SM_RCOMP#
SM_RCOMP
AV9
AT9
SM_VREF_0
SM_VREF_1
AK1
AK41
EN_BL
20
L_DDC_CLK
20 L_DDC_DATA
TP506
14
14
14
14
20
TPM_OCDCOMP0
TPM_OCDCOMP1
G_CLKIN#
G_CLKIN
D_REFCLKIN#
D_REFCLKIN
D_REFSSCLKIN#
D_REFSSCLKIN
L_IBG
1.5K_1%
R502
EN_LCD
TPM_OCDCOMP0
D32
J30
H30
H29
G26
G25
B38
C35
F32
C33
C32
L_BKLTCTL
L_BKLTEN
L_CLKCTLA
L_CLKCTLB
L_DDC_CLK
L_DDC_DATA
L_IBG
L_VBG
L_VDDEN
L_VREFH
L_VREFL
15
15
15
15
LA_CLKN
LA_CLKP
LB_CLKN
LB_CLKP
A33
A32
E27
E26
LA_CLK#
LA_CLK
LB_CLK#
LB_CLK
15
15
15
LA_DATAN0
LA_DATAN1
LA_DATAN2
C37
B35
A37
LA_DATA#_0
LA_DATA#_1
LA_DATA#_2
15
15
15
LA_DATAP0
LA_DATAP1
LA_DATAP2
B37
B34
A36
LA_DATA_0
LA_DATA_1
LA_DATA_2
15
15
15
LB_DATAN0
LB_DATAN1
LB_DATAN2
G30
D30
F29
LB_DATA#_0
LB_DATA#_1
LB_DATA#_2
15
15
15
LB_DATAP0
LB_DATAP1
LB_DATAP2
F30
D29
F28
LB_DATA_0
LB_DATA_1
LB_DATA_2
A16
C18
A19
TV_DACA_OUT
TV_DACB_OUT
TV_DACC_OUT
TPM_OCDCOMP1
M_ODT0
M_ODT1
M_ODT2
M_ODT3
10,14
10,14
10,14
10,14
+V1.8_DDR
R64
M_RCOMP#
M_RCOMP
R533
R68
40.2_1%
40.2_1%
150_1%
M_VREF_MCH
AF33
AG33
A27
A26
C40
D41
150_1%
GCLK#
5
GCLK
5
DREFCLK# 5
DREFCLK 5
DREFSSCLK# 5
DREFSSCLK 5
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
AE35
AF39
AG35
AH39
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
AC35
AE39
AF35
AG39
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
AE37
AF41
AG37
AH41
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
AC37
AE41
AF37
AG41
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
TV_DACA
15
15
TV_Y_DACB
TV_C_DACC
R16
DMI_TXN[3:0] 17
R508
R506
R505
modify 10/03
4.99K_1% J20
B16
B18
B19
*150_1%
*150_1%
150_1%
TP37
TP38
DMI_TXP[3:0] 17
TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC
K30
J29
TV_DCONSEL0
TV_DCONSEL1
E23
D23
C22
B22
A21
B21
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
C26
C25
G23
J22
H23
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_IREF
CRT_VSYNC
modify 10/03
15
CRT_BLUE
15
CRT_GREEN
15
CRT_RED
DMI_RXN[3:0] 17
R511
*150_1%
R510
*150_1%
R509
*150_1%
25 CRT_DDC_CLK
25 CRT_DDC_DATA
15 CRT_HSYNC
DMI_RXP[3:0] 17
15
R14
R25
R13
CRT_VSYNC
39
255_1%
39
VGA
TP_MCH_NC0
TP_MCH_NC1
TP_MCH_NC2
TP_MCH_NC3
TP_MCH_NC4
TP_MCH_NC5
TP_MCH_NC6
TP_MCH_NC7
TP_MCH_NC8
TP_MCH_NC9
TP_MCH_NC10
TP_MCH_NC11
TP_MCH_NC12
TP_MCH_NC13
TP_MCH_NC14
TP_MCH_NC15
TP_MCH_NC16
TP_MCH_NC17
TP_MCH_NC18
SDVO_CTRLCLK
SDVO_CTRLDATA
LT_RESET#
CLK_REQ#
NC
TP514
TP516
TP511
TP536
TP538
TP537
TP540
TP539
TP535
TP513
TP502
TP534
TP533
TP532
TP531
TP508
TP510
TP507
TP503
PM_BMBUSY#
PM_EXTTS#_0
PM_EXTTS#_1
PM_THRMTRIP#
PWROK
RSTIN#
MISC
TP566
TP567
17 MCH_ICH_SYNC#
G28
F25
H26
G6
AH33
AH34
SM_CK#_0
SM_CK#_1
SM_CK#_2
SM_CK#_3
14
14
14
14
TV
14 PM_EXTTS#0_DDR
18,30 PM_DPRSLPVR
6,16 PM_THRMTRIP#
18 DELAY_VR_PWRGOOD
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
R532
PM
AY35
AR1
AW7
AW40
PCI-EXPRESS
TP10
TP44
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
DDR
TP12
K16
K18
J18
F18
E15
F15
E18
D19
D16
G16
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J26
CFG
MCH_CFG_3
MCH_CFG_4
MCH_CFG_5
MCH_CFG_6
MCH_CFG_7
MCH_CFG_8
MCH_CFG_9
MCH_CFG_10
MCH_CFG_11
MCH_CFG_12
MCH_CFG_13
MCH_CFG_14
MCH_CFG_15
MCH_CFG_16
MCH_CFG_17
MCH_CFG_18
MCH_CFG_19
MCH_CFG_20
TP17
TP14
CLK
MCH_BSEL0
MCH_BSEL1
MCH_BSEL2
20
SM_CK_0
SM_CK_1
SM_CK_2
SM_CK_3
LVDS
6
6
6
RSVD_1
RSVD_2
RSVD_3
RSVD_4
RSVD_5
RSVD_6
RSVD_7
RSVD_8
RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
DMI
T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A35
A34
D28
D27
RSVD
MCH_RSVD_1
MCH_RSVD_2
MCH_RSVD_3
MCH_RSVD_4
MCH_RSVD_5
MCH_RSVD_6
MCH_RSVD_7
MCH_RSVD_8
MCH_RSVD_9
MCH_RSVD_10
MCH_RSVD_11
MCH_RSVD_12
MCH_RSVD_13
TP75
TP55
TP25
TP36
TP102
TP98
TP39
TP43
TP509
TP505
TP504
TP11
TP16
GRAPHICS
U503B
PEG_COMP
EXP_A_COMPI
EXP_A_COMPO
D40
D38
EXP_A_RXN_0
EXP_A_RXN_1
EXP_A_RXN_2
EXP_A_RXN_3
EXP_A_RXN_4
EXP_A_RXN_5
EXP_A_RXN_6
EXP_A_RXN_7
EXP_A_RXN_8
EXP_A_RXN_9
EXP_A_RXN_10
EXP_A_RXN_11
EXP_A_RXN_12
EXP_A_RXN_13
EXP_A_RXN_14
EXP_A_RXN_15
F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
EXP_A_RXP_0
EXP_A_RXP_1
EXP_A_RXP_2
EXP_A_RXP_3
EXP_A_RXP_4
EXP_A_RXP_5
EXP_A_RXP_6
EXP_A_RXP_7
EXP_A_RXP_8
EXP_A_RXP_9
EXP_A_RXP_10
EXP_A_RXP_11
EXP_A_RXP_12
EXP_A_RXP_13
EXP_A_RXP_14
EXP_A_RXP_15
D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
EXP_A_TXN_0
EXP_A_TXN_1
EXP_A_TXN_2
EXP_A_TXN_3
EXP_A_TXN_4
EXP_A_TXN_5
EXP_A_TXN_6
EXP_A_TXN_7
EXP_A_TXN_8
EXP_A_TXN_9
EXP_A_TXN_10
EXP_A_TXN_11
EXP_A_TXN_12
EXP_A_TXN_13
EXP_A_TXN_14
EXP_A_TXN_15
F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
EXP_A_TXP_0
EXP_A_TXP_1
EXP_A_TXP_2
EXP_A_TXP_3
EXP_A_TXP_4
EXP_A_TXP_5
EXP_A_TXP_6
EXP_A_TXP_7
EXP_A_TXP_8
EXP_A_TXP_9
EXP_A_TXP_10
EXP_A_TXP_11
EXP_A_TXP_12
EXP_A_TXP_13
EXP_A_TXP_14
EXP_A_TXP_15
D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
R520
24.9_1%
TP24
TP18
TP30
TP28
TP40
TP47
TP50
TP54
TP56
TP59
TP66
TP73
TP77
TP93
TP96
TP100
TP20
TP19
TP26
TP29
TP32
TP35
TP48
TP53
TP57
TP62
TP67
TP69
TP76
TP84
TP85
TP101
TP13
TP518
TP23
TP34
TP41
TP527
TP45
TP51
TP68
TP530
TP60
TP71
TP74
TP92
TP97
TP99
TP15
TP22
TP21
TP521
TP27
TP33
TP49
TP46
TP58
TP529
TP61
TP63
TP70
TP83
TP82
TP91
CALISTOGA
CALISTOGA
MCH_CFG_5
+V3.3S
MCH_CFG_9
+V3.3S
LOW= DMI*2
R503
High= DMI*4
*2.2K
MCH_CFG_5
MCH_CFG_9
LOW= Reverse Lane
PCIE Graphics
Lane
High= Normal
Operation
MCH_CFG_18
LOW= 1.05V
VCC Select
High= 1.5V
R19
2.2K
R11
*1K
MCH_CFG_19
DMI LANE
Reversed
MCH_CFG_18
MCH_CFG_10
MCH_CFG_6
+V3.3S
80.6_1%
LOW= Moby Dick
R17
High= Calistoga
*2.2K
MCH_CFG_6
R77
R12
10K
PM_EXTTS#0
R29
10K
PM_EXTTS#1
MCH_CFG_10
HOST PLL VDD
Select
LOW= Resvred
High= Mobility
R18
*2.2K
MCH_CFG_16
FSB Dynamic
ODT
LOW= Disabled
R15
High= Enabled
*2.2K
M_RCOMP#
M_RCOMP
*1K
MCH_CFG_19
MCH_CFG_16
+V1.8_DDR
R23
LOW= Normal
High= LANES
Reversed
modify 10/06
MCH_CFG_20
LOW= only SDVO or PCIE

x1 is operation
(defaults)
PCIE Backward
Interpoerability
Mode
High= SDVO and PCIE x1

are operating
simultaneously via PEG
port
+V3.3S
R24
*1K
R76
MCH_CFG_7
80.6_1%
MCH_CFG_11
MCH_CFG_20
MCH_CFG_12
MCH_CFG_7
CPU Strap
LOW=RSVD
High= MOBILE CPU
MCH_CFG_11
PSB 4x CLK
Enable
R507
*2.2K
LOW= Calistoga
High= Resvred
R504
R20
*2.2K
*2.2K
MCH_CFG_13
R21
*2.2K

Title
Calistoga 2/6 DDR,VGA,PCI-E
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
of
32
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
SA_BS_0
SA_BS_1
SA_BS_2
AU12
AV14
BA20
SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
AY13
AJ33
AM35
AL26
AN22
AM14
AL9
AR3
AH4
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS[7:0] 14
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
AK33
AT33
AN28
AM22
AN12
AN8
AP3
AG5
AK32
AU33
AN27
AM21
AM12
AL8
AN3
AH5
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A[13:0] 14
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
AY16
AU14
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
AW14
AK23
AK24
AY14
M_A_DQ[63:0]
DDR SYSTEM MEMORY
14
M_B_DQ[63:0]
M_A_BS0 14
M_A_BS1 14
M_A_BS2 14
M_A_CAS# 14
M_A_DM[7:0] 14
M_A_DQS#[7:0] 14
M_A_RAS# 14
TP105
TP103
M_A_WE# 14
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AK39
AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
DDR SYSTEM MEMORY B
U503H
14
U503D
SB_BS_0
SB_BS_1
SB_BS_2
AT24
AV23
AY28
SB_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
AR24
AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
AM39
AT39
AU35
AR29
AR16
AR10
AR7
AN5
AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS[7:0] 14
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
AY23
AW24
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27
AY27
AR23
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A[13:0] 14
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#
AU23
AK16
AK18
AR27
M_B_BS0 14
M_B_BS1 14
M_B_BS2 14
M_B_CAS# 14
M_B_DM[7:0] 14
M_B_DQS#[7:0] 14
M_B_RAS# 14
TP104
TP107
M_B_WE# 14
CALISTOGA
CALISTOGA
modify 08/12
+V0.9
1200mA
+V0.9
C550
0.1u/10V
X7R
C93
0.1u/10V
X7R
C94
0.1u/10V
X7R
C95
0.1u/10V
X7R
C97
0.1u/10V
X7R
C98
0.1u/10V
X7R
C123
0.1u/10V
X7R
C96
0.1u/10V
X7R
C574
0.1u/10V
X7R
C575
0.1u/10V
X7R
C568
0.1u/10V
X7R
14
14
14
14
M_B_BS1
M_B_A0
M_B_A2
M_B_A4
14
14
14
14
M_B_A8
M_B_A5
M_B_A3
M_B_A1
14
14
14
14
M_A_A8
M_A_A5
M_A_A3
M_A_A1
9,14
9,14
9,14
9,14
M_ODT3
M_CS#3
M_ODT1
M_CS#1
9,14
14
14
14
M_CKE2
M_B_BS2
M_B_A12
M_B_A9
14
14
14
14
M_A_A10
M_A_BS0
M_A_WE#
M_A_CAS#
9,14
14
14
14
M_CKE0
M_A_BS2
M_A_A12
M_A_A9
C122
0.1u/10V
X7R
C572
C119
C109
C573
C125
C547
C545
C546
C548
C557
C124
C549
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
Layout note: Place one cap close to every 2 pullup resistors terminated to DDR_VREF
RP506
4
3
2
1
8P4RX56R
5
6
7
8
RP503
4
3
2
1
RP7
M_A_A8
4
M_A_A5
3
M_A_A3
2
M_A_A1
1
RP9
M_ODT3
1
M_CS#3
2
M_ODT1
3
M_CS#1
4
RP504
M_CKE2
4
M_B_BS2
3
M_B_A12
2
M_B_A9
1
RP8
M_A_A10
4
M_A_BS0
3
M_A_WE#
2
M_A_CAS# 1
RP6
M_CKE0
4
M_A_BS2
3
M_A_A12
2
M_A_A9
1
8P4RX56R
5
6
7
8
8P4RX56R
5
6
7
8
8P4RX56R
8
7
6
5
8P4RX56R
5
6
7
8
8P4RX56R
5
6
7
8
8P4RX56R
5
6
7
8
M_B_BS1
M_B_A0
M_B_A2
M_B_A4
M_B_A8
M_B_A5
M_B_A3
M_B_A1
14
14
14
9,14
M_B_A6
M_B_A7
M_B_A11
M_CKE3
14
14
14
14
M_B_A10
M_B_BS0
M_B_WE#
M_B_CAS#
14
14
14
9,14
M_A_A6
M_A_A7
M_A_A11
M_CKE1
14
M_A_A13
9,14 M_ODT0
9,14 M_CS#0
14
M_A_RAS#
14
14
14
14
M_A_BS1
M_A_A0
M_A_A2
M_A_A4
14
9,14
9,14
14
M_B_A13
M_ODT2
M_CS#2
M_B_RAS#
RP507
4
3
2
1
RP502
M_B_A10 4
M_B_BS0 3
M_B_WE# 2
M_B_CAS# 1
RP3
M_A_A6
4
M_A_A7
3
M_A_A11 2
M_CKE1 1
RP5
M_A_A13 4
M_ODT0 3
M_CS#0 2
M_A_RAS# 1
RP4
M_A_BS1 4
M_A_A0
3
M_A_A2
2
M_A_A4
1
RP505
M_B_A13 4
M_ODT2 3
M_CS#2 2
M_B_RAS# 1
M_B_A6
M_B_A7
M_B_A11
M_CKE3
8P4RX56R
5
6
7
8
8P4RX56R
5
6
7
8
8P4RX56R
5
6
7
8
8P4RX56R
5
6
7
8
8P4RX56R
5
6
7
8
8P4RX56R
5
6
7
8

Title
Calistoga 3/6 DDR_System&Termination
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
10
of
32
+V1.05S
U503E
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
VCC_95
VCC_96
VCC_97
VCC_98
VCC_99
VCC_100
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
VCC_110
VCC
VCC_SM_0
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_SM_37
VCC_SM_38
VCC_SM_39
VCC_SM_40
VCC_SM_41
VCC_SM_42
VCC_SM_43
VCC_SM_44
VCC_SM_45
VCC_SM_46
VCC_SM_47
VCC_SM_48
VCC_SM_49
VCC_SM_50
VCC_SM_51
VCC_SM_52
VCC_SM_53
VCC_SM_54
VCC_SM_55
VCC_SM_56
VCC_SM_57
VCC_SM_58
VCC_SM_59
VCC_SM_60
VCC_SM_61
VCC_SM_62
VCC_SM_63
VCC_SM_64
VCC_SM_65
VCC_SM_66
VCC_SM_67
VCC_SM_68
VCC_SM_69
VCC_SM_70
VCC_SM_71
VCC_SM_72
VCC_SM_73
VCC_SM_74
VCC_SM_75
VCC_SM_76
VCC_SM_77
VCC_SM_78
VCC_SM_79
VCC_SM_80
VCC_SM_81
VCC_SM_82
VCC_SM_83
VCC_SM_84
VCC_SM_85
VCC_SM_86
VCC_SM_87
VCC_SM_88
VCC_SM_89
VCC_SM_90
VCC_SM_91
VCC_SM_92
VCC_SM_93
VCC_SM_94
VCC_SM_95
VCC_SM_96
VCC_SM_97
VCC_SM_98
VCC_SM_99
VCC_SM_100
VCC_SM_101
VCC_SM_102
VCC_SM_103
VCC_SM_104
VCC_SM_105
VCC_SM_106
VCC_SM_107
AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6
AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1
C531
C536
0.1u/10V
X7R
0.1u/10V
X7R
+V1.05S
2500mA
C35 +
X5R
C26 +
X5R
U503F
C516+
*22u/6.3V_0805
AA33
W33
P33
N33
L33
J33
AA32
Y32
W32
V32
P32
N32
M32
L32
J32
AA31
W31
V31
T31
R31
P31
N31
M31
AA30
Y30
W30
V30
U30
T30
R30
P30
N30
M30
L30
AA29
Y29
W29
V29
U29
R29
P29
M29
L29
AB28
AA28
Y28
V28
U28
T28
R28
P28
N28
M28
L28
P27
N27
M27
L27
P26
N26
L26
N25
M25
L25
P24
N24
M24
AB23
AA23
Y23
P23
N23
M23
L23
AC22
AB22
Y22
W22
P22
N22
M22
L22
AC21
AA21
W21
N21
M21
L21
AC20
AB20
Y20
W20
P20
N20
M20
L20
AB19
AA19
Y19
N19
M19
L19
N18
M18
L18
P17
N17
M17
N16
M16
L16
*22u/6.3V_0805
2900mA
4.7u/10V_0805
Y5V
C515+
4.7u/10V_0805
Y5V
C61
C58
1u/10V_0603 0.1u/10V
Y5V
X7R
C81
0.1u/10V
X7R
C44
C27
0.1u/10V
X7R
0.1u/10V
X7R
AD27
AC27
AB27
AA27
Y27
W27
V27
U27
T27
R27
AD26
AC26
AB26
AA26
Y26
W26
V26
U26
T26
R26
AD25
AC25
AB25
AA25
Y25
W25
V25
U25
T25
R25
AD24
AC24
AB24
AA24
Y24
W24
V24
U24
T24
R24
AD23
V23
U23
T23
R23
AD22
V22
U22
T22
R22
AD21
V21
U21
T21
R21
AD20
V20
U20
T20
R20
AD19
V19
U19
T19
AD18
AC18
AB18
AA18
Y18
W18
V18
U18
T18
VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72
VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17
VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57
AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15
+V1.5S_NB
NCTF
2000mA
CALISTOGA
+V1.8_DDR
3100mA
C543
C538+
4.7u/10V_0805
Y5V
C544+
4.7u/10V_0805
Y5V
0.1u/10V
X7R
C537
C530
CALISTOGA
0.1u/10V
X7R
0.1u/10V
X7R

Title
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
11
of
32
CAPS USED IN
+V3.3S_TVDAC should
be within 250mils of
edge of MCH
+V3.3S
500mA
L502
QT1608RL060HC_3A_0603
+V1.5S
0.1uf CAPS IN
+V1.5SXPLL need to
be located as edge
caps within
200mils
+V1.5S
D
200mA
10
D500
A
+V1.5S_DPLLA
L3
QT1608RL060HC_3A_0603
C17
4.7u/10V_0805
Y5V
0.1u/10V
X7R
C4
C16
0.1u/10V
X7R
22n/16V
X7R
+V2.5S
BAT54
+V3.3S_TVDACB
C28
120mA
40mA
C11
+V3.3S_TVDACA
120mA
R9
C506
C8
0.1u/10V
X7R
22n/16V
X7R
+V1.5S_DPLLB
L504
QT1608RL060HC_3A_0603
+V1.5S_PCIE
+V3.3S_TVDACC
120mA
40mA
C509
C510
4.7u/10V_0805
Y5V
0.1u/10V
X7R
C14
C19
0.1u/10V
X7R
22n/16V
X7R
+V1.5S_3GPLL
+V2.5S
+V1.5S_HPLL
L508
QT1608RL060HC_3A_0603
45mA
C529
C528
1u/10V_0603
Y5V
0.1u/10V
X7R
C18
C524
1u/10V_0603
Y5V
0.1u/10V
X7R
4.7u/10V_0805
Y5V
C21
0.1u/10V
X7R
45mA
C525
C64
0.1u/10V
X7R
H22
VCCSYNC
C30
B30
A30
VCC_TXLVDS0
VCC_TXLVDS1
VCC_TXLVDS2
AJ41
AB41
Y41
V41
R41
N41
L41
AC33
G41
H41
+V2.5S_CRTDAC
+V1.5S_MPLL
L507
QT1608RL060HC_3A_0603
C65
U503G
0.1u/10V
X7R
+V2.5S
+V1.5S_DPLLA
+V1.5S_DPLLB
22n/16V
X7R
+V1.5S_HPLL
C5
C13
0.1u/10V
X7R
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
B26
C39
AF1
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
A38
B39
VCCA_LVDS
VSSA_LVDS
AF2
VCCA_MPLL
H20
G20
VCCA_TVBG
VSSA_TVBG
E19
F19
C20
D20
E20
F20
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
AH1
AH2
VCCD_HMPLL0
VCCD_HMPLL1
A28
B28
C28
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
D21
VCCD_TVDAC
A23
B23
B25
VCC_HV0
VCC_HV1
VCC_HV2
H19
VCCD_QTVDAC
+V1.5S_MPLL
0.01u/16V
X7R
C12
C22
VTT_0
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VTT_26
VTT_27
VTT_28
VTT_29
VTT_30
VTT_31
VTT_32
VTT_33
VTT_34
VTT_35
VTT_36
VTT_37
VTT_38
VTT_39
VTT_40
VTT_41
VTT_42
VTT_43
VTT_44
VTT_45
VTT_46
VTT_47
VTT_48
VTT_49
VTT_50
VTT_51
VTT_52
VTT_53
VTT_54
VTT_55
VTT_56
VTT_57
VTT_58
VTT_59
VTT_60
VTT_61
VTT_62
VTT_63
VTT_64
VTT_65
VTT_66
VTT_67
VTT_68
VTT_69
VTT_70
VTT_71
VTT_72
VTT_73
VTT_74
VTT_75
VTT_76
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG
F21
E21
G21
+V2.5S
120mA
+V1.05S
+V3.3S_TVDACA
0.1u/10V
X7R
22n/16V
X7R
+V3.3S_TVDACB
+V1.05S
+V3.3S_TVDACC
+V2.5S
CAPS USED IN
+V2.5S_CRTDAC
SHOULD BE
WITHIN
250mils OF
EDGE OF MCH
D1
R22
C
BAT54
10
+V2.5S_CRTDAC
+V1.5S
+V1.5S
+V1.5S
70mA
L1
QT1608RL060HC_3A_0603
C503
0.1u/10V
X7R
22n/16V
X7R
+V3.3S
+V1.5S_PCIE
CAPS USED IN
+V1.5S_PCIE
SHOULD BE ON
TOP LAYER
+V1.5S
1500mA
C504
+V1.5S_QTVDAC
+V1.5S_NB
L506
QT1608RL060HC_3A_0603
C522
C523
4.7u/10V_0805
Y5V
4.7u/10V_0805
Y5V
+V1.5S
B
+V1.5S_3GPLL
2mA
L11
QT1608RL060HC_3A_0603
10uf Caps
used in
+V1.5S_3GPLL
SHOUD BE
PLACED IN
Cavity
+V1.5S
+V1.5S_QTVDAC
+V1.5S_NB
24mA
+V1.5S
3000mA
L12
QT1608RL060HC_3A_0603
C72
+V1.5S
C25
L2
QT1608RL060HC_3A_0603
C7
22n/16V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
C505
C500
4.7u/10V_0805
Y5V
+V2.5S
C9
C10
C501
4.7u/10V_0805
Y5V
0.1u/10V
X7R
0.1u/10V
X7R
modify 09/28
0.1u/10V
X7R
CAPS USED IN
+V1.5S_TVDAC AND
+V1.5S_QTVDAC should be
within 250mils of edge
+V1.5S
C6
C212
4.7u/10V_0805
Y5V
AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14
AG14
AF14
AE14
Y14
AF13
AE13
AF12
AE12
AD12
POWER
VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31
VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40
AC14
AB14
W14
V14
T14
R14
P14
N14
M14
L14
AD13
AC13
AB13
AA13
Y13
W13
V13
U13
T13
R13
N13
M13
L13
AB12
AA12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
L12
R11
P11
N11
M11
R10
P10
N10
M10
P9
N9
M9
R8
P8
N8
M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2
D2
AB1
R1
P1
N1
M1
1400mA
+V1.05S
C518
C43
4.7u/10V_0805
Y5V
C62
4.7u/10V_0805
Y5V
0.1u/10V
X7R
Place IN
CAVITY
C512
C20
10u/6.3V_0805
X5R
10u/6.3V_0805
X5R
Place on
the EDGE
VTTLF_CAP3
C502
0.1u/10V
X7R
VTTLF_CAP2
VTTLF_CAP1
C508
C521
0.1u/10V
X7R
0.1u/10V
X7R
CALISTOGA
0.1u/10V
X7R

Title
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
12
of
32
U503I
AC41
AA41
W41
T41
P41
M41
J41
F41
AV40
AP40
AN40
AK40
AJ40
AH40
AG40
AF40
AE40
B40
AY39
AW39
AV39
AR39
AN39
AJ39
AC39
AB39
AA39
Y39
W39
V39
T39
R39
P39
N39
M39
L39
J39
H39
G39
F39
D39
AT38
AM38
AH38
AG38
AF38
AE38
C38
AK37
AH37
AB37
AA37
Y37
W37
V37
T37
R37
P37
N37
M37
L37
J37
H37
G37
F37
D37
AY36
AW36
AN36
AH36
AG36
AF36
AE36
AC36
C36
B36
BA35
AV35
AR35
AH35
AB35
AA35
Y35
W35
V35
T35
R35
P35
N35
M35
L35
J35
H35
G35
F35
D35
AN34
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
U503J
VSS
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
AK34
AG34
AF34
AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21
AN21
AL21
AB21
Y21
P21
K21
J21
H21
C21
AW20
AR20
AM20
AA20
K20
B20
A20
AN19
AC19
W19
K19
G19
C19
AH18
P18
H18
D18
A18
AY17
AR17
AP17
AM17
AK17
AV16
AN16
AL16
J16
F16
C16
AN15
AM15
AK15
N15
M15
L15
B15
A15
BA14
AT14
AK14
AD14
AA14
U14
K14
H14
E14
AV13
AR13
AN13
AM13
AL13
AG13
P13
F13
D13
B13
AY12
AC12
K12
H12
E12
AD11
AA11
Y11
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
J11
D11
B11
AV10
AP10
AL10
AJ10
AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1
POWER TP
TP215
TP218
TP221
TP224
TP227
+V3.3A
TP216
TP219
TP222
TP225
TP228
+V1.05S
TP231
TP234
TP237
TP240
TP243
+V5A
+VCC_CORE
TP247
TP249
TP251
TP254
TP257
+V12A
TP232
TP235
TP238
TP241
TP244
TP246
TP248
TP250
TP252
TP255
TP260
TP263
TP266
TP269
TP272
+V3.3
TP261
TP264
TP267
TP270
TP273
+V1.8_DDR
TP276
TP278
TP280
TP283
TP286
+V5
TP277
TP279
TP281
TP284
TP287
+V0.9
TP292
TP294
TP296
TP298
TP301
+V3.3S
+V5S
TP303
TP306
TP309
TP312
TP314
+V1.5S
TP305
TP308
TP311
TP313
TP315
TP316
TP318
TP320
TP322
TP324
TP214
TP217
TP220
TP223
TP226
TP229
TP230
TP233
TP236
TP239
TP242
TP245
TP253
TP256
TP258
TP259
TP262
TP265
TP268
TP271
TP274
TP275
VIN
TP282
TP285
TP288
TP289
TP291
+V2.5S
TP300
TP302
TP304
TP307
TP310
VDD
+V12S
CALISTOGA
CALISTOGA

Title
Calistoga 6/6 Gnd & Power TP
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
13
of
32
+V3.3S
10
C561
+V1.8_DDR
+V3.3S
81
82
87
88
95
96
103
104
111
112
117
118
DDR2 RVS TYPE
DDR2 STD TYPE
CON4
0.1u/10V
X7R
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
81
82
87
88
95
96
103
104
111
112
117
118
+V1.8_DDR
199
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
M_B_A[13:0]
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
C115
0.1u/10V
X7R
199
M_A_A[13:0]
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
10
+V3.3S
CON508
10
10
10
M_A_WE#
M_A_CAS#
M_A_RAS#
9,10
9,10
M_CKE0
M_CKE1
BA0
BA1
BA2
M_CS#0
M_CS#1
110
115
S0#
NC/S1#
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
10
26
52
67
130
147
170
185
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
M_A_WE#
M_A_CAS#
M_A_RAS#
109
113
108
WE#
CAS#
RAS#
79
80
M_CLK_DDR0
30
M_CLK_DDR1 164
M_CLK_DDR#0 32
M_CLK_DDR#1 166
10 M_A_DQS#[7:0]
M_ODT0
M_ODT1
CKE0
NC/CKE1
CK0
CK1
CK#0
CK#1
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
13
31
51
70
131
148
169
188
11
29
49
68
129
146
167
186
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
M_ODT0
M_ODT1
114
119
ODT0
NC/ODT1
DDR_VREF
C114
0.1u/10V
X7R
1
184
187
190
193
196
171
172
177
178
183
+V3.3S
RT1
10
M_B_BS0
M_B_BS1
M_B_BS2
9,10
M_CS#2
9,10
M_CS#3
M_B_DM[7:0]
10K_T
26
DDR2_TEMP
R356
SA0
SA1
195
197
SDA
SCL
M_B_BS0
M_B_BS1
M_B_BS2
107
106
85
BA0
BA1
BA2
MB_CS#2
MB_CS#3
110
115
S0#
NC/S1#
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
10
26
52
67
130
147
170
185
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
109
113
108
WE#
CAS#
RAS#
1.5K_1
10
10
10
M_B_WE#
M_B_CAS#
M_B_RAS#
9,10
9,10
M_CKE2
M_CKE3
M_CKE2
M_CKE3
+V1.8_DDR
R543
C551
150_1%
0.1u/10V
X7R
10 M_B_DQS#[7:0]
DDR_VREF
C560
C556
0.1u/10V
X7R
1000p/50V
X7R
R544
150_1%
9,10
9,10
M_ODT2
M_ODT3
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
13
31
51
70
131
148
169
188
11
29
49
68
129
146
167
186
M_ODT2
M_ODT3
114
119
DDR_VREF
C562
145
149
150
155
156
161
162
165
168
0.1u/10V
X7R
modify 10/11
E1
TCSBB58-5
E2
TCSBB58-5
E502
TCS-038
E501
TCS-038
E3
TCSBB58-5
TOP
SIDE
Y5V
C108
C110
1000p/50V
1000p/50V
C107
C668 X7R
C106 X7R
C117 1000p/50V C118
C664
X7R
1000p/50V
1000p/50V
1000p/50V
Y5V
X7R
X7R
X7R
330u/3V_7343
4.7u/10V_0805
Y5V
C670
4.7u/10V_0805
4.7u/10V_0805
*4.7u/10V_0805
Y5V
C669
184
187
190
193
196
171
172
177
178
183
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
ODT0
NC/ODT1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E500
*TCS-A
BOTTOM
SIDE
330u/3V_7343
modify 10/13
TOP
SIDE
+V1.8_DDR
EMI ISSUE
C213
C215
C216
C217
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
145
149
150
155
156
161
162
165
168
Y5V
C553
Y5V
C554
Y5V
C566
C558
C559
1000p/50V
1000p/50V
C555 X7R
C571 X7R
C567 1000p/50V C569
X7R
1000p/50V
1000p/50V
1000p/50V
Y5V
X7R
X7R
X7R
+V1.8_DDR
modify 10/13
+V1.8_DDR
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
modify 10/13
modify 09/23
C552
+V1.8_DDR
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
VREF
C665
modify 10/14
modify 10/12
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK0
CK1
CK#0
CK#1
+V1.8_DDR
modify 09/23
C671
CKE0
NC/CKE1
modify 10/13
modify 09/28
+V1.8_DDR
79
80
M_CLK_DDR3
30
M_CLK_DDR2 164
M_CLK_DDR#3 32
M_CLK_DDR#2 166
9 M_CLK_DDR3
9 M_CLK_DDR2
9 M_CLK_DDR#3
9 M_CLK_DDR#2
10 M_B_DQS[7:0]
VDDSPD
198
200
SMBDATA_DDR
SMBCLK_DDR
2
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC/TEST
NC3
NC4
NC1
NC2
modify 10/11
VREF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
163
50
69
83
120
10K
10
10
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
NC/A13
NC/A14
NC/A15
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
NC/A13
NC/A14
NC/A15
107
106
85
M_CKE0
M_CKE1
9 M_CLK_DDR0
9 M_CLK_DDR1
9 M_CLK_DDR#0
9 M_CLK_DDR#1
10 M_A_DQS[7:0]
9,10
9,10
M_A_BS0
M_A_BS1
M_A_BS2
R553
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
4.7u/10V_0805
9,10
M_CS#0
9,10
M_CS#1
M_A_DM[7:0]
SDA
SCL
10K
4.7u/10V_0805
10
M_A_BS0
M_A_BS1
M_A_BS2
SA0
SA1
195
197
9 PM_EXTTS#0_DDR
R552
4.7u/10V_0805
10
10
10
198
200
M_A_DQ[63:0] 10
*4.7u/10V_0805
SMBDATA_DDR
SMBCLK_DDR
18,22 SMBDATA_DDR
18,22 SMBCLK_DDR
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
10K
NC/TEST
NC3
NC4
NC1
NC2
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
2
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
R91
10K
163
50
69
83
120
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R90
VDDSPD
M_B_DQ[63:0] 10
9 PM_EXTTS#0_DDR
D
C214
C218
1000p/50V
X7R
1000p/50V
X7R
C219
C220
C221
C222
C223
C224
1000p/50V
X7R
1000p/50V
X7R
1000p/50V
X7R
1000p/50V
X7R
1000p/50V
X7R
1000p/50V
X7R
C225
C226
C227
0.1u/10V
0.1u/10V
0.1u/10V
X7R
X7R
X7R
C672
C675
C676
0.1u/10V
0.1u/10V
0.1u/10V
X7R
X7R
X7R
BOTTOM
SIDE
+V1.8_DDR
EMI ISSUE Neer NB.

C673
C674
C677
C678
C679
C680
C681
1000p/50V
X7R
1000p/50V
X7R
1000p/50V
X7R
1000p/50V
X7R
1000p/50V
X7R
1000p/50V
X7R
1000p/50V
X7R

Title
DDR2 SODIMM
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
14
of
32
+V3.3S
U501
+V3.3S
U1
SEL
NB-A
9
9
9
9
9
9
9
9
LA_DATAN0
LA_DATAP0
LA_DATAN1
LA_DATAP1
LA_DATAN2
LA_DATAP2
LA_CLKN
LA_CLKP
DK_LA_DATAN0
DK_LA_DATAP0
DK_LA_DATAN1
DK_LA_DATAP1
DK_LA_DATAN2
DK_LA_DATAP2
DK_LA_CLKN
DK_LA_CLKP
TP7
TP8
TP6
TP5
TP1
TP2
TP3
TP4
MXM-A
36
19
12
6
1
VDD5
VDD4
VDD3
VDD2
VDD1
14
NC
24
SEL
48
47
42
41
35
34
29
28
A1
B1
C1
D1
E1
F1
G1
H1
45
44
39
38
32
31
26
25
A2
B2
C2
D2
E2
F2
G2
H2
2
4
8
10
15
17
21
23
YA
YB
YC
YD
YE
YF
YG
YH
LVDSA_N0 20
LVDSA_P0 20
LVDSA_N1 20
LVDSA_P1 20
LVDSA_N2 20
LVDSA_P2 20
LVDSA_CLKN 20
LVDSA_CLKP 20
SEL
3
5
7
9
11
13
16
18
20
22
27
30
33
37
40
43
46
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
9
9
9
9
9
9
9
9
NB-B
LB_DATAN0
LB_DATAP0
LB_DATAN1
LB_DATAP1
LB_DATAN2
LB_DATAP2
LB_CLKN
LB_CLKP
TP519
TP523
TP517
TP528
TP526
TP525
TP524
TP520
MXM-B
DK_LB_DATAN0
DK_LB_DATAP0
DK_LB_DATAN1
DK_LB_DATAP1
DK_LB_DATAN2
DK_LB_DATAP2
DK_LB_CLKN
DK_LB_CLKP
36
19
12
6
1
VDD5
VDD4
VDD3
VDD2
VDD1
14
NC
24
SEL
48
47
42
41
35
34
29
28
A1
B1
C1
D1
E1
F1
G1
H1
45
44
39
38
32
31
26
25
A2
B2
C2
D2
E2
F2
G2
H2
YA
YB
YC
YD
YE
YF
YG
YH
2
4
8
10
15
17
21
23
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
3
5
7
9
11
13
16
18
20
22
27
30
33
37
40
43
46
LVDSB_N0 20
LVDSB_P0 20
LVDSB_N1 20
LVDSB_P1 20
LVDSB_N2 20
LVDSB_P2 20
LVDSB_CLKN 20
LVDSB_CLKP 20
**PI3DBV40
**PI3DBV40
LA_DATAP1
LA_DATAN1
LA_DATAP0
LA_DATAN0
LA_CLKP
LA_CLKN
LA_DATAP2
LA_DATAN2
RP2
5
6
7
8
5
6
7
8
RP1
8P4RX0
4
3
2
1
4
3
2
1
8P4RX0
LB_DATAP1
LB_DATAN1
LB_DATAP0
LB_DATAN0
LB_CLKP
LB_CLKN
LB_DATAP2
LB_DATAN2
LVDSA_P1
LVDSA_N1
LVDSA_P0
LVDSA_N0
LVDSA_CLKP
LVDSA_CLKN
LVDSA_P2
LVDSA_N2
CRT / TV
IF USE Extenal VGA(C30/C40 EN)
RP501
5
6
7
8
5
6
7
8
RP500
8P4RX0
LVDSB_P1
4
LVDSB_N1
3
LVDSB_P0
2
LVDSB_N0
1
LVDSB_CLKP
4
LVDSB_CLKN
3
LVDSB_P2
2
LVDSB_N2
1
8P4RX0
** must install
MUST INSTALL:
1.U4,U5 from NC to PI3DBV40
2.U6 from NC to PI5V330
3.Q7,Q8,Q9,Q10,Q11,Q12,Q13,Q14 from NC to 2N7002
4.C198 from NC to 4.7uF
REMOVE:
1.RP1,RP2,RP3,RP4 from 8P4R_0 to NC
2.R140,R141,R142,R429,R430,R431,R432 from 0 to NC
+V5S
U500
SEL
9 CRT_GREEN
TP500
DK_CRT_GREEN
CRT_GREEN_OUT
9 CRT_BLUE
DK_CRT_BLUE
CRT_BLUE_OUT
TP501
B
1
2
3
4
5
6
7
8
INTERNAL / EXTERNAL SELECT
C507
VCC
EN#
S1D
S2D
DD
S1C
S2C
DC
IN
S1A
S2A
DA
S1B
S2B
DB
GND
16
15
14
13
12
11
10
9
**4.7u/10V_0805
Y5V
SEL
Change:
1.L11,L12,L13 change 0 to QT1608RL011
L
DK_CRT_RED
CRT_RED_OUT
MXM_VO-ON 20,25,26
INTERNAL
LO = n1-> Yn
CRT_RED 9
TP512
**PI5V330
EXTERNAL
HI = n2-> Yn
CRT_GREEN R501
CRT_BLUE
R500
CRT_RED
R512
0
0
0
CRT_BLUE_OUT L500
CRT_GREEN_OUT L501
CRT_RED_OUT
L503
CRT_GREEN_OUT
CRT_BLUE_OUT
CRT_RED_OUT
0/**QT1608RL011
0/**QT1608RL011
0/**QT1608RL011
OUT_CRT_BLUE
OUT_CRT_GREEN
OUT_CRT_RED
OUT_CRT_BLUE 25
OUT_CRT_GREEN 25
OUT_CRT_RED 25
R522
R51
R518
R34
CRT_VSYNC
20,25,26 MXM_VO-ON
TP515
DK_CRT_HSYNC
25
CRT_VSYNC_OUT
Q500
**2N7002
25
TP9
Q7
**2N7002
TV_C_DACC
20,25,26 MXM_VO-ON
Q4
**2N7002
TV_Y_DACB
Q503
**2N7002
D
MXM
20,25,26 MXM_VO-ON#
CRT_HSYNC_OUT
Q501
**2N7002
CRT_HSYNC
DK_TVY_DACB
20,25,26 MXM_VO-ON#
Q3
**2N7002
NB
Q6
**2N7002
Q502
**2N7002
TV_Y_DACB_OUT 23
TV_C_DACC_OUT 23

Title
TP522
DK_CRT_VSYNC
TP31
DK_TVC_DACC
Internal/Extenal VGA Switch
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
15
of
32
ICH7M INTERNAL VR
ENABLE STRAP
+V3.3A_RTC
+V3.3A
D4
A
RTC Circuitry
C152
modify 10/17
1u/10V_0603
Y5V
C135
10p/50V
NPO
Y2
32.768KHz_DIP
1K
1M
C139
10p/50V
NPO
R127
10M
U9A
CON511
1
2
+V3.3A_RTC
BAT_CONN
R580
332K_1%
ICH7M INTERNAL VR ENABLE STRAP

R579
INTVRMEN
AB1
AB2
RTXC1
RTCX2
AA3
RTCRST#
Y5
W4
INTRUDER#
INTVRMEN
W1
Y1
Y2
W3
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN
*0
Enable(Default)
Disable
STUFF
UNSTUFF
V3
LAN_CLK
UNSTUFF
STUFF
U3
LAN_RSTSYNC
U5
V4
T5
LAN_RXD0
LAN_RXD1
LAN_RXD2
U7
V6
V7
LAN_TXD0
LAN_TXD1
LAN_TXD2
ACZ_BITCLK
ACZ_SYNC
U1
R6
ACZ_BIT_CLK
ACZ_SYNC
ACZ_RST#
R5
ACZ_RST#
T2
T3
T1
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
T4
ACZ_SDOUT
+V3.3S
R110
R101
0.1u/10V
X7R
10K
10K
25
25
25
TP138
1
IDE_ACT#
S
2N7002
Q26
4
2
3
25
25 ACZ_SDATAIN0
25 ACZ_SDATAIN1
U5
C126
CD_LED# 23
25 ACZ_SDATAOUT
AF18
SATALED#
AF3
AE3
AG2
AH2
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
AF7
AE7
AG6
AH6
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AF1
AE1
SATA_CLKN
SATA_CLKP
TC7SH08FU
22
22
22
22
SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0
C640 3900p/50V
X7R
C128 3900p/50V
X7R
C639 3900p/50V
X7R
C127 3900p/50V
X7R
Distance between the ICH7M and CAP on

the "P"singnal should be identical
distance between the ICH7M and CAP on
the "N"signal for same pair.
5 CLK_PCIE_SATA#
5 CLK_PCIE_SATA
Layout Note: Short pins AH10

and AG10 at the package.
Place CAP within 500mils of
ICH7 ball.
R121
24.9_1%
23 IDE_PDIOR#
23 IDE_PDIOW#
23 IDE_PDDACK#
23
INT_IRQ14
23 IDE_PDIORDY
23 IDE_PDDREQ
AH10
AG10
SATARBIASN
SATARBIASP
AF15
AH15
AF16
AH16
AG16
AE15
DIOR#
DIOW#
DDACK#
IDEIRQ
IORDY
DDREQ
LPC_AD[3:0]
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
26
LAD0
LAD1
LAD2
LAD3
AA6
AB5
AC4
Y6
LDRQ0#
LDRQ1#/GPIO23
AC3
AA5
LFRAME#
AB3
A20GATE
A20M#
CPUSLP#
AE22
AH28
AG27
TP1/DPRSTP#
TP2/DPSLP#
AF24
AH25
FERR#
AG26
GPIO49/CPUPWRGD
AG24
IGNNE#
INIT3_3V#
INIT#
INTR
AG22
AG21
AF22
AF25
H_INIT#
H_INTR
6
6
RCIN#
AG23
H_RCIN#
18,26
NMI
SMI#
AH24
AF23
H_NMI
H_SMI#
6
6
H_STPCLK# 6
LPC
*0.1u/10V
X7R
CPU
1u/10V_0603
Y5V
R160
modify 10/17
RTC
JP1
OPEN
LAN
C154
R158
C155
AC-97 /AZALIA
20K
+V1.05S
R125
*0
LDRQ#0
26
+V1.05S
LPC_FRAME# 26
R604
H_A20GATE 26
H_A20M# 6
H_CPUSLP# 6,8
*0
modify 09/15
R114 R113
*56
*56
R112
H_DPRSTP# 6,30
H_DPSLP# 6
56
H_FERR# 6
H_PWRGD 6
H_IGNNE# 6
TP134
STPCLK#
AH22
THERMTRIP#
AF26
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15
IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15
DA0
DA1
DA2
AH17
AE17
AF17
IDE_PDA0
IDE_PDA1
IDE_PDA2
DCS1#
DCS3#
AE16
AD16
+V1.05S
R97
56
R111
PM_THRMTRIP# 6,9
24.9_1%
SATA
R156
BAT54
IDE
D5
BAT54
IDE_PDD[15:0]
23
Layout Note: CAP needs to placed

Within 2" of ICH7 R must be placed
within 2"of R W/O stub.
IDE_PDA[2:0]
23
modify 10/13
EMI ISSUE
IDE_PDCS1# 23
IDE_PDCS3# 23
ICH7M
+V1.5S
+V1.05S
+V5S
+V3.3S
+V3.3S
C206
C207
*0.01u/16V
X7R
0.01u/16V
X7R
C663
C208
C209
C210
0.01u/16V
X7R
*0.01u/16V
X7R
0.01u/16V
X7R
0.01u/16V
X7R
C211
*0.01u/16V
X7R
R581
*1K
ACZ_SDATAOUT
RSVD9
17
R214
A
*1K

Title
ICH7M 1/4 RTC,SATA,IDE,CPU
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
16
of
32
22 PCIE_TXN3_M_C
22 PCIE_TXP3_M_C
C158
0.1u/10V
X7R
0.1u/10V
X7R
22 PCIE_RXN3_M_C
22 PCIE_RXP3_M_C
C160
PERn1
PERp1
PETn1
PETp1
H26
H25
G28
G27
PERn2
PERp2
PETn2
PETp2
K26
K25
J28
J27
PERn3
PERp3
PETn3
PETp3
M26
M25
L28
L27
PERn4
PERp4
PETn4
PETp4
P26
P25
N28
N27
PERn5
PERp5
PETn5
PETp5
T25
T24
R28
R27
PERn6
PERp6
PETn6
PETp6
TP140
TP552
TP141
R2
P6
P1
TP553
TP142
P5
P2
SPI_MOSI
SPI_MISO
D3
C4
D5
D4
E5
C3
A2
B3
OC0#
OC1#
OC2#
OC3#
OC4#
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
+V3.3
RP12 1
8P4RX8.2K 2
3
RP10 4
1
8P4RX8.2K 2
3
4
8
7
6
5
8
7
6
5
USB_OC#7
USB_OC#6
USB_OC#2
USB_OC#1
USB_OC#5
USB_OC#3
USB_OC#0
USB_OC#4
SPI_CLK
SPI_CS#
SPI_ARB
Direct Media Interface
Layout note:PCIE AC coupling

caps need to be within
250mils of the driver.
F26
F25
E28
E27
USB
C165
0.1u/10V
X7R
SPI
C162
0.1u/10V
X7R
PCI-Express
U9D
21 PCIE_RXN1_LAN
21 PCIE_RXP1_LAN
21 PCIE_TXN1_LAN
21 PCIE_TXP1_LAN
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
V26
V25
U28
U27
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
9
9
9
9
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
Y26
Y25
W28
W27
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
9
9
9
9
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
AB26
AB25
AA28
AA27
DMI_RXN2 9
DMI_RXP2 9
DMI_TXN2 9
DMI_TXP2 9
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
AD25
AD24
AC28
AC27
DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3
DMI_CLKN
DMI_CLKP
AE28
AE27
PCIE_CLK_ICH# 5
PCIE_CLK_ICH 5
DMI_ZCOMP
DMI_IRCOMP
+V1.5S
9
9
9
9
R179
24.9_1%
Place within 500mils

of ICH7M
C25
D25
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3
USBRBIAS#
USBRBIAS
D2
D1
USB_P0USB_P0+
USB_P1USB_P1+
USB_P4USB_P4+
USB_P5USB_P5+
USB_P6USB_P6+
23
23
25
25
USB PN/PP
DEVECE
M/B
M/B
M/B
M/B
23
23
25
25
25
25
NWE_CARD
MINI_CARD
PORT_REPLICATOR
USB_HUB
ICH7M
Place within
500mils of
ICH7M
R177
22.6_1%
U9B
22,23 PCI_AD[31:0]
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
E18
C18
A16
F18
E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10
F11
F10
E9
D9
B9
A8
A6
C7
B6
E6
D6
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
REQ4#/GPIO22
GNT4#/GPIO48
GPIO1/REQ5#
GPIO17/GNT5#
D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8
C/BE0#
C/BE1#
C/BE2#
C/BE3#
B15
C12
D12
C15
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
A7
E10
B18
A12
C9
E11
B10
F15
F14
F16
PCI_IRDY# 18,22,23
PCI_PAR 18,22,23
PCI_RST# 18,22,23,26
PCI_DEVSEL# 18,22,23
PCI_PERR# 18,22,23
PCI_LOCK# 18
PCI_SERR# 18,22
PCI_STOP# 18,22,23
PCI_TRDY# 18,22,23
PCI_FRAME# 18,22,23
PLTRST#
PCICLK
PME#
C26
A9
B19
PLT_RST# 9,18,21,22,26
PCI_CLK_ICH7 5
PCI_PME# 22,23
PCI
INTERRUPT
18,23
18
18,22
18
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
A3
B4
C5
B5
PIRQA#
PIRQB#
PIRQC#
PIRQD#
AE5
AD5
AG4
AH4
AD9
RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]
PCI_REQ#0
PCI_GNT#0
PCI_REQ#1
PCI_GNT#1
PCI_REQ#2
18,22
22
18,23
23
18
TP560
TP554
R225
PCI_REQ#4 18
TP146
*1K
PCI_REQ#5 18
PCI_GNT#5
REQ/GNT
0
1
PCI_GNT#5
PCI_REQ#3 18
22,23
22,23
22,23
22,23
DEVECE
1394
PCMCIA
2
3
4
5
NC
NC
NC
INT
A
B
DEVECE
PCMCIA
NC
C
D
E
F
G
H
1394
NC
PCMCIA
NC
NC
NC
NC
I/F
GPIO2/PIRQE#
GPIO3/PIRQF#
GPIO4/PIRQG#
GPIO5/PIRQH#
G8
F7
F8
G7
INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#
18,23
18
18
18
MISC
TP544
TP549
TP131
TP130
TP547
RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
MCH_SYNC#
AE9
AG8
AH8
F21
AH20
TP548
TP132
TP133
RSVD9
16
MCH_ICH_SYNC#
ICH7M

Title
ICH7M 2/4 PCI-E,PCI,USB
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
17
of
32
+V3.3
+V3.3S
ICH7M PULLUPS TO HI
+V3.3
SMBCLK_DDR
R251
2.2K
SMBDATA_DDR
R212
2.2K
SATA0 and SATA2 ICH6 PULL HI(3.3V)

ICH7M PULL LO
+V3.3S
SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1
PM_RI#
A28
RI#
TP145
A19
A27
A22
SPKR
SUS_STAT#
SYS_RST#
R215
*1K
R213
23
10K
25
R98
R555
*10K
*10K
ACZ_SPKR
26 PM_SYSRST#
AB18
PM_BMBUSY#
PM_ALERT#
5
5
R559
R116
PM_STPPCI#
PM_STPCPU#
26
26
26
+V3.3S
0
0
B23
AC20
AF21
LED_R
LED_G
LED_B
LED_R
LED_G
LED_B
R248
R247
R243
GPO26
GPO27
GPO28
*0
*0
*0
100K
22 PCIE_WAKE#
23,26 INT_SERIRQ
B21
E23
R560
21
R618
G_RST#
26
26
EC_SCI#
EC_EXTSMI#
GPIO18/STPPCI#
GPIO20/STPCPU#
GPIO26
GPIO27
GPIO28
GPIO32/CLKRUN#
AC19
U2
GPIO33/AZ_DOCK_EN#
GPIO34/AZ_DOCK_RST#
PM_THROTTING#
F20
AH21
AF20
WAKE#
SERIRQ
THRM#
AD22
VRMPWRGD
AC21
AC18
E21
GPIO6
GPIO7
GPIO8
modify 10/13
VR_PWRGD
GPIO11/SMBALERT#
AG18
9 DELAY_VR_PWRGOOD
30
GPIO0/BM_BUSY#
TP545
TP137
22 PM_CLKRUN#
R556
A21
SMB
C22
B22
A26
B25
A25
SYS-GPIO
Power MGT
SMBCLK_DDR
SMBDATA_DDR
SMB_LINK_ALERT#
SMLINK0
SMLINK1
14,22 SMBCLK_DDR
14,22 SMBDATA_DDR
4.7K
G_LAN_RST
EC_SCI#
CLOCKS SATA
GPIO
U9C
+V3.3S
17,22,23
17,22,23
17,22,23
17,22,23
17,22
17,22,23
17,22,23
17
GPIO
GPIO21/SATA0GP
GPIO19/SATA1GP
GPIO36/SATA2GP
GPIO37/SATA3GP
R99
R119
R118
R557
AF19
AH18
AH19
AE19
*100
100
100
100
CLK14
CLK48
AC1
B2
SUSCLK
C20
SLP_S3#
SLP_S4#
SLP_S5#
B24
D23
F22
PWROK
AA4
VCC_MCH_VRPWRGD
AC22
PM_DPRSLPVR 9,30
GPIO16/DPRSLPVR
C21
PWRBTN#
C23
LAN_RST#
C19
RSMRST#
Y4
R256
R227
R220
R219
R224
R222
R260
R258
R262
R255
R218
R257
R221
R226
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
*8.2K
8.2K
R231
R230
R229
R239
R223
R228
R261
R171
R120
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
SUS_CLK
PM_SLP_S3#R
PM_SLP_S4#R
PM_SLP_S5#R
R210
R209
R614
100
100
100
modify 09/27
TP0/BATLOW#
GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO35
GPIO38
GPIO39
CLK_REF_ICH7 5
USB_CLK_48M 5
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_SERR#
PCI_DEVSEL#
PCI_PERR#
PCI_LOCK#
17,22 PCI_REQ#0
17,23 PCI_REQ#1
17 PCI_REQ#2
17 PCI_REQ#3
17 PCI_REQ#4
17 PCI_REQ#5
PM_SLP_S3# 23,26
PM_SLP_S4# 26
PM_SLP_S5# 26
+V3.3
26
R250
*10K
PM_BATLOW#
PM_PWRBTN# 26
LAN_RST#
R216
PM_RSMRST#R
E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20
0
R567
17,23 INT_PIRQA#
17 INT_PIRQB#
17,22 INT_PIRQC#
17 INT_PIRQD#
17,23 INT_PIRQE#
17 INT_PIRQF#
17 INT_PIRQG#
17 INT_PIRQH#
22 PM_CLKRUN#
PLT_RST# 9,17,21,22,26
100
PM_RSMRST# 26
LCDSEL0# 20
LCDSEL1# 20
LCDSEL2# 20
TP555
TP136
TP559
TP139
TP556
TP550
TP546
TP543
8.2K
10K
10K
*10K
10K
PM_THROTTING# R117
R96
R115
R259
EC_SCI#
R558
16,26 H_RCIN#
23,26 INT_SERIRQ
17,22,23 PCI_PAR
+V3.3
SMB_LINK_ALERT#
R189
PM_ALERT#
R249
ICH7M
23
10K
10K
SMLINK1
R211
10K
SMLINK0
R242
10K
R187
10K
R198
R245
*4.7K
*4.7K
PM_RI#
23,26 PM_SLP_S3#
26 PM_SLP_S4#
+V3.3
17,22,23,26 PCI_RST#
9,17,21,22,26 PLT_RST#
R217
R185
R253
R254
SUS_CLK
22 PCIE_WAKE#
*8.2K
*8.2K
*10K
1K
modify 09/15
ICH7M PULLUPS TO LO
9,30 PM_DPRSLPVR
26 PM_RSMRST#
VCC_MCH_VRPWRGD
R561
*8.2K
R566
10K
R562
10K
+V3.3
PM_BATLOW#
R252
10K

Title
ICH7M 3/4 GPIO,MGT
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
18
of
32
+V1.05S
R554
D501
100
BAT54
U9F
modify 09/28
C596
Layout Note: Place above CAPS within

100mils of ICH7 on the bootom side or
140mils on the top near Pin
D28,T28,AD28
+V1.5S
C619
0.1u/10V
X7R
*22u/6.3V_0805
C159
+ C143
4.7u/10V_0805
X5R
Y5V
C617
0.1u/10V 0.1u/10V
X7R
X7R
+V3.3S
L13
1
QT1608RL060HC_3A_0603
C131
4.7u/10V_0805
Y5V
C603
0.1u/10V
X7R
+V1.5S
Place CAP within 100mils of ICH7

on the bottom side or 140mils on
the top near pin AG5,
C602
0.1u/10V
X7R
B27
+V1.5S
+V1.5S_DMIPLL
C140

the top ,
C604
+V3.3
0.1u/10V
X7R
+V1.5S
0.1u/10V
X7R
C172
1u/10V_0603
Y5V
+V1.5S
V5
V1
W2
W7
Vcc3_3/VccHDA
U6
VccSus3_3/VccSusHDA
R7
V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]
AE23
AE26
AH26
Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]
Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]
AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19
Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]
A5
B13
B16
B7
C10
D15
F9
G11
G12
G16
Vcc3_3[1]
VccDMIPLL
AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5
Vcc1_5_A[1]
Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]
AD2
VccSATAPLL
AH11
Vcc3_3[2]
AB10
AB9
AC10
AD10
AE10
AF10
AF9
AG9
AH9
Vcc1_5_A[10]
Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]
ATX

the top near pin AG9,
VccSus3_3/VccLAN3_3[1]
ARX

the top ,
AG28
VCC PAUX
VCCA3GP
0.01u/16V
X7R
C137
CORE
0.1u/10V
X7R
Vcc1_5_B[1]
Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
IDE
Layout Note: CAP needs be placed

within 100mils of pin F6 of ICH7 on
the bottom side or 140mils on the
top.
AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
W23
Y22
Y23
Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]
Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]
PCI
C667
V5REF_Sus
USB
D6
BAT54
V5REF_SUS
VccRTC
W5
VccSus3_3[1]
P7
VccSus3_3[2]
VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]
A24
C24
D19
D22
G19
VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]
K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7
Vcc1_5_A[19]
Vcc1_5_A[20]
AB17
AC17
Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]
T7
F17
G17
Vcc1_5_A[24]
Vcc1_5_A[25]
AB8
AC8
E3
VccSus3_3[19]
VccSus1_05[1]
K7
0.1u/10V
X7R
C1
VccUSBPLL
VccSus1_05[2]
VccSus1_05[3]
C28
G20
C637
0.1u/10V
X7R
TP135
TP551
AA2
Y7
Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]
C624
0.1u/10V
X7R
C623
1u/10V_0603
Y5V
C606+
X5R
C607
4.7u/10V_0805
Y5V
Layout Note:
Place at MCH
edge,
+V3.3
+V3.3S
C632
Layout Note: Place

on secondary side
under MCH,
0.1u/10V
X7R
+V3.3
Layout Note: Place CAP within

100mils of ICM7 on the botom
side or 140mils on the top
near pin,
C638
0.1u/10V
X7R
+V1.05S
+V3.3S
Layout Note: Place CAPS

within 100mils of ICM7 on the
botom side or 140mils on the
+V3.3S
top near pin,
C592
0.1u/10V
X7R
C636
C634
C601
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
C628
C616
0.1u/10V
X7R
0.1u/10V
X7R
C576
4.7u/10V_0805
Y5V
Layout Note:
Distribute in
PCI section
+V3.3A_RTC
+V3.3
C614
USB CORE
+V3.3S
V5REF[2]
F6
R271
10
+V1.5S
V5REF[1]
0.1u/10V
X7R
Place above CAPS within 100mils of

ICH7 on the bottom side or 140mils
on the top,
G10
AD17
*22u/6.3V_0805
V5REF
+V3.3
+V5
C586
Layout Note: CAP needs be placed

within 100mils of pin AD17 of ICH7 on
the bottom side or 140mils on the
top.
+V3.3S
A
+V5S
+V3.3
C627
C621
0.1u/10V
X7R
0.1u/10V
X7R
+V1.5S
C629
C625
0.1u/10V
X7R
0.1u/10V
X7R
C610
C611
0.1u/10V
X7R
0.1u/10V
X7R
+V1.5S
+V1.5S
+V1.5S
B
X7R
C631 0.1u/10V
C635
0.1u/10V
X7R
A1
H6
H7
J6
J7
+V1.5S
ICH7M
C600
U9E
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27
0.1u/10V
X7R
ICH7M
A4
A23
B1
B8
B11
B14
B17
B20
B26
B28
C2
C6
C27
D10
D13
D18
D21
D24
E1
E2
E4
E8
E15
F3
F4
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G18
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J1
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L24
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M17
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P24
P27
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]

Title
ICH7M 4/4 Power pin
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
19
of
32
Tentative LVDS Voltage Translation Circuitry

LCDVCC
15,25,26 MXM_VO-ON#
LCD
+V2.5S
R536
**2.2K
9 L_DDC_CLK
CON504
15
15
EDID_CLK
LVDSA_N0
LVDSA_P0
15 LVDSA_CLKN
15 LVDSA_CLKP
+V2.5S
15
15
18
R534
**2.2K
Q506
**2N7002
LVDSB_N1
LVDSB_P1
LCDSEL1#
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
15 LVDSB_CLKN
15 LVDSB_CLKP
Q504
**2N7002
EDID_CLK
+V3.3S
LVDSB_N2 15
LVDSB_P2 15
+V3.3
LVDSA_N1 15
LVDSA_P1 15
LCDSEL0#
LCDSEL1#
LCDSEL2#
EDID_DATA
EDID_CLK
LVDSA_N2 15
LVDSA_P2 15
LVDSB_N0
LVDSB_P0
LCDSEL2#
LCDSEL0#
EDID_DATA
R531
R63
R530
R527
R529
4.7K
4.7K
4.7K
4.7K
4.7K
15
15
18
18
LCD_CON
S
R535
R528
9 L_DDC_DATA
EDID_DATA
PANNEL SELECT
LCDSEL2# LCDSEL1# LCDSEL0#
modify 08/02
OPTION FOR DOCKING VGA PCI_E

G
15,25,26 MXM_VO-ON
MUST INSTALL:
1.Q16,Q17,Q26,Q27,Q19,Q21,Q22,Q25 from NC to 2N7002
2.R238,R240 from NC to 2.2K
DK_EDID_CLK
EDID_CLK
Q505
**2N7002
15,25,26 MXM_VO-ON
G
TP112
** must install
TP111
DK_EDID_DATA
EDID_DATA
1400X1050
1280X800
1280X768
reserved
1680X1050
1920X1200
1440X900
1024X768
13.3"(16:9)
13"(15:9)
C
Q507
**2N7002
REMOVE:
1.R433,R434,R435,R438 from 0 to NC
VIN_LCD
CON503
R54
BRIGHTADJ
26 BRIGHTADJ
1
3
5
7
9
100
QT1608RL060HC_3A_0603
VIN
INVERTER
C513
C517
0.1u/25V_0603
1u/25V_0805
Y5V
R521
100
BL_ON
+V3.3S
B
INV CONN
VIN_LCD
L505
2
4
6
8
10
modify 09/28
R341
*4.7K
26
LCDSW
+V3.3S
R53
L4
0
C31
QT1608RL060HC_3A_0603
C30
0.1u/10V
X7R
*220p/50V
NPO
AO3413L
R59
R52
G
15,25,26 MXM_VO-ON#
47K
1K
C204+
4.7u/10V_0805
Y5V
C205
*4.7u/10V_0805
Y5V
EN_BL
DK_BKLTEN
D
Q12
**2N7002
BL_ON
4
9
TP52
Q14
**2N7002
U2
TC7SH08FU
1
Q9
**2N7002
LCDVCC
2
3
R62
VCC3_LCD
+V3.3S
15,25,26 MXM_VO-ON#
Q11
S
EN_LCD
R60
47K
G
C51
DK_FPVDDEN S
TP94
2N7002
15,25,26 MXM_VO-ON
0.1u/10V
X7R
Q15
**2N7002
G
Q13
Title
LCD/INVERTOR
15,25,26 MXM_VO-ON
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
20
of
32
AVDD25
17
17
17
17
modify 10/11
SMB_CLK, SMB_DATA are NC on
88E8053 and 88E8036. Mount
R4 and R5 only when using
88E8052.
PCIE_CLK_LAN
PCIE_CLK_LAN#
PCIE_RXP1_LAN
PCIE_RXN1_LAN
PCIE_TXP1_LAN
PCIE_TXN1_LAN
5 PCIE_CLK_LAN
5 PCIE_CLK_LAN#
QT1608RL060HC_3A_0603
PLT_RST#
9,17,18,22,26 PLT_RST#
L509
PCIE_RXP1_LAN
PCIE_RXN1_LAN
PCIE_TXP1_LAN
PCIE_TXN1_LAN
+V3.3A
VPD_DATA
C564
+V3.3A
3V3_main=0 at S5
for PnG function
1000p/50V 1u/10V_0603
X7R
Y5V
R123
R124
4.7K
4.7K
U7
VPD_CLK
+V3.3A
VPD_CLK
VPD_DATA
pin 34,35,36,37 are NC on E8036
X7R
1
2
3
7
GND
VDD
0.1u/10V
A0
SCLEEPROM A1
A2
SDA
WP
6
5
C136
modify 10/11
C563
VCC
PT1
34
35
36
37
38
39
40
41
42
43
44
45
46
47
33
VDD
SPI_DO
SPI_DI
SPI_CS
AVDDL
SPI_CLK
TX_N
51
VPD_CLK
50
VDD
0.1u/10V X7R
VDDO_TTL
C609
VPD_DATA
PCIE_RXN1_LAN
SMCLK
TX_P
SMDATA
49
VDD
0.1u/10V X7R
VDDO_TTL
C608
AVDDL
32
MDIN[3]
31
MDI3-
MDIP[3]
30
MDI3+
52
AVDDL
TSTPT
29
PCIE_TXN1_LAN
53
RX_N
AVDDL
28
PCIE_TXP1_LAN
54
RX_P
MDIN[2]
27
MDI2-
PCIE_CLK_LAN
55
REFCLKP
MDIP[2]
26
MDI2+
PCIE_CLK_LAN#
56
REFCLKN
HSDACN
25
57
AVDDL
HSDACP
24
58
VDD
AVDD
23
59
LED_LNK/ACTn
AVDDL
22
C111
1000p/2KV_1808
XTALO
CRYSTAL 25MHz
MDIN[0]
18
MDI0-
VDD25
MDIP[0]
17
MDI0+
EPAD
16
15
VDD
14
13
12
11
10
SWITCH_VAUX
9
modify 10/11
MDI1MDI1+
C130
C133
22p/50V
NPO
22p/50V
NPO
RSET
LED_LINKn
64
XTALI
63
XTALO
19
VAUX_AVLBL
MDI1+
AVDDL
SWITCH_VCC
20
LED_LINK1000n
LOM_DISABLEn
21
MDIP[1]
VDDO_TTL_MAIN
MDIN[1]
VDDO_TTL
62
VDD
LED_LINK10/100n
61
WAKEn
60
PERSTn
MDI2MDI2+
XTALI
Y1
MDI1-
MDI3MDI3+
88E805X
CTRL25
CTRL12
75
75
75
75
LG-2407S
MDI0MDI0+
VDD
U6
PCIE_RXP1_LAN
TESTMODE
48
AVDD25
TXD+_3
TXD-_3
AVDD25
VMAIN_AVAL
TXD+_3
TXD-_3
TXD+_2
TXD-_2
MDI0+
MDI0V_DAC
MDI1+
MDI1V_DAC
MDI2+
MDI2V_DAC
MDI3+
MDI3V_DAC
VDD
23
23
TXD+_1
TXD-_1
12
11
10
9
8
7
6
5
4
3
2
1
TD4TD4+
TCT4
TD3TD3+
TCT3
TD2TD2+
TCT2
TD1TD1+
TCT1
VDDO_TTL
TXD+_2
TXD-_2
MX4MX4+
MCT4
MX3MX3+
MCT3
MX2MX2+
MCT2
MX1MX1+
MCT1
TXD+_1
TXD-_1
23
23
13
14
15
16
17
18
19
20
21
22
23
24
23
23
TXD+_0
TXD-_0
R82
R83
R84
R87
TXD+_0
TXD-_0
M24C08
23
23
88E805X
+V3.3A
R122
R105
R102
R103
R104
R106
R107
R108
4.87K 1%
R109
XTALI
49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1%
modify 10/11
+V3.3A
modify 10/13
CTRL12
XTALO
R451 = 2K for E8036
CTRL25
C578
0.1u/10V
C583
X7R
C579
C582
0.1u/10V
C577
X7R
C584
0.1u/10V
C581
X7R
C144
C142
0.1u/10V
0.1u/10V
1000p/50V
X7R X7R
1000p/50V
X7R
1000p/50V
X7R
C594
C593
0.1u/10V
X7R
1000p/50V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
PLT_RST#
PCIE_LAN_WAKE#
C591
C580
22 PCIE_LAN_WAKE#
0.1u/10V
X7R
X7R
R357 4.7K
+V3.3A
modify 10/11
18
R619
G_RST#
*0
88E8053 rev. A2 issue:

Reset IC to delay 250ms when VAUX33 available.
Or use GPIO to control LOM_DISABLEn
+V3.3A
R126
4.7K
modify 10/13
+V2.5S
+V3.3A
modify 10/11
+V3.3A
L15
4.7u/10V_0805
Y5V
0.1u/10V
X7R
+ C169
C141
4.7u/10V_0805
Y5V
4.7K
1
CTRL25
+ C163
4.7u/10V_0805
Y5V
R180
C590
C597
C161
+ C164
0.1u/10V
X7R
R167
4.7u/10V_0805
Y5V
C589
4.7K
1
BCP69T1
Q29
*QT1608RL060HC_3A_0603
0.1u/10V
X7R
C167
0.1u/10V
BCP69T1
Q30
AVDD25
0.1u/10V
X7R
AVDD25
0.1u/10V
X7R
VDD
0.1u/10V
X7R
CTRL12
X7R
+ C170
VDD
QT1608RL060HC_3A_0603
L17
C166
+ C150
C146
+ C151
4.7u/10V_0805
Y5V
AVDD25
88E8053
88E8055
2.5V
1.8V
C587
C598
C145
C588
0.1u/10V
X7R
PLACE PNP TO CHIP ACAP

CTRL25 PIN TRACE IS
25MIL
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
C148
4.7u/10V_0805
Y5V
C153
0.1u/10V
X7R
Note: Place Bypass Cap. as close as possible with every

power pin.

Title
GIGA-LAN
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
21
of
32
4
500mA
1A
+V3.3S
PCI_AD[0..31]
PCI_C/BE#[0..3]
C647
+
17 PCIE_RXP3_M_C
17 PCIE_RXN3_M_C
15
13
11
9
7
5
3
1
5 MINICARD_REQ#
PCIE_MINI_WAKE#
R613
GND
REFCLK+
REFCLKGND
CLKREQ#
RESERVED
RESERVED
WAKE#
UIM_VPP
UIM_RESET
UIM_CLK
UIM_DATA
UIM_PWR
+V1.5
GND
+V3.3
WL-LED-L#
R597 1
*0
R596 1
R595 1
300mA
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
RF_LED_ON# 25,26
*0
*0
2
2
SMBDATA_DDR 14,18
SMBCLK_DDR 14,18
+V3.3
MINI_RFON
16
14
12
10
8
6
4
2
R590 1
26
1
R589
*0
PCI_RST# 17,18,23,26
PLT_RST# 9,17,18,21,26
+V3.3
C642
Mini-Card
PCI_C/BE#[0..3]
modify 09/28
D502 BAT54
C
A
modify 10/13
21 PCIE_LAN_WAKE#
D12
C
PCIE_LAN_WAKE#
PCIE_WAKE# 18
17,18,23 PCI_PAR
17,18,23 PCI_FRAME#
17,18,23 PCI_IRDY#
17,18,23 PCI_TRDY#
17,18,23 PCI_DEVSEL#
BAT54
A
17,18,23 PCI_STOP#
PCI_AD26
R263
17,18
17
17,18,23
17,18
PCI_REQ#0
PCI_GNT#0
PCI_PERR#
PCI_SERR#
5 PCICLK_1394
18 PM_CLKRUN#
SATA HDD
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3
73
60
47
34
PCI_CBE0#
PCI_CBE1#
PCI_CBE2#
PCI_CBE3#
PCI_PAR
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
Z2326
330
58
49
50
52
53
54
36
19
18
56
57
PM_CLKRUN#
16
12
PCI_CLK
PCI_CLKRUN#
85
21
13
PCI_RST#
PCI_PME#
PCI_INTA#
PCI_PME#
SATA_TXP0
SATA_TXN0
16
16
SATA_RXN0
SATA_RXP0
S1
S2
S3
S4
S5
S6
S7
modify 09/09
*1u/10V_0603
X7R
1394_XIN
XO
1394_XOUT
R1
119
R0
118
C176
C175
8.2p/50V
NPO
8.2p/50V
NPO
Close to pin
6.34K_1%
R273
C191
1394_AGND
FILTER1
TPBIAS0
TPA0+
TPA0TPB0+
TPB0TPBIAS1
TPA1+
TPA1TPB1+
TPB1-
116
115
114
113
112
125
124
123
122
121
1u/10V_0603
Y5V
0.1u/10V
X7R
R276
R277
56.2_1%
56.2_1%
TPBIAS0
TPA0+
TPA0TPB0+
TPB0C186
0.1u/10V
X7R
R264
1K
R269
1K
23
23
23
23
R282
56.2_1%
56.2_1%
C195
R286
220p/50V
NPO
5.11K_1%
99
98
97
TEST0
TEST1
TEST2
TEST3
TEST8
TEST9
105
104
102
101
95
94
REG18
REG18
30
93
1394_AGND
C180 0.1u/10V X7R
C198 0.1u/10V X7R
R293
390K
1394_AVCC3
CYCLEIN
CYCLEOUT
87
86
R304
R303
4.7K
10K
+V3.3S
TEST16
TEST17
11
10
R202
R203
10K
10K
10K
10K
10K
CPS
TPA0+
TPA0TPB0+
TPB0-
DEL L22
R287
106
C
L19
1394_PVCC3
CNA
96
R300
GPIO3
GPIO2
89
90
R305
R306
SDA
SCL
92
91
SDA
SCL
REG_EN
1394_PGND
G_RST#
14
+V3.3S
QT1608RL060HC_3A_0603
C174
0.1u/10V
X7R
L18
1394_PGND
QT1608RL060HC_3A_0603
R313
*47K
+V3.3S
PCI_RST#
C199
0.1u/10V
X7R
+V3.3S
1394_PGND
C202
C181
C192
C185
C197
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/10V
X7R
1394_AGND
+V3.3S
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
C622
PC0
PC1
PC2
17
23
33
44
55
64
68
75
83
103
CON509
16
16
XI
C177
PCI_REQ#
PCI_GNT#
PCI_PERR#
PCI_SERR#
V_HDD
Y4
24.576MHz_SMT
FILTER0
PCI_PAR
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_IDSEL
PCI_PERR#
PCI_SERR#
PCI_RST#
TSB43AB22A
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
17,18,23,26 PCI_RST#
17,23 PCI_PME#
17,18 INT_PIRQC#
+V3.3S
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
84
82
81
80
79
77
76
74
71
70
69
67
66
65
63
61
46
45
43
42
41
40
38
37
32
31
29
28
26
25
24
22
PCI_AD26
0.1u/10V
X7R
PCIE_MINI_WAKE#
120
108
107
2
1
modify 09/15
10K
+V3.3S
PLLVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
Mechanical Key
5 PCIE_CLK_MINI_CARD
5 PCIE_CLK_MINI_CARD#
U11
PLLGND
17 PCIE_TXP3_M_C
17 PCIE_TXN3_M_C
PCI_AD[0..31]
AVDD
AVDD
AVDD
AVDD
AVDD
IEEE-1394
+V3.3
GND
+V1.5
LED_WPAN#
LED_WLAN#
LED_WWAN#
GND
USB_D+
USB_DGND
SMB_DATA
SMB_CLK
+V1.5
GND
+V3.3AUX
PERST#
W_DISABLE#
GND
17,23
1394_PVCC3
0.1u/10V
X7R
CON512
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GND
PETp0
PETn0
GND
GND
PERp0
PERn0
GND
UIM_C4/Reserved
UIM_C8/Reserved
1394_XIN
1394_AVCC3
C650
*10u/10V_0805
Y5V
78
62
48
35
20
10u/6.3V_0805
X5R
1394_XOUT
100mA
VDDP
VDDP
VDDP
VDDP
VDDP
C651
+V3.3S
AGND
AGND
AGND
AGND
ANGD
AGND
AGND
17,23
PCI_C/BE#[0..3]
C645
0.1u/10V
X7R
PCI_AD[0..31]
109
110
111
117
126
127
128
MINI_CARD
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
+V1.5S
100
88
72
59
51
39
27
15
+V5S
modify 09/28
L20
C666
80 mil
C595+
C612+
4.7u/10V_0805
Y5V
4.7u/10V_0805
Y5V
QT1608RL060HC_3A_0603
L21
C182
C178
L510
QT1608RL060HC_3A_0603
4.7u/10V_0805
Y5V
1394_AVCC3
QT1608RL060HC_3A_0603
V_HDD
0.1u/10V
X7R
0.1u/10V
X7R
1394_AGND
Close to Pin 59,62,64,65
C605
0.1u/10V
X7R
+V3.3S
GND1
GND2
+V3.3S
SATA_CON
R301
R302
10K
10K
SDA
SCL
modify 10/13
modify 10/14
H1
C315D174
H2
C315D174
H14
C237D107
H20
H6
S241X276D107 C315D107
modify 10/13
H21
C315D107
H10
C315D107
H5
C197D107
H501
C100B210D60
H26
C100B210D60
modify 10/13
modify 10/13
H500
H3
C126B210D126 C315D158
modify 10/12
H8
C315D158
H7
C315D158BS315
+V3.3S
H12
C197D126
H11
C197D87
H13
C197D87
H18
C197D87
H16
C197D87
SDATA
SCLK
WP
VCC
GND
A2
A1
A0
4
3
2
1
AT24C02
R299
H22
C158D158
U12
5
6
7
8
330
H503
C100B210D60
If an EEPROM is not implemented,then both
the SDAand SCL pins should be connected
GND with 220-ohm pull down resistors
M15
M12
M17
M501
M4
M506
M11
M504
M10
M505
M1
M6
M8
M503
M13
M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1
M502
M508
M2
M9
M3
M18
M7
M19
M5
M16
M500
M14
M507
M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1
A
modify 10/13
modify 10/13
modify 10/13
H24
C158D158
H23
C158D158
H25
C158D158
H502
C197D60
H504
C197D60
H27
C100B210D60

Title
IEEE-1394,Mini_card,SATA,HOL
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
22
of
32
USB
modify 09/30
TV-OUT 1394 CONN
USB_P4USB_P4+
1
3
5
7
9
11
13
15
17
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0
15 TV_Y_DACB_OUT
15 TV_C_DACC_OUT
D
+V5S
2
4
6
8
10
12
14
16
18
TPA0+
TPA0-
22
22
TPB0+
TPB0-
22
22
IO BD CONN
C657
PIN NC3~4=GND POWER
C658
*22p/50V
NPO
*22p/50V
NPO
13" IO BD:USB , TV , 1394

14" IO BD:USB*2 , TV , 1394
17,22 PCI_C/BE#[0..3]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
17,18,22 PCI_DEVSEL#
17,18,22 PCI_FRAME#
17,18,22 PCI_IRDY#
5 PCI_CLK_PCMCIA
LAN CONN
CLKRUN# Pull-Low in PCMCIA Board.
CON8
17,22 PCI_AD[0..31]
CON507
17
17
CON9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
17,18,22 PCI_TRDY#
17,18,22 PCI_STOP#
17,18,22 PCI_PAR
17,18,22 PCI_PERR#
17,18 PCI_REQ#1
17
PCI_GNT#1
17,18,22,26 PCI_RST#
17,22 PCI_PME#
25
CARD_SPK
18
PM_RI#
18,26 INT_SERIRQ
17,18 INT_PIRQA#
17,18 INT_PIRQE#
R600
R599
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Z1808
0
*0
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
17,22 PCI_AD[0..31]
+V3.3S
C653 +V5S
+V12S
*0.1u/10V
X7R
CARD BUS-1
C654
C655
*0.1u/10V
X7R
*0.1u/10V
X7R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CARD BUS-2
CON505
21
21
TXD+_0
TXD-_0
21
21
TXD+_1
TXD-_1
1
3
5
7
9
Change Package for SMT

2
4
6
8
10
TXD+_2
TXD-_2
21
21
TXD+_3
TXD-_3
21
21
PCMCIA CONN
LAN CONN
PIN NC3~4=GND POWER
C
V_CDROM
CD-ROM
V_CDROM
modify 10/17
modify 10/17
CON501
25
CD_L
25
CDGND
17,18,22,26 PCI_RST#
R551
+V5S
U505
17
USB_P0_ON#
USB_P0USB0-
USB_P0-
0
1
2
3
4
0
BE1#
A1
B1
GND
VCC
BE2#
B2
A2
8
7 USB_P0_ON#
6 USB0+
5 USB_P0+
USB_P0_ON# 26
C570
USB_P0+ 17
C2
1000p/50V
X7R
modify 10/06
R28
0_0603
CDGND
*0.1u/10V
X7R
*SN74CBT3306PWR
R2
R8
R27
CDGND
16
16
16
16
R3
16
16
10K
16
16
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0
16
16
16
16
16
CDACT# 16
IDE_PDIOW#
IDE_PDIORDY
INT_IRQ14
IDE_PDA1
IDE_PDA0
IDE_PDCS1#
0
0_0603
0
IDE_RST#
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0
IDE_PDIOW#
IDE_PDIORDY
INT_IRQ14
IDE_PDA1
IDE_PDA0
IDE_PDCS1#
A
D2
BAS16
S_M/S_SET
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
R5
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15
IDE_PDDREQ
IDE_PDIOR#
IDE_PDDACK#
CD_R
IDE_PDD8 16
IDE_PDD9 16
IDE_PDD10 16
IDE_PDD11 16
IDE_PDD12 16
IDE_PDD13 16
IDE_PDD14 16
IDE_PDD15 16
IDE_PDDREQ 16
IDE_PDIOR# 16
IDE_PDDACK#
R6
C3
10K
1000p/50V
X7R
CDGND
25
16
CD_DET
IDE_PDA2
IDE_PDCS3#
IDE_PDA2 16
IDE_PDCS3# 16
B
GND1
GND2
R550
+V5S
V_CDROM
L5
QT1608RL060HC_3A_0603
DVD_CON
80 mil
C34 +
4.7u/10V_0805
Y5V
+V5S
R545
*0_0603
modify 09/27
100K
G
POLY SW_1206
16
100K
USB5VA_ON
USB_POWER
Q509
2N7002
G
S
26
USB0USB0+
C565
CD_LED#
100p/50V
NPO
CD_LED#
CDACT#
+V3.3S
Q5
CON506
R546
0.1u/10V
X7R
R44
AO3413L
S
C32
18,26 PM_SLP_S3#
Q508
S500
+V5A
C36 +
4.7u/10V_0805
Y5V
1
2
3
4
5
6
7
8
2N7002
INT_IRQ14
R515
4.7K
IDE_PDIORDY
R514
4.7K
CD_DET
R31
10K
S_M/S_SET
R58
470
USB BD CONN

Title
CD-ROM/PCMCIA/IO/LAN/USB
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
23
of
32
LV_LOCK
H_VID0
S
R350 1
SMART POWER
PM_VID0
2 *0
S
D
D
Q79
2N7002
G
Q78
2N7002
D
EC_SMP4_50MV_EN#
VCORE
1.708
-0mV
1.676
-32mV
1.644
-64mV
LV_LOCK
Reduce 12.5mv~87.5mv
+_mV
modify 10/03
VID5 VID4 VID3 VID2 VID1 VID0
H_VID1
S
R351 1
1.580
-128mV
1.452
-256mV
1.548
1.532
1.516
1.484
1.420
1.388
1.356
1.308
1.292
0
0
0
Q81
2N7002
EC_SMP4_50MV_EN#
26 EC_SMP4_50MV_EN#
LV_LOCK
del
Q31,Q32,Q33,Q35,R174,R182
1.436
H_VID2
S
R352 1
Q82
2N7002
D
HH_VID2
2 *0
S
D
C
Q83
2N7002
G
PM_VID1
2 *0
Q80
2N7002
D
EC_SMP4_100MV_EN#
26 EC_SMP4_100MV_EN#
VID5 VID4 VID3 VID2 VID1 VID0
+_mV
VCORE
1.276
1.260
1.228
1.196
1.164
1.116
1.100
1.036
1.020
1.004
0.988
0.972
0.956
0.844
0.716
R321
R322
R323
R324
R325
R326
R327
H_VID6
H_VID5
H_VID4
H_VID3
H_VID2
H_VID1
H_VID0
*0
*0
*0
*0
*0
*0
*0
PM_VID6
PM_VID5
PM_VID4
PM_VID3
PM_VID2
PM_VID1
PM_VID0
30
30
30
30
30
30
30
+VCCP
+VCCP
RP13
8P4RX4.7K
RP11
8P4RX4.7K
1
2
3
4
1
1
7
7
7
7
7
7
7
5
6
7
8
4
3
2
1
8
7
6
5
+V5S
C168
modify 10/03
7
7
7
H_VID5
H_VID4
H_VID3
HH_VID2
H_VID5
H_VID4
H_VID3
FROM EC CONTROLLER
26
26
26
26
+V3.3S
24
1A1
1A2
1A3
1A4
1A5
1B1
1B2
1B3
1B4
1B5
2
5
6
9
10
14
17
18
21
22
2A1
2A2
2A3
2A4
2A5
2B1
2B2
2B3
2B4
2B5
15
16
19
20
23
CPUVID_EN# 1
ECVID_EN# 13
4.7K
PM_VID5
PM_VID4
PM_VID3
PM_VID2
30
30
30
30
1OE#
2OE#
12
Q34
2N7002
G
S
26 CELERON_EN#
GND
D
LV_LOCK#
SN74CBT3384A
G
2N7002
S
C
A
R186
1
1
C
D10
100
100
100
100
Q85
1K
2
H_VID4
Q84
2N2222
del
R191,R194,R188
BAT54
R267
R246
R206
R205
LV_LOCK
R354
10K
BAT54
A
+V5S
10K
R355
D11
C
EC_VID5
EC_VID4
EC_VID3
EC_VID2
TO PWM CONTROLLER
( CPU V_CORE PWM)
3
4
7
8
11
R353
+V3.3S
+VCCP
H_VID5
0.1u/10V
X7R
VCC
U10

Title
Smart_power
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
24
of
32
CRT CON
AUDIO CONN
Design guind is 2.2K ohm.
R74
R541
modify 10/13
CON7
+V2.5S
26
CHG_R#
26
SCROLL#
26
CHG_G#
26
LID#
26
NUM#
26 SILENT_LED#
26
CAPS#
22,26 RF_LED_ON#
26
PWR_LED#
26
AMP_MUTE#
16
IDE_ACT#
D3
R73
R80
**4.7K
**4.7K
Q25
**2N7002
R542
R540
3.01K_1% 3.01K_1%
G
15,20,26 MXM_VO-ON#
S
D
Q22
**2N7002
9 CRT_DDC_DATA
+V5S
Q18
**2N7002
R69
R71
MIC CON
2N7002
1K
1K
CON510
INTMIC
INTMIC_GND
1
2
DDC_DATA
DDC_CLK
MIC_CONN
modify 10/13
Q20
2N7002
+V3.3
15,20,26 MXM_VO-ON
Q23
D
Q19
**2N7002
9 CRT_DDC_CLK
BAT54
G
+V2.5S
TP109
TP110
DK_CRT_DDC_DATA
DK_CRT_DDC_CLK
+V2.5S
R337
4.7K
change
CODEC_14MHZ net
to GND
LID#
R316
R317
R297
180
220
180
R296
R294
R290
R289
R285
220
220
220
220
220
SW_CHG_R#
SW_SCROLL#
SW_CHG_G#
LID#
SW_NUM#
SW_SILENT_LED#
SW_CAPS#
SW_BTLED_ON#
SW_PWR_LED#
R280
220
SW_IDE_ACT#
26
RF_OFF#
23
CD_R
23
CDGND
23
CD_L
16 ACZ_SDATAIN1
16 ACZ_SDATAIN0
16 ACZ_SDATAOUT
16
ACZ_RST#
16
ACZ_SYNC
16 ACZ_BITCLK
+V12S
modify 09/30
INTMIC
INTMIC_GND
L22
QT1608RL060HC_3A_0603
+V5A
PC_BEEP
+V3.3
17
17
modify 09/28
USB_P1+
USB_P1+V5S
modify 09/28
** must install
MUST INSTALL:
1.Q45,Q47,Q49,Q50 from NC to 2N7002
2.R331,R333 from NC to 4.7K
23
CARD_SPK
26
BTL_BEEP
18
ACZ_SPKR
R347
10K
R346
10K
R345
10K
17
17
BAS16
A
C
D9
R270
10K
REMOVE:
1.R436,R437 from 0 to NC
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
USB_P5+
USB_P5-
PC_BEEP
C187
C189
*0.01u/16V
X7R
C190
FPC_LED_CONN
C184
*0.01u/16V
X7R
Modify in R:B1
Modify in R:01
0.01u/16V
X7R
*0.1u/10V
X7R
modify 10/13
+V3.3S
0.1u/10V
C33 X7R
HSYNC L9
VSYNC L10
L6
L7
L8
15 OUT_CRT_RED
15 OUT_CRT_GREEN
15 OUT_CRT_BLUE
HS
VS
R
G
B
QT1608RL011
QT1608RL011
QT1608RL011
QT1608RL011
QT1608RL011
15 CRT_VSYNC_OUT
VSYNC
HS
VS
2
R
15 CRT_HSYNC_OUT
R
G
B
EMI ISSUE
modify 10/07
4
U3
TC7SH08FU
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PWRSW#
INSTANT_ON#
SILNET_ON#
SW_BTLED_ON#
SW_IDE_ACT#
SW_SILENT_LED#
SW_CHG_R#
SW_CHG_G#
SW_PWR_LED#
SW_CAPS#
SW_NUM#
SW_SCROLL#
+V3.3S
U4
TC7SH08FU
1
CON2
0.1u/10V
X7R
26
ADAP_I
27
PWRSW#
27 INSTANT_ON#
27 SILNET_ON#
Modify in R:01
+V3.3A
C24
HSYNC
C50
C53
C57
10p/50V
NPO
10p/50V
NPO
17
17
USB_P6+
USB_P6-
C71
+V5S
10p/50V
NPO
26
R67
RFLED_ON#
0.1u/10V
X7R
SW_RFLED_ON#
DDC_DATA
DDC_CLK
*220
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CRT CONN
PIN NC1~2=GND POWER

Title
CRT / AUDIO CONN
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
25
of
32
+V3.3A_RTC
+V3.3A
+V3.3A
+V3.3A
QT1608RL060HC_3A_0603
49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
AC_BATT
110
111
114
115
116
117
FCS
FRD
FWR
173
150
151
ROMCS#
ROMRD#
ROMWR#
DA0
DA1
DA2
DA3
99
100
101
102
FAN_CTRL0
FAN_CTRL1
ADC8/ANOTE
ADC9/CATHODE
93
94
DDR2_TEMP
PM_SLP_S5#
ADC0
ADC1
ADC2
ADC3
81
82
83
84
R588
R587
ADC4/GPE0
ADC5/GPE1
ADC6/GPE2
ADC7/GPE3
87
88
89
90
R586
0
SILNET_EC
MXM_PCIE_DET#
2
44
24
25
PWRSW_EC
LID#
RF_OFF#
PM_SLP_S3#
26
29
30
ADAP_IN
R348
IOPD4
GINT/IOPD5
TACH0/GPD6
TACH1/GPD7
41
42
62
63
PM_SLP_S4#
LED_R
LED_G
LED_B
GPA0/PWM0
GPA1/PWM1
GPA2/PWM2
GPA3/PWM3
GPA4/PWM4
GPA5/PWM5
GPA6/PWM6
GPA7/PWM7
32
33
36
37
38
39
40
43
GPI
SCROLL#
CAPS#
NUM#
SCROLL#
CAPS#
NUM#
CHGLED_R
31
+5V_ON
25 SILENT_LED#
25
PWR_LED#
SILENT_LED#
PWR_LED#
118
119
GPCF6/PS2CLK3
GPCF7/PS2DAT3
148
149
152
155
156
168
174
GPI0
GPI1
GPI2
GPI3
GPI4
GPI5
GPI6
modify 09/27
29
MXM_VO-DET
31
+3.3V_ON
29
+1.5VS_ON
+1.05VS_ON
CHGLED_G
R195
modify 10/06
30
VCORE_ON
DK_MXM_THERM#
TP564
20
LCDSW
25
AMP_MUTE#
24 EC_SMP4_50MV_EN#
AMP_MUTE#
24 EC_SMP4_100MV_EN#
23 USB_P0_ON#
31
+3.3VS_ON
27
SMBCLK0
27
SMBDAT0
31
48
54
55
69
70
75
76
105
3
4
27
28
153
154
162
163
164
SMBCLK0
SMBDAT0
+5VS_ON
32KI
R591
*20M_0603
GPH0
GPH1
GPH2
GPIO
GPH3
GPH4
GPH5
GPH6
GPH7 GPO
165
GPB7
158
CK32K
160
CK32KE
R592
Y500
32.768KHz_DIP
GPIO
GPIO
GPG4
GPG5
GPG6/LPC80HL
GPG7/LPCGPG7
GPB0/URXD
GPB1/UTXD
GPB2
SMCLK0/GPB3
SMDAT0/GPB4
WUI0/GPD0
WUI1/GPD1
WUI4/GPD2
GPIO
GPO
GPIO
GPO
CLOCKOUT/GPC0
GPC1/SMCLK1
GPC2/SMDAT1
GPC3
GPIO
WUI2/GPC4
GPC5
WUI3/GPC6
CLKOUT/GPC7
GPIO
17
35
46
122
159
167
137
29 +1.8V_DDR_ON
22,25 RF_LED_ON#
PWRSW/GPE4
WUI5/GPE5
LPCPD/WUI6/GPE6
CLKRUN/WUI7/GPE7
GPI
GPIO
*0.1u/10V
X7R
TP562
+V5S
+V5S
CON6
18
18
18
1
2
3
4
5
LED_R
LED_G
LED_B
LED_R
LED_G
LED_B
SMBCLK1
Q66
2N7002
S
SMBDAT1
*85205-05R
10p/25V
NPO
12p/50V
NPO
+V5A
TP561
G
4.7K
TP148
SMBCLK_GEN 5
modify 09/27
4.7K
4.7K
SMBDAT0
Q63
2N7002
S
SMBCLK0
TP147
+V3.3S
SILNET_EC 27
R288
R291
4.7K
4.7K
27
+V5S
+V3.3S
+V3.3A
0.1u/10V
X7R
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
VCC
32
O0
O1
O2
O3
O4
O5
O6
O7
13
14
15
17
18
19
20
21
+V3.3A
WE#
OE
CE
31
24
22
VSS
16
R173
CON502
C201
C643
C519
0.1u/10V
X7R
0.1u/10V
X7R
0.1u/25V_0603
X7R
PC513
22u/10V_1206 +
C1
1K
PC515
+ 10u/10V_1206
Y5V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
18
1
2
3
CPU_FAN
0.1u/10V
X7R
Y5V
ABC_0805
+V12S
PL502
5.11K_1%
QT1608RL060HC_3A_0603
100_1%
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
LPC_FRAME#
PCI_RST#
CLK_PCI_LPC
INT_SERIRQ
LDRQ#0
Z2626
Z2627
PC514
PR521
17,18,22,23 PCI_RST#
5 CLK_PCI_LPC
18,23 INT_SERIRQ
16
LDRQ#0
*4.7K
R166
ROMWR#
ROMRD#
ROMCS#
0~5V
+V12S
+V5A
LPC_CLK_48M
4.7u/10V_0805
Y5V
R172
+V3.3A
PQ503
A1797
C
VIN
DEBUG CONN(LPC BUS)
+ C156
0.1u/10V
X7R
Flash ROM
CON513
VCC_MCH_VRPWRGD
C157
*4.7K
PR520
modify 09/09
PM_SLP_S4# 18
ROMD0
ROMD1
ROMD2
ROMD3
ROMD4
ROMD5
ROMD6
ROMD7
4.7K
CPU_BSEL2_EC
PU500A
LM358
3
1
2
PC508
0.1u/10V
X7R
PR517
10K_1%
B
0~3.3V
PR511
100K
FAN_CTRL0
PR508
100K
*@53398-1490_MOLEX
PIN NC1~2=GND POWER
PWR_keep 27
MINI_RFON 22
PM_RSMRST# 18
CHG_ON 27
USB5VA_ON 23
+V3.3A
MXM_PCIE_DET# R584
+V3.3S
4.7K
R583
6
Z2620
CPU_BSEL1
Lo = 133Mhz
Hi = 100Mhz
Hi = 133Mhz
Lo= 100Mhz
T/P
4.7K
CPU FSB Select
IT8510E/NS97551
CPU_BSEL1_EC
TOCHPAD CONNECTOR
+V5S
Q514
2N3904
CON5
1K
TP_BT
C116
*10p/25V
NPO
C113
modify 09/09
TP_CLK
+V3.3S
C112
6
5
4
3
2
1
TP_BT
C120
*10p/25V
NPO
*0.1u/10V
X7R
C121
TP_DATA
TP_CLK
0.01u/16V
X7R
*10p/25V
NPO
T/P_CONN
RF_OFF#
Modify in R:B for ESD

R57
4.7K
A
2N7002
R606
modify 09/09
D
CHG_G#
R607
Q519
CHGLED_G
+V3.3A
Z2620
CPU_BSEL2
Lo = 133Mhz
Hi = 100Mhz
+V3.3S
CPU_BSEL2_EC
TP_BT
TP_DATA
TP_CLK
Q517
2N3904
R94
R93
R92
4.7K
4.7K
4.7K
1K
2N7002
Hi = 133Mhz
Lo= 100Mhz
4.7K
CPU FSB Select
S
S
MXM_VO-ON# 15,20,25
Title
modify 09/27
R334
R335
R336
Q515
*2N7002
+V5A
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
1
PR519
PWRSW_EC 27
LID#
25
RF_OFF# 25
PM_SLP_S3# 18,23
ADAP_IN
CPU FAN
CPU_THER_SMBCLK0 6
R585
*2N7002
*10K
100K
CPU_THER_SMBDAT0 6
+V5S
MXM_VO-ON 15,20,25
R349
D
25
R315
U506
MUST INSTALL:
R1014,R1016,R1017,R1018, R1020,R1023
form NC to 0.
R1001,R1002 form NC to 4.7K
REMOVE:
R1025,R1012 form 47K to NC
R1013,R1015,R1019,R1021, R1022,R1024
form 0 to NC
R645 for 4.7K to NC
Q57
2N7002
VR_THERM# 30
CPU_BSEL1_EC
BTL_BEEP 25
TP570
EC_VID2 24
EC_VID3 24
EC_VID4 24
EC_VID5 24
CELERON_EN# 24
PM_PWRBTN# 18
0
47 R598
SMBCLK1
169
SMBDAT1
170
171
MINI_RFON
172
175
176
1
+V5S
BATT_TEMP 27
ADAP_I
25
PLT_RST# 9,17,18,21,22
Q518
D8
C
FLASH ROM
ROMA0
ROMA1
ROMA2
ROMA3
ROMA4
ROMA5
ROMA6
ROMA7
ROMA8
ROMA9
ROMA10
ROMA11
ROMA12
ROMA13
ROMA14
ROMA15
ROMA16
ROMA17
ROMA18
IF USE NS97551
S DK_MXM_SMB_DAT
D
G
LRST1#
8P4RX4.7K
4 SMBCLK0
3 SMBDAT0
2 SMBCLK1
1 SMBDAT1
MUST INSTALL:
R1025,R1012 form NC to 47K
R1013,R1015,R1019,R1021, R1022,R1024
form NC to 0
R645 for NC to 4.7K
REMOVE:
R1014,R1016,R1017,R1018, R1020,R1023
form 0 to NC.
R1001,R1002 form 4.7K to NC
ADAP_I
*10K
Q516
R593
MXM_VO-DET
R318
4.7K
Q69
*2N7002
S DK_MXM_SMB_CLK
Q70
*2N7002
DDR2_TEMP 14
PM_SLP_S5# 18
10K
CHGLED_R G
BAT54
A
+V3.3S
IF USE ITE8510E
R319
+V3.3S
CHG_R#
+V5S
+V5S
RP508
5
6
7
8
+V3.3A
MXM_VO-ON 15,20,25
+V5S
4.7K
15,20,25 MXM_VO-ON
modify 09/27
10K
R594
*4.7K
*4.7K
*4.7K
4.7K
4.7K
C200
TP_DATA
R616
25
modify 10/06
4.7K
4.7K
SMBDAT_GEN 5
BRIGHTADJ 20
CHG_I
27
+V3.3A
R615
R312
R311
R149
R148
R147
R146
R145
EC_HRCIN#
+V3.3S
Q67
2N7002
change footprint to XS2-1

C646
*4.7K
*4.7K
*4.7K
*4.7K
EC_HA20GATE
EC_HRCIN#
Q64
2N7002
16,18 H_RCIN#
+V3.3S
modify 09/15
C644
4.7K
R307
R309
R308
R610
EC_HA20GATE
25
25
25
INSTANT_EC
EC_EXTSMI#_A
H_A20GATE
C196
NC
NC
LPCPROG
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RFLED_ON#
INSTANT_EC
GPI
AGND
25
27
GPIO
11
12
20
21
85
86
91
92
97
98
106
107
108
109
8
modify 10/06
IN
96
TP_BT
TP_CLK
TP_DATA
del R356,R357
PS2CLK0/GPCF0
PS2DAT0/GPCF1
PS2CLK1/GPCF2
PS2DAT1/GPCF3
PS2CLK2/GPCF4
PS2DAT2/GPCF5
GND1
GND2
GND3
GND4
GND5
GND6
GND7
TP563
Q65
2N7002
G
OUT
KEYBOARD_CON
18 PM_SYSRST#
Q68
*2N7002
R314
Embedded
Controller
ROMD0
ROMD1
ROMD2
ROMD3
ROMD4
ROMD5
ROMD6
ROMD7
*0
EC_EXTSMI#_A
LID#
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
ROMA0
ROMA1
ROMA2
ROMA3
ROMA5
EC_SCI#_A
161
95
138
139
140
141
144
145
146
147
16
R292
4.7K
KEY_0
KEY_1
KEY_2
KEY_3
KEY_4
KEY_5
KEY_6
KEY_7
KEY_8
KEY_9
KEY_10
KEY_11
KEY_12
KEY_13
KEY_14
KEY_15
FD0
FD1
FD2
FD3
FD4
FD5
FD6
FD7
IT8510E
EC_EXTSMI#
*0
R340
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KEY_15
KEY_14
KEY_13
KEY_12
KEY_11
KEY_10
KEY_9
KEY_8
KEY_7
KEY_6
KEY_5
KEYIN0
KEYIN1
KEYIN2
KEYIN3
KEY_4
KEY_3
KEYIN4
KEYIN5
KEYIN6
KEYIN7
KEY_2
KEY_1
KEY_0
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
KB Matrix Interface
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Q61
*ASM809S
2
3
*4.7K
18
R295
EC_SCI#_A
71
72
73
74
77
78
79
80
GPO
CON3
LRST1#
R298
EC_SCI#
KEYIN0
KEYIN1
KEYIN2
KEYIN3
KEYIN4
KEYIN5
KEYIN6
KEYIN7
Power Supply
18
R339
Q75
2N7002
GPD3/ECSCI
GPB5/GA20
GPB6/KBRST
ROMA0
ROMA1
ROMA2
ROMA3
ROMA4
ROMA5
ROMA6
ROMA7
ROMA8
ROMA9
ROMA10
ROMA11
ROMA12
ROMA13
ROMA14
ROMA15
ROMA16
ROMA17
ROMA18
EC_EXTSMI#
*0
31
5
6
124
125
126
127
128
131
132
133
143
142
135
134
130
129
121
120
113
112
104
103
18
R338
EC_SCI#_A
EC_HA20GATE
EC_HRCIN#
+V3.3A
FA0
FA1
BADDR1/FA2
BADDR0/FA3
FA4
SHBM/FA5
FA6
FA7
FA8
FA9
FA10
FA11
FA12
FA13
FA14
FA15
FA16
FA17
FA18
FA19
EC_SCI#
PWUREQ
ECSMI
0.1u/10V
X7R
18
*4.7K
23
EC_EXTSMI#_A 22
C203
SERIRQ
LFRAME
LPCCLK
WRST
0.1u/10V
X7R
AVCC
7
9
18
19
+ C194
4.7u/10V_0805
Y5V
LRST1#
R310
+V3.3A
LAD3
LAD2
LAD1
LAD0
Flash Interface
LPC_FRAME#
10
13
14
15
4.7u/10V_0805
Y5V
0.1u/10V
X7R
VBAT
VCC
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
System & LPC Bus
16 LPC_AD[0..3]
0.1u/10V
X7R
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
16
U507
0.1u/10V
X7R
34
45
123
136
157
166
0.1u/10V
X7R
C641
+ C652
C173
18,23 INT_SERIRQ
16 LPC_FRAME#
5 PCI_CLK_LPC
+V3.3A
STRAP define
modify 09/15
*QT1608RL060HC_3A_0603
C648
C649
C656
+V3.3A
QT1608RL060HC_3A_0603
L512
K/B CONTROLLER
+V5S
L16
+V3.3S
L511
100K
100K
100K
PWRSW_EC
INSTANT_EC
SILNET_EC
IT8510E & KB&BIOS & TP & FAN
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
26
of
32
PF500
1206/5A/35V
C
PR16
100K
VADAP
DTC
PR2
2.2K_0805
Footprint
12
1.0A
12.641V
0A
12.608V
16
15
FB
2IN+
2IN-
4
5
6
3
2
1
PL500
15UH_CDRH104R
PR506
Footprint
PC501
6.81K_1%
PC505
PD501
SK34A
1000p/50V
X7R
PR522
220K_1%
PC512
100u/25V_EC_6.3X7
PR11
40mR_1/1W_2512
1
2
4.7u/25V_1206
PQ1
2N2907
B
ADAPTOR_I
PR8
576_1%
4
PC1
470p/50V
X7R
PR515
100K_1%
PJP501
3mm
CHG_GND
PJP502
CLOSE
PR516
16.2K_1%
PQ5
RSS090N03
PR13
39K
26
PQ502
SI4835
DTC
7
13
PR523
300K_1%
DTC
CT
RT
5
6
7
8
8
9
11
10
10K
GND
OUT-CTRL
10K
PR505
CHG_GND
C1
E1
C2
E2
PR504
10K_0603
PC503
0.01u/16V X7R
PC502
0.01u/16V X7R
REF
1IN+
1IN-
PQ4
2N2222
0.1u/25V_X7R_0603
14
1
2
CHG_GND
12.675V
100K_1%
SET_I :
2.0A
PC2
PU1
TL594
1u/10V_0603
Y5V
VCC
CHG_GND
3.2V = 2.0A
1.6V = 1.0A
0.233V = 150mA
100u/25V_EC_6.3X7
PR4
PC3
PR18
CHG_ON
26
PQ8
2N7002
D
1u/25V_0805_Y5V
VADAP
VADAP/6A
PD500
SK34A
+ PC509
PC504
1
2
3
CHG_I
PR12
+V3.3A
PJP500
3mm
PC4
PR503
100K_1%
1K_1%
0.1u/10V
X7R
8
7
6
5
PR17
56K
PQ7
2N7002
4.5A
1.97V
5A
2.188V
C
ADAP_IN 26
26
PR7
56K
PQ3
2N7002
CHG_ON
PR6
56K
1.532V
1.752V
PR15
560K
G
PR9
100K
3.5A
4.0A
PR507
10M
CHG_GND
1.099V
1.316V
VIN
2.5A
3.0A
LDO5
PR14
100K
PR94
56K
+V3.3A
PR89
PQ25
2N2907
Battery_CON
PD502
SK54
C
EN5
VIN
PR513
8
7
6
5
BATT_TEMP 26
PC511
220p/50V
NPO
PC510
220p/50V
NPO
PC506
220p/50V
NPO
PQ20
PQ6
SMBCLK0 26
SMBDAT0 26
100
*FDS4435
PR514
220K
DC IN
PR10
330_0603
2N7002
1
2
3
PR79
56K
SILNET_EC 26
PQ22
2N7002
S
VADAP
PR5
22K_0603
PR85
56K
PD1
SK54
CON1
1
2
3
4
5
6
28
PR90
10K
PR512
100
INSTANT_EC 26
1
2
3
4
5
6
7
8
9
10
GND1
GND2
10K
0.1u/25V_X7R_0603
PL501
QT4516RL060HC_6A_1806
CON500
PR518
100K
PC507
C
PD12
DAP202K C
A1
PC529
SILNET_ON# 25
A2
INSTANT_ON# 25
PQ28
0.1u/25V_X7R_0603
PR97
56K
DC CONN
2N7002
S
PWRSW_EC 26
PQ2
PR502
*10K
1
2
3
PD15
A
*SI4835
PWRSW# 25
S
G
BAS16
PQ501
8
7
6
5
2N7002
PR510
56K
VADAP
G
S
PZ1
*UDZ16B
56K
PR500
*10K
PQ21
D
B
PQ500
*2N2222
2N7002
G
PR1
*10K
PC500
*0.1u/25V_X7R_0603
PWR_Keep 26
PR3
*1K
PR509
PR501
*2.2K
PR101
100K

Title
DC IN/BATT IN/Charger
Size
Document Number
Date:
SCHEMATIC1
1
Rev
B
M31EI1
Sheet
27
of
32
PJP8 TOPOPEN-3MM
VIN
1
PR75
PC61
5
6
7
8
EN3
UGATE3
26
PGOOD
LGATE3
25
LDO3
24
PGND
23
5
6
7
8
21
19
11
FB5
UGATE5
18
12
COMP5
PHASE5
17
13
EN5
BOOT5
16
OUT5
15
14
CS5
PC76
0.1u/25V_X7R_0603
PR87
PC72
ISL6232
4.7u/10V_0805
Y5V
PC79
0.1u/25V_X7R_0603
4.7u/10V_0805
Y5V
PR537
PC526
100u/25V_EC_6.3X7 10K_0805
+V5A
PL507
6uH/27mR
PC530 PC528
PR98
PJP506 OPEN-SMALL
2
+V5A/6A
SOP-8
1K_1%
PR96
+
PC82
SK14
RSS090N03
+V12A
390u/6.3V_OSC_DIP_8x11.5
PQ27
PC67
PR95
2.2_0603
*1u/10V_0603
Y5V
1:2.2
PC75
390K
4.7u/25V_1206
X5R
4.7u/25V_1206
X5R
PD14
4
*47p
+
ES1D_SMA
270p/50V
X7R
C
4
+V12A/100mA
PJP505 OPEN-SMALL
1
2
PC63
PC66
PQ24
PC74
PC73
VCC
20
VCC
RSS090N03
LGATE5
GND
REF
PR536
160_0805
Footprint
PD503
LDO5
9
10
PC524
PR81 10_0603
PR86
0
REF
22
3
2
1
PC71
0.22u/10V_0603
X7R
VIN
LDO5
0.1u/10V
560u/4V_OSC_DIP_8x11.5
X7R
SKIP#
PC533
4.7u/10V_0805
SOP-8
SHDN#
RSS090N03
5
6
7
8
PC525
SK14
3
2
1
FB3
SHDN#
SKIP#
PJP504 OPEN-SMALL
2
4.7uH/22mR
PD9
6
PR83
COMP3
PQ19
4
LDO3
5
6
7
8
EN3
+V3.3A +V3.3A/6A
0.68u/16V_0603
X7R
PL506
1K_1%
270p/50V
X7R
PC60
27
CLOSE
TO IC
28
PHASE3
3
2
1
BOOT3
CS3
OUT3
PR71
RSS090N03
0.1u/25V_X7R_0603
1
PR78
10K_0603
*47p
PC69
PC65
4
4.7u/25V_1206
X5R
4.7u/25V_1206
X5R
PC68
PR76
2.2_0603
PU6
*1u/10V_0603
Y5V
PQ18
3
2
1
+V3.3A
PR80
300K
PC64
PC59
1.5K_1%
DEL PD10
0.68u/16V_0603
X7R
PR99
PC527
390_0805
4.7u/10V_X5R_0805
0.1u/10V
X7R
619_1%
VCC
PD11
A
PC70
DEL PD10
BAT54
C
CLOSE
TO IC
0.1u/25V_X7R_0603
10K PR77
EN3
PR84
EN5
27
0
PR100
SKIP#
100K
PC62
+V5S
1000p
LDO3
PR82
PR91
200K_0603
100k
PR102
SHDN#
Operate Mode
PQ23
2N7002
2N7002
PWM
REF
Ultrasonic
GND
Pluse Skip
10k
AUX_OFF# 6,31
G
S
VCC
PQ26
SKIP#
PR88
200K_0603
PJP10
2
1
CLOSE
SHDN#
EN3
EN5
LOW
LOW
LOW
High
LDO3
LDO5
OFF
OFF
3.3V Buck
OFF
OFF
ON
ON
OFF
OFF
5V Buck
High
LOW
High
ON
ON
OFF
ON
High
High
LOW
ON
ON
ON
OFF
High
High
High
ON
ON
ON
ON
High
High
REF
ON
ON
High
REF
High
ON
ON
ON after 3.3V up
ON
ON after 5V up
ON

Title
+V3.3V +V5V +V12A
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
28
of
32
PJP5 TOPOPEN-3MM
2
UGATE2
UGATE1
BOOT2
BOOT1
1000p/50V
X7R
PR58
1.8K
22
ISEN2
ISEN1
21
EN2
EN1
VOUT1
20
VOUT2
19
VSEN2
18
OCSET2
17
SOFT2
13
DDR
14
VIN
1
2
3
PR67
PR64
6.81K_1%
*0
PC54
0.01u/16V
X7R
PR72
100K
PC57
0.01u/16V
X7R
PC56
VSEN1
10
11
SOFT1
12
PG2/REF
16
PG1
15
PC49
0.1u/10V
X7R
0.1u/25V_X7R_0603
C
PR68
10K_1%
modify 09/27
PR63
0
5
6
7
8
PQ9
RSS090N03
PR59
2K
4
modify 09/15
OCSET1
modify 09/15
PC52 0.1u/25V_X7R_0603
PJP1
OPEN-SMALL
2
PC516
PD2
SK14
23
+V1.05S
4.7u/25V_1206
6*6 10X10
FOOTPRINT
PL503
2.2UH
820u/2.5V_OSC_DIP_8x11.5
PHASE1
24
PC8
PC523
4.7u/10V_X5R_0805
PHASE2
PC522 PC48
PC51 0.1u/25V_X7R_0603
PQ17
RSS090N03
25
PC7
1000p/50V
X7R
PC531
4.7u/10V_X5R_0805 330u/2V
PGND1
3
2
1
LGATE1
PGND2
1
2
3
8
7
6
5
PD6
SK14
LGATE2
26
27
+V1.05S/8A
PQ10
RSS090N03
28
VCC
GND
PL505
2.2UH
OPEN-SMALL
PJP503
1
2
PC50
1u/10V_0603
Y5V
PD8
BAT54
5
6
7
8
PU5
ISL6227
3
2
1
+V1.5S
PD7
BAT54
PQ16
RSS090N03
8
7
6
5
PC47
4.7u/25V_1206
6227_AGND
+V1.5/6A
PC53
1u/10V_0603
Y5V
modify 09/27
6227_AGND
PR74
2.2_0603
6227_AGND
PR61
2.2_0603
+V5
VIN
modify 09/28
PC58
0.01u/16V
X7R
PR65
*0
PC55
0.01u/16V
X7R
PR69
1.69K_1%
PR73
82K
PR66
0
PR70
10K_1%
6227_AGND
PJP9
26
6227_AGND
+1.5VS_ON
PR60
100K
PR62
100K
2
PR40
2.2_0603
PC32
1u/10V_0603
Y5V
PC29
4.7u/25V_1206
+V3.3S
1
8
7
6
5
PD4
SK14
LGATE2
27
PGND1
PGND2
26
PC28 0.1u/25V_X7R_0603
PQ14
RSS090N03
1000p/50V
X7R
PR38
modify 09/23
2K
UGATE2
24
BOOT1
BOOT2
23
ISEN1
ISEN2
22
EN1
EN2
21
VOUT2
20
VOUT1
10
VSEN1
11
OCSET1
12
SOFT1
*0
13
DDR
PC37
0.01u/16V
X7R
PR52
100K
PC46
0.01u/16V
X7R
PC45
14
VIN
VSEN2
19
18
SOFT2
17
PG2/REF
16
PG1
15
PR33
10K_1%
VIN
3
9
REFEN
GND
GND
5
6
7
8
VCNTL
VCNTL
VCNTL
VCNTL
PC15
0.1u/10V
X7R
+V0.9
PJP3
4
OUTPUT
OPEN-SMALL
RT9173B
PC26
0.01u/50V_0603
Y5V
+V3.3S
40mil
PC19
10u/6.3V_0805
X5R
PR29
10K_1%
+V3.3A
25 mil
+V5S
PC21
0.1u/10V
X7R
0.1u/25V_X7R_0603
PR47
10K_1%
PC16
1u/10V_0603
Y5V
OCSET2
+0.9V/1A
PU2
25
UGATE1
1
2
3
PR48
PR45
10K_1%
PHASE2
PHASE1
PC22
4.7u/10V_X5R_0805
820u/2.5V_OSC_DIP_8*9
28
LGATE1
4
PC532
VCC
modify 09/28
PC17
GND
1
2
3
to DIMM
40 mil
PU4
ISL6227
+V1.8_DDR +V1.8_DDR layout

PD5
BAT54
PQ15
RSS090N03
8
7
6
5
DDR2_AGND
+V1.8_DDR
PL1
PJP2
OPEN-SMALL 2.2UH
1
2
1
PR53
2.2_0603
DDR2_AGND
+V5
1
CLOSE
PJP4 TOPOPEN-3MM
VIN
+V1.8S/7A
26 +1.05VS_ON
+2.5VS/0.6A
PU7
PR44
0
PC80
1u/10V_0603
Y5V
DDR2_AGND
PR93
3.16K_1%
26 +1.8V_DDR_ON
VIN
REFEN
9
2
GND
GND
VCNTL
VCNTL
VCNTL
VCNTL
5
6
7
8
PC81
0.1u/10V
X7R
+V2.5S
PJP11
OUTPUT
OPEN-SMALL
2
RT9173B
25mil
PR41
100K
PJP6
A
PC78
1u/10V_0603
Y5V
PC77
10u/6.3V_0805
X5R
PR92
10K_1%
CLOSE

Title
1.5VS/1.05V/1.8V/0.9V/2.5VS
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
29
of
32
VIN
+V3.3S
+V3.3S
PR25
10_0603
PR43
1.91K
PM_DPRSLPVR_I
PR540
500
9,18 PM_DPRSLPVR
2
1
PR527
10
PC34
1u/10V_0603
PC23
0.1u/25V_X7R_0603
PR538
*100K
+V5S
VR_PWRGD 18
40
PC41
*10n
24
Panasonic
24
ERT-J0EV474J
2
PR524
0
PR526
0
PR525
0
PR20
0
PR23
0
PR24
0
PR26
0
PR28
0
PR32
0
PR36
0
PR39
0
PM_VID0
PM_VID1
24
PM_VID2
24
PM_VID3
24
PM_VID4
24
PM_VID5
24
PM_VID6
26 VCORE_ON
PM_DPRSLPVR_I
100K
6,16 H_DPRSTP#
5 VTT_PWRGD#
+V3.3S
PR539
+V5S
SOFT
VCCP
27
28
VID0
29
VID1
UGATE
23
30
VID2
BOOT
22
31
VID3
32
VID4
33
VID5
34
VID6
35
VR_ON
36
DPRSLPVR
37
DPRSTP#
38
CLK_EN#
PHASE
24
LGATE
26
VSSP
25
PC519
4.7u/25V_1206
PC521
4.7u/25V_1206
+VCC_CORE
2
PC6
PC11
PC517
PC12
PC518
+
330u/2V
PD3
330u/2V
*330u/2V
330u/2V
SK34A
1
PC18
4.7u/10V_0805
X7R
PC9
PC520
4.7u/10V_X5R_0805
330u/2V
PR22 2.2
PC14
0.22u/16V_0603
X7R
modify 10/13
*10K
2 PR31
7.68K_1%
1 PR34
0
PC43
*1000p
PR46
2.21K_1%
11
PC38
560p
PR51
4.99K_1%
OCSET
PR56
8.2K_1%
VSUM
17
VSUM
VDIFF
PC24
10
PR54
374K_1%
PR27
3.57K_1%
PR529
10K_5% NTC
Panasonic
ERT-J1VR103J
COMP
PC40
47p
Rfset(K ohms)=[Period(uS)-0.5]*1.25
300KHZ -----> 3.33uS
R49=3.53K Ohms
PC35
1000p
15
PGD_IN
PR35
1K_1%
PC30
0.22u/10V
Close to Phase 1 Inductor
R568
R570
*0
R565
*0
VCCP_PWRGD
VCORE_ON
+V3.3S
PR37
5.23K_1%
PC31
330p
PC33
330p
PJP7
16
DFB
DROOP
14
13
PC44
1000p
12
VW
RTN
VSEN
VO
PR57
6.81K_1%
PR30
4.53K_1%
0.1u/10V
PC25
X7R
82n
FB
PC39
180p
9
5
6
7
8
PR19
0_0603
PQ13
RQA200N03
NTC
PQ11
RQA200N03
VR_TT#
5
6
7
8
NC
Footprint
1
21
3
2
1
RBIAS
PGD_IN
PC42
15n
FDE
3
2
1
PR528
470K_5%_0402_NTC
PR55
4.02K_1%
3
2
1
26 VR_THERM#
PR42
Recommend 0.45uH for

reduce Vcore ripple
PL504
0.47UH
PR535
0
PR49
147K_1%
499R
X5R
H,L GATE 25-30 mil
VIN
PR50
X5R
PR21
*21K
PR534 and PSI#

PGD_IN
+V3.3S
X5R
820u/2.5V_OSC_DIP_8*9
modify 09/15
DEL
X5R
modify 10/13
PC10
4.7u/25V_1206
5
6
7
8
4
PC13
4.7u/25V_1206
GND_T
3
2
1
41
Throttling temp.
105 degree C
VSS
TOPOPEN-3MM
1
PQ504
RQA130N03
5
6
7
8
39
3V3
ISL6261_MLFP_40
19
PJP12
RQA130N03
PGOOD
18
VDD
PR541
0
modify 08/25
PU3
VIN
20
PQ12
PC20
1u/10V_0603
Close to Phase 1 Inductor
ISL6261_VO
+V3.3S
del
PR530.PR531
PC36
1000p
1
CLOSE
R569
10K
VCC_SENSE 7
R100
10K
VCCP_PWRGD
C129
1u/10V_0805
G
S
PR533
10
R95
330_0603
VSS_SENSE 7
PR532
When test without CPU,

R56 and R57 change to
0 Ohm
Q28
2N7002
+V1.05S
B
Q27
2N3904
E
10

Title
CPU CORE
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
30
Sheet
H
of
32
Q42
RSS090N03
Q62
RSS090N03
1
2
3
+V3.3S
+V5S
VIN
R281
100K
R278
75_0603
R193
220K
Q58
2N7002
R279
220K
+3.3VS_ON 26
Q37
2N7002
G
S
Q60
2N7002
C193
0.1u/25V_0603
X7R
Q39
2N7002
G
D
R284
220K
Q38
2N7002
C171
0.1u/25V_0603
X7R
+V12A
R201
220K
+V12A
R190
75_0603
1
2
3
S
8
7
6
5
+V5A
VIN
R196
100K
D
8
7
6
5
+V3.3A
+5VS_ON 26
Q59
2N7002
R197
220K
R283
220K
+12VS/100mA
+V5A
+V5
R192
100K
R1
100K
R4
100K
R199
100K
Q2
2N7002
+V12S
Q56
AO3413L
S
+V3.3
+V3.3A
Q36
AO3413L
S
+V12A
Q1
AO3413L
S
+5VS_ON
S
G
+5V_ON
R7
220K
26
Q40
2N7002
Q41
2N7002
G
C
+3.3V_ON 26
R208
220K
R207
220K
modify 09/27
DEL Q43,Q44,Q45,Q55,R244,R266,R275,R265,C179
modify 09/27
DEL Q24,Q16,Q17,Q21,R75,R70,R72,R66,C79
B
+V12S
modify 09/29
+V3.3
DEL Q51,R236
R232
300_0603
Z3324
Z3323
Q53
2N7002
D
S
Q54
2N7002
AUX_POWER_OFF G
Q52
2N7002
AUX_OFF#G
AUX_OFF#
Q50
2N7002
R241
100K
6,28
R238
75_0603
Z3319
POWER_OFF G
Z3322
Q49
2N7002
POWER_OFF G
AUX_POWER_OFF
S
Q47
2N7002
+3.3V_ON
G
Z3321
R237
75_0603
+3.3V_ON
Q48
2N7002
POWER_OFF G
26
R240
100K
R234
75_0603
R233
75_0603
Q46
2N7002
G
POWER_OFF
+V5A
Z3318
+V3.3A
LDO5
+V2.5S
+V5
LDO5
R235
75_0603
Title
Voltage SW
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
31
of
32
M31EI1 schematics B phase modified list

modify 09/09
modify 10/06
1.page 22 SATA CONN Pin 5,6 SATA_RXN0,SATA_RXP0 SWAP.

2.page 26 R334,R335,R336 for SW_BD must stuff.
3.page 26 change net CPU_BSEL0 to CPU_BSEL1 and add R605,R606,R607,Q517 with CPU_BSEL2 control.
1.page
2.page
3.page
4.page
5.page
6.page
modify 09/15
D
1.page
2.page
3.page
4.page
5.page
6.page
7.page
8.page
5 change R139 22 ohm to 10K with ICS 9LPR310 rev:B.

16 add R604 with SB CPUSLP# no stuff.
18 DEL R561 8.2K.
22 R597 0 ohm no stuff with WLAN LED.
26 R292,R338 no stuff,R339 must stuff.
26 add R608 4.7K with RF_OFF# pull high.
29 change PR59,PR73 to 2K,82K to improve +1.05V over current.
30 DEL PR534 and PSI# net.
29
05
30
14
power modify 10/07
1.page 27 PR90 56K change 10K

2.page 28 ADD PR100 100K
modify 10/11
1.page
2.page
3.page
4.page
5.page
modify 09/23
1.page
2.page
3.page
4.page
5 del R184,CLK_MCH_QE# no use.

9 R20,R21 NB config12,13 no use,cancel on BOM.
9 R10,R320 with DDR Thermal on module detect,must stuff.
23 C570 no use,cancel on BOM.
26 DEL R356,R357 with CHGLED_G.
26 Q515,Q516,R593,R594 MXM detect circuit no use,cancel on BOM.
change PR38 from 1.5K to 2K,up OCP to 8.8A with +1.8V_DDR use.
R162 (4.3K) was Deleted for Rev B of Clock Gen (9LPR310B)
PC521(4.7uF) no stuff
Add C664,C665 for DDR2 SDRAM 1G/667MHz running 3D Marks stability
14
14
21
21
22
add R356,RT1 with DDR Thermal use.

add E1,E2,E3,E4,E5,E6 EMI with EMI issue.
add R621 with PCIE_LAN_WAKE# pull high.
change Gigalan +V3.3S power to +V3.3A
add D503 with PCIE_LAN_WAKE# to SB GPIO.
modify 10/12
power modify 09/24
1.page 14 add C213,C215,C216,C217 0.1uF with can't boot issue(port 80 step RAM status)
1.page 27 PC509,PC512 ELC 100U/2.5V FOOTPRINT

2.page 28 +V3A PL506 CHOKE 6UH 4.7UH
3.page 28 ADD PC530 0.1U/10V.
4.page 28 PQ19,PQ27 FOOTPRINT SOP-8
5.page 29 change PR58, 1.8K to improve +1.5V over current.
6.page 29 change PR38, 2K to improve +V1.8V_DDR over current.
7.page 29 PL503 FOOTPRINT LAYOUT 6x6 .
8.page 30 change PC512 820U/2.5V .
9.page 30 PL504 0.36 UH 0.47UH
10.page 30 PQ12,PQ504 change footprint.
modify 10/13
1.Top loacation change R621-->R357,D503-->D12,H500-->H26,H501-->H27.

2.Bottom loacation
E4-->E500,E5-->E501,E6-->E502,H4-->H500,H9-->H501,H15-->H502,H17-->H503,H19-->H504.
3.page 7 reserved R88,R89,cancel.
4.page 14 change C106,C108,C110,C558,C571,C566 0.1uF to 1000pF.
5.page 14 add C214,C218,C219,C220,C221,C222,C223,C224 1000pF with EMI DDR High frequency issue.
6.page 14 add C673,C674,C677,C678,C679,C680,C681 1000pF with EMI DDR high frequency issue.
7.page 14 add C225,C226,C227,C672,C675,C676 0.1uF with EMI DDR high frequency issue.
8.page 16 add C184,C207,C209,C210,C663 0.01uF with EMI power plane issue.
9.page 18 add R618 4.7K with LAN G_RST# use.
10.page 21 L15 no stuff,L17,Q30,R180,C166,C167,C169,C170 must stuff with 8055 Gigalan use.
11.page 25 change R337 2.7K to 4.7K for LID# use.
12.page 25 D3,R69,R71 must stuff with CRT DDC Type detect issue.
modify 09/27
1.page
2.page
3.page
4.page
5.page
6.page
18
23
26
31
29
31
add R342 with S5 funtion .

add S500 with USB protect.
add Q76,Q77,R343,R344 charger LED control.
DEL Q43,Q44,Q45,Q55,R244,R266,R275,R265,C179 +V1.5S SW circuit.
change +V1.5 to +V1.5S,+1.5V_ON to +1.5VS_ON.
reserved +V1.8S circuit must del Q24,Q16,Q17,Q21,R75,R70,R72,R66,C79.
modify 10/17
1.page 5 C147,C149 change 33Fp to 27pF,that adjust 14.318 MHZ to meet DQA SPEC.
2.page 16 C135,C139 change 15pF,12pF to 10pF with RTC delay issue.
3.page 23 R2,R5 change 13K to 0 ohm with audio measure issue.
modify 09/28
B
1.TOP component change location

C585-->C212,D503-->D9,R601-->R345,R602-->R346,R603-->R347,R605-->R348,R608-->R349.
2.Bottom component change location
C183-->C666,C188-->C667,PC5-->PC531,PC27-->PC532,C101-->C668,C102-->C669,C103-->C670,C104-->C671.
3.page 22 add R613 mini_card WAKE# pull high 10K to +V3.3S.
4.page 20 reserved R341 with LCDSW pull high resister.
modify 09/29
1.page 31 del Q51,R236 +V1.5 power_off circuit.

modify 09/30
1.page 23 CON507 USB port 2,4 Swap,and del USB port 2 for EMI issue.
2.page 25 CON7.19 net change CODEC_14MHZ to GND.
modify 10/03
1.page 9 del R506,R508,R509,R510,R511 150_1% with CRT,TV function.

2.page 24 del Q31,Q32,Q33,Q35,R174,R182,R191,R194,R188.
3.page 24 add Q78,Q79,Q80,Q81,Q82,Q83,Q84,Q85,D10,D11,R350,R351,R352,R353,R354,R355 with Smart power function.
4.Bottom component change location R342-->R614,R343-->R615,R344-->R616,Q76-->Q518,Q77-->Q519.
power modify 10/04
A
1.page28
2.page28
3.page28
4.page28
ADD PC533 0.1U/10V

PC60,PC82 0.47U/16V CHANGE 0.68U/16V
PR99 1K 619 OHM +V5A OCP
PD10,PD13 BAT54 DEL
modify 10/05
1.page 25 add R337 LID# pull high,to prevent LID floating.

1.page 26 add R356 with CHG_G,reserved R357 EC pin76 with CHG_G use.
Title
ADD&CHANGE NOTICE
Size
Document Number
Date:
SCHEMATIC1
Rev
B
M31EI1
Sheet
1
32
of
32

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5

UNIWILL COMPUTER CORP.

DDR2 RAM BUS

UNIWILL COMPUTER CORP.

SYSTEM BLOCK DIAGRAM

POWER BLOCK DIAGRAM

POWER DIAGRAM & SEQUENCE

LCD Panel ID select

UNIWILL COMPUTER CORP.

GPIO & Power Consumption

Crystal Load Cap = 20P

Crystal external Cap = 33P

BIOS need modified

FSLC FSLB FSLA

UNIWILL COMPUTER CORP.

ICS 9LPR310-CLK GEN.

COMP(3:0) Traces should be at least

Layout:connect test point

UNIWILL COMPUTER CORP.

ROUTE VCCSENSE AND VSSSENSE

UNIWILL COMPUTER CORP.

UNIWILL COMPUTER CORP.

Calistoga 1/6 HOST BUS

del CLK_MCH_QE# net

LOW= Reverse Lane

LOW= Moby Dick

LOW= only SDVO or PCIE

High= SDVO and PCIE x1

UNIWILL COMPUTER CORP.

Calistoga 2/6 DDR,VGA,PCI-E

DDR SYSTEM MEMORY

DDR SYSTEM MEMORY B

UNIWILL COMPUTER CORP.

Calistoga 3/6 DDR_System&Termination

UNIWILL COMPUTER CORP.

Calistoga 4/6 Power pin

UNIWILL COMPUTER CORP.

Calistoga 5/6 Power pin

UNIWILL COMPUTER CORP.

Calistoga 6/6 Gnd & Power TP

DDR2 RVS TYPE

DDR2 STD TYPE

EMI ISSUE Neer NB.

UNIWILL COMPUTER CORP.

IF USE Extenal VGA(C30/C40 EN)

INTERNAL / EXTERNAL SELECT

UNIWILL COMPUTER CORP.

Internal/Extenal VGA Switch

ICH7M INTERNAL VR ENABLE STRAP

Distance between the ICH7M and CAP on

Layout Note: Short pins AH10

Layout Note: CAP needs to placed

UNIWILL COMPUTER CORP.

ICH7M 1/4 RTC,SATA,IDE,CPU

Direct Media Interface

Layout note:PCIE AC coupling

Place within 500mils

UNIWILL COMPUTER CORP.

ICH7M 2/4 PCI-E,PCI,USB

SATA0 and SATA2 ICH6 PULL HI(3.3V)

UNIWILL COMPUTER CORP.

ICH7M 3/4 GPIO,MGT

Layout Note: Place above CAPS within