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REVISION
1.0 1.1
DESCRIPTION
Initial Customer Release Changed R5 (INTRP pull-up) from NC to 4.7K. Deleted R43 and R44 (both re-work resistors are no longer needed).
Revision History KSZ8021/31RNL Eval Board -- Block Diagram KSZ8021/31RNL Device / UTP Interface / RMII Port USB Port for MDC/MDIO Register Access
Document Number
Revision History
Wednesday, July 28, 2010 Sheet
5
Rev 1.1 1 of 4
3.3V LDO
RESET
C C
Jumpers
MDC / MDIO
Pulse H1102
24-pin QFN
B
Magnetics
TX / RX pairs
KSZ8021RNL / KSZ8031RNL
RMII Signals
25 MHz XTAL
50MHz clock input to XI (pin 8) 25MHz crystal / clock input to XI (pin 8) 50MHz RMII reference clock output from REF_CLK (pin 16)
KSZ8031RNL
R17, R19
NOTE: After power-up, both devices can be programmed via MDC/MDIO bus to either 25MHz or 50MHz clock input mode.
Document Number
Rev 1.1 4
of
SYS_CLK_BTB TP1
1.8V_2.5V RMII_5.0V
5 R1 + BYP/ADJ 4 C5 1 3 470pF 1.50K 10uF 0.1uF C4 C3
5.0V U3 JP1
1 2 3 1 C6 + 47uF/16V TANT C C9 0.1uF
3.3V
1. Close jumpers (J1, J2, J3). 2. Program KSZ8021/31RNL for RMII Back-to-Back mode by setting register 22 (16h) bit [6] to '1'.
TP2
GND
VIN GND EN
VOUT
2 C2 3 0.1uF
USB_5.0V
MIC39100-3.3WS / SOT-223
IN OUT 3 C7 + 47uF / TANT C C8 0.1uF
J1 J2 J3
GND
3X1
R2 R3 1.50K
TAB
JP2
3X1
GND
MDC MDIO
TP3 TP4
For Adjustable Voltage Regulator (MIC5207YM5), use following formula to set VOUT.
680
Rsel = R2 or R3
RMII Mode
VDDA_3.3 VDDIO
The RMII signal connections between KSZ8021/31RNL PHY and external MAC are shown in the table to the right. For RMII mode with 25MHz XTAL input and 50MHz RMII Reference Clock output, 1.8V_2.5V : close pins 1, 2 3.3V : close pins 2, 3 1. Connect J4 (RMII Port) to board with RMII MAC (e.g. Micrel KSZ8893MQL Eval Board). 2. Program KSZ8021/31RNL for RMII mode with 25MHz XTAL input and 50MHz RMII Reference Clock output. 3. Program other KSZ8021/31RNL configuration settings (ISOLATE, B-CAST_OFF, NWAYEN, SPEED, DUPLEX) to desired settings.
3.3V
Notes:
1. KSZ8021/31RNL has a Paddle Ground on bottom side of chip. Refer to datasheet for mechanical dimensions. 2. KSZ8021/31RNL provides the 1.2V supply for VDD_1.2 (pin 1). Decouple 1.2V power rail as shown. 3. Place components (Y1, C16, C17, C18, R15) close to respective pins of U1.
C10 C11 RST# LED0 2.2uF
STEWARD HI1206N101R-00
FB1 1 FBEAD 2
3.3V
1.8V_2.5V
JP3
1 2 3
R4 220 2
D1
POWER_ON LED
3X1
VDD_1.2
TXD1 TXD0 TXEN + 0.1uF
Board
Input Input
VDDIO
VDDIO
TP5
LED Mode
LED0
[00]
LINK/ACT
[01]
LINK
C14
VDDA_3.3
25 24 23 22 21 20 19 + C12 22uF C13 0.1uF INTRP R5 4.7K
C15 22uF
3.3V
LED1 1 LEDx1 2 R8 220 LED0
0.1uF
P_GND
RMII_5.0V
TXD1 RXM RXP TXM TXP 1 2 3 4 5 6 VDD_1.2 VDDA_3.3 RXM RXP TXM TXP INTRP RXER REF_CLK CRS_DV VDDIO RXD0 18 17 16 15 14 13 INTRP RXER REF_CLK CRS_DV RXD0 TXD0 TXEN
R6 R7 R9
0 0 0
J4
VCC CRS COL TXD3 TXD2 TXD1 TXD0 TX_EN TX_CLK TX_ER RX_ER RX_CLK RX_DV RXD0 RXD1 RXD2 RXD3 MDC MDIO VCC VCC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCC 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
System Clock options Layout SMD footprint ECS-3953M-250-BN (25MHz 50ppm) ECS-3953M-500-BN (50MHz 50ppm)
B
TXD1_RMII TXD0_RMII TXEN_RMII RXER_RMII REF_CLK_RMII CRS_DV_RMII RXD0_RMII RXD1_RMII MDC MDIO
REF_CLK
U1 KSZ8021RNL / KSZ8031RNL
RXD1 MDC MDIO MDC MDIO (4) (4)
7 8 9 10 11 12
Y1 25MHz
22pF
VDDIO
4 1 + C19 10uF C20 10nF
VDDIO
Y2
VCC NC OUT GND 3
25/50MHz +/-50ppm
NC / 0 SYS_CLK SYS_CLK_BTB
ENET_CGND
TH1 TH2
TP10 GND
TP11 GND
J5
A
8 7 6 5 4 3 2 1
75 75 C21
R23 R25
75 75
CMT CMR
16 15 14 11 10 9
TXP
VDDIO
1000pF / 2kV
RJ-45 Jack
1
STEWARD HI1206N101R-00
GND
CMR RX-
BAV16W-7 SOD-123
S1 2 4
Place ferrite bead ground bridge for ENET_CGND to GND (signal ground) return close to GND at input power to board.
Rev 1.1 4
Sheet
of
5.0V
U4
MIC5207-5.0YM5
1 VIN GND EN BYP/ADJ 4
C34 470pF
STEWARD HI1206N101R-00
FB3
5V_Reg
3.3V
STEWARD HI1206N101R-00
FB4
VOUT
5
C26 + 10uF / TANT A 0.1uF C27
1
FBEAD
1
FBEAD
2
C32 C33
C25
D
2 3
1.0uF
C35
27pF XTIN
MIC5207-5.0YM5 has very low dropout voltage (typically 165mV @ 150mA). FTDI FT2232D can operate down to +4.35V for its 5V input power (5V_USB).
C36 27pF
Y3 6MHz
XTOUT
3.3V_USB
VDDIO 3.3V_USB
R27 R28 4.7K R29 4.7K
C
5V_USB
C
USB_5.0V
JP4
1 2 3
R33
U5
TI PCA9306
1 2 3 4 GND VREF1 SCL1 SDA1 EN VREF2 SCL2 SDA2 8 7 6 5
200K
3X1
USB_5.0V (USB Port Powered) * close JP4 pins 2, 3 * close JP5 pins 1, 2
R34
JP5
1 2 3
48 47 46 45 44 43 42 41 40 39 38 37
3.3V_USB
U6 FTDI FT2232D
EECS TEST AVCC AGND XTOUT XTIN VCC PWREN# NC NC NC NC
MDIO_PHY
VSSOP-DCU
R35 10K
RMII_5.0V (RMII Port Powered) * close JP4 pins 1, 2 * close JP5 pins 2, 3
3X1
R36 10K
B
C39 33nF
USB_5.0V
2
1 2 3 4 5 6 7 8 9 10 11 12
EESK EEDATA VCC RESET# RSTOUT# 3V3OUT USBDP USBDM GND NOT_USED GPIOH3 GPIOH2
36 35 34 33 32 31 30 29 28 27 26 25
3.3V_USB
R37 10K
B
FB5 FBEAD
STEWARD HI1206N101R-00
R38
GPIOH1 VCCIOA GPIOH0 GPIOL3 GPIOL2 GND GPIOL1 GPIOL0 TMS/CS TDO/D1 TDI/D0 TCK/SK
USB Port - MDC / MDIO Access * close JP6, JP7 RMII Port - MDC / MDIO Access * open JP6, JP7
3.3V_USB
10K
C40
CN1
CN-USB
1 2 3 4
R40 R41
10nF JP6 R39 27 0805 27 0805 1.5K RSTOUT# USBDM USBDP R42 0 MDC_USB MDIO_USB MDC_PHY MDIO_PHY
13 14 15 16 17 18 19 20 21 22 23 24
1 1
JP7
2 2
MDC MDIO
MDC MDIO
(3) (3)
5
A
STEWARD HI1206N101R-00
FB6
1
FBEAD USB_CGND
Rev 1.1 of 4